148 строки
3.5 KiB
C
148 строки
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* aQuantia Corporation Network Driver
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* Copyright (C) 2018-2019 aQuantia Corporation. All rights reserved
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*/
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#include "aq_phy.h"
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bool aq_mdio_busy_wait(struct aq_hw_s *aq_hw)
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{
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int err = 0;
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u32 val;
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err = readx_poll_timeout_atomic(hw_atl_mdio_busy_get, aq_hw,
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val, val == 0U, 10U, 100000U);
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if (err < 0)
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return false;
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return true;
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}
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u16 aq_mdio_read_word(struct aq_hw_s *aq_hw, u16 mmd, u16 addr)
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{
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u16 phy_addr = aq_hw->phy_id << 5 | mmd;
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/* Set Address register. */
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hw_atl_glb_mdio_iface4_set(aq_hw, (addr & HW_ATL_MDIO_ADDRESS_MSK) <<
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HW_ATL_MDIO_ADDRESS_SHIFT);
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/* Send Address command. */
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hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |
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(3 << HW_ATL_MDIO_OP_MODE_SHIFT) |
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((phy_addr & HW_ATL_MDIO_PHY_ADDRESS_MSK) <<
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HW_ATL_MDIO_PHY_ADDRESS_SHIFT));
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aq_mdio_busy_wait(aq_hw);
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/* Send Read command. */
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hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |
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(1 << HW_ATL_MDIO_OP_MODE_SHIFT) |
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((phy_addr & HW_ATL_MDIO_PHY_ADDRESS_MSK) <<
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HW_ATL_MDIO_PHY_ADDRESS_SHIFT));
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/* Read result. */
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aq_mdio_busy_wait(aq_hw);
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return (u16)hw_atl_glb_mdio_iface5_get(aq_hw);
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}
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void aq_mdio_write_word(struct aq_hw_s *aq_hw, u16 mmd, u16 addr, u16 data)
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{
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u16 phy_addr = aq_hw->phy_id << 5 | mmd;
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/* Set Address register. */
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hw_atl_glb_mdio_iface4_set(aq_hw, (addr & HW_ATL_MDIO_ADDRESS_MSK) <<
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HW_ATL_MDIO_ADDRESS_SHIFT);
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/* Send Address command. */
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hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |
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(3 << HW_ATL_MDIO_OP_MODE_SHIFT) |
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((phy_addr & HW_ATL_MDIO_PHY_ADDRESS_MSK) <<
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HW_ATL_MDIO_PHY_ADDRESS_SHIFT));
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aq_mdio_busy_wait(aq_hw);
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hw_atl_glb_mdio_iface3_set(aq_hw, (data & HW_ATL_MDIO_WRITE_DATA_MSK) <<
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HW_ATL_MDIO_WRITE_DATA_SHIFT);
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/* Send Write command. */
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hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |
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(2 << HW_ATL_MDIO_OP_MODE_SHIFT) |
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((phy_addr & HW_ATL_MDIO_PHY_ADDRESS_MSK) <<
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HW_ATL_MDIO_PHY_ADDRESS_SHIFT));
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aq_mdio_busy_wait(aq_hw);
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}
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u16 aq_phy_read_reg(struct aq_hw_s *aq_hw, u16 mmd, u16 address)
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{
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int err = 0;
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u32 val;
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err = readx_poll_timeout_atomic(hw_atl_sem_mdio_get, aq_hw,
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val, val == 1U, 10U, 100000U);
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if (err < 0) {
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err = 0xffff;
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goto err_exit;
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}
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err = aq_mdio_read_word(aq_hw, mmd, address);
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hw_atl_reg_glb_cpu_sem_set(aq_hw, 1U, HW_ATL_FW_SM_MDIO);
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err_exit:
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return err;
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}
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void aq_phy_write_reg(struct aq_hw_s *aq_hw, u16 mmd, u16 address, u16 data)
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{
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int err = 0;
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u32 val;
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err = readx_poll_timeout_atomic(hw_atl_sem_mdio_get, aq_hw,
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val, val == 1U, 10U, 100000U);
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if (err < 0)
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return;
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aq_mdio_write_word(aq_hw, mmd, address, data);
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hw_atl_reg_glb_cpu_sem_set(aq_hw, 1U, HW_ATL_FW_SM_MDIO);
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}
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bool aq_phy_init_phy_id(struct aq_hw_s *aq_hw)
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{
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u16 val;
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for (aq_hw->phy_id = 0; aq_hw->phy_id < HW_ATL_PHY_ID_MAX;
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++aq_hw->phy_id) {
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/* PMA Standard Device Identifier 2: Address 1.3 */
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val = aq_phy_read_reg(aq_hw, MDIO_MMD_PMAPMD, 3);
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if (val != 0xffff)
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return true;
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}
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return false;
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}
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bool aq_phy_init(struct aq_hw_s *aq_hw)
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{
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u32 dev_id;
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if (aq_hw->phy_id == HW_ATL_PHY_ID_MAX)
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if (!aq_phy_init_phy_id(aq_hw))
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return false;
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/* PMA Standard Device Identifier:
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* Address 1.2 = MSW,
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* Address 1.3 = LSW
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*/
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dev_id = aq_phy_read_reg(aq_hw, MDIO_MMD_PMAPMD, 2);
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dev_id <<= 16;
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dev_id |= aq_phy_read_reg(aq_hw, MDIO_MMD_PMAPMD, 3);
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if (dev_id == 0xffffffff) {
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aq_hw->phy_id = HW_ATL_PHY_ID_MAX;
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return false;
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}
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return true;
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}
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