- Make gpio gate clks propagate rate setting up to parent
* clk-gpio-flags:
clk: clk-gpio: propagate rate change to parent
* clk-tegra: (23 commits)
clk: tegra: Use match_string() helper to simplify the code
clk: tegra: Fix build error without CONFIG_PM_SLEEP
clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP
clk: tegra: Optimize PLLX restore on Tegra20/30
clk: tegra: Add suspend and resume support on Tegra210
clk: tegra: Share clk and rst register defines with Tegra clock driver
clk: tegra: Use fence_udelay() during PLLU init
clk: tegra: clk-dfll: Add suspend and resume support
clk: tegra: clk-super: Add restore-context support
clk: tegra: clk-super: Fix to enable PLLP branches to CPU
clk: tegra: periph: Add restore_context support
clk: tegra: Support for OSC context save and restore
clk: tegra: pll: Save and restore pll context
clk: tegra: pllout: Save and restore pllout context
clk: tegra: divider: Save and restore divider rate
clk: tegra: Reimplement SOR clocks on Tegra210
clk: tegra: Reimplement SOR clock on Tegra124
clk: tegra: Rename sor0_lvds to sor0_out
clk: tegra: Move SOR0 implementation to Tegra124
clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC
...
* clk-rockchip:
clk: rockchip: protect the pclk_usb_grf as critical on px30
clk: rockchip: add video-related niu clocks as critical on px30
clk: rockchip: move px30 critical clocks to correct clock controller
clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc
clk: rockchip: Add div50 clock-ids for sdmmc on px30 and nandc
clk: rockchip: make clk_half_divider_ops static
* clk-sprd:
clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle()
* clk-pxa:
clk: pxa: fix one of the pxa RTC clocks
dabedfede3