415 строки
11 KiB
C
415 строки
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#include <linux/edac.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/soc/qcom/llcc-qcom.h>
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#include "edac_mc.h"
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#include "edac_device.h"
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#define EDAC_LLCC "qcom_llcc"
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#define LLCC_ERP_PANIC_ON_UE 1
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#define TRP_SYN_REG_CNT 6
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#define DRP_SYN_REG_CNT 8
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#define LLCC_COMMON_STATUS0 0x0003000c
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#define LLCC_LB_CNT_MASK GENMASK(31, 28)
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#define LLCC_LB_CNT_SHIFT 28
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/* Single & double bit syndrome register offsets */
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#define TRP_ECC_SB_ERR_SYN0 0x0002304c
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#define TRP_ECC_DB_ERR_SYN0 0x00020370
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#define DRP_ECC_SB_ERR_SYN0 0x0004204c
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#define DRP_ECC_DB_ERR_SYN0 0x00042070
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/* Error register offsets */
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#define TRP_ECC_ERROR_STATUS1 0x00020348
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#define TRP_ECC_ERROR_STATUS0 0x00020344
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#define DRP_ECC_ERROR_STATUS1 0x00042048
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#define DRP_ECC_ERROR_STATUS0 0x00042044
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/* TRP, DRP interrupt register offsets */
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#define DRP_INTERRUPT_STATUS 0x00041000
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#define TRP_INTERRUPT_0_STATUS 0x00020480
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#define DRP_INTERRUPT_CLEAR 0x00041008
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#define DRP_ECC_ERROR_CNTR_CLEAR 0x00040004
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#define TRP_INTERRUPT_0_CLEAR 0x00020484
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#define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440
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/* Mask and shift macros */
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#define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0)
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#define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16)
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#define ECC_DB_ERR_WAYS_SHIFT BIT(4)
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#define ECC_SB_ERR_COUNT_MASK GENMASK(23, 16)
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#define ECC_SB_ERR_COUNT_SHIFT BIT(4)
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#define ECC_SB_ERR_WAYS_MASK GENMASK(15, 0)
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#define SB_ECC_ERROR BIT(0)
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#define DB_ECC_ERROR BIT(1)
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#define DRP_TRP_INT_CLEAR GENMASK(1, 0)
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#define DRP_TRP_CNT_CLEAR GENMASK(1, 0)
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/* Config registers offsets*/
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#define DRP_ECC_ERROR_CFG 0x00040000
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/* Tag RAM, Data RAM interrupt register offsets */
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#define CMN_INTERRUPT_0_ENABLE 0x0003001c
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#define CMN_INTERRUPT_2_ENABLE 0x0003003c
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#define TRP_INTERRUPT_0_ENABLE 0x00020488
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#define DRP_INTERRUPT_ENABLE 0x0004100c
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#define SB_ERROR_THRESHOLD 0x1
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#define SB_ERROR_THRESHOLD_SHIFT 24
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#define SB_DB_TRP_INTERRUPT_ENABLE 0x3
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#define TRP0_INTERRUPT_ENABLE 0x1
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#define DRP0_INTERRUPT_ENABLE BIT(6)
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#define SB_DB_DRP_INTERRUPT_ENABLE 0x3
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enum {
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LLCC_DRAM_CE = 0,
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LLCC_DRAM_UE,
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LLCC_TRAM_CE,
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LLCC_TRAM_UE,
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};
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static const struct llcc_edac_reg_data edac_reg_data[] = {
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[LLCC_DRAM_CE] = {
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.name = "DRAM Single-bit",
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.synd_reg = DRP_ECC_SB_ERR_SYN0,
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.count_status_reg = DRP_ECC_ERROR_STATUS1,
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.ways_status_reg = DRP_ECC_ERROR_STATUS0,
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.reg_cnt = DRP_SYN_REG_CNT,
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.count_mask = ECC_SB_ERR_COUNT_MASK,
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.ways_mask = ECC_SB_ERR_WAYS_MASK,
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.count_shift = ECC_SB_ERR_COUNT_SHIFT,
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},
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[LLCC_DRAM_UE] = {
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.name = "DRAM Double-bit",
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.synd_reg = DRP_ECC_DB_ERR_SYN0,
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.count_status_reg = DRP_ECC_ERROR_STATUS1,
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.ways_status_reg = DRP_ECC_ERROR_STATUS0,
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.reg_cnt = DRP_SYN_REG_CNT,
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.count_mask = ECC_DB_ERR_COUNT_MASK,
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.ways_mask = ECC_DB_ERR_WAYS_MASK,
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.ways_shift = ECC_DB_ERR_WAYS_SHIFT,
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},
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[LLCC_TRAM_CE] = {
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.name = "TRAM Single-bit",
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.synd_reg = TRP_ECC_SB_ERR_SYN0,
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.count_status_reg = TRP_ECC_ERROR_STATUS1,
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.ways_status_reg = TRP_ECC_ERROR_STATUS0,
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.reg_cnt = TRP_SYN_REG_CNT,
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.count_mask = ECC_SB_ERR_COUNT_MASK,
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.ways_mask = ECC_SB_ERR_WAYS_MASK,
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.count_shift = ECC_SB_ERR_COUNT_SHIFT,
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},
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[LLCC_TRAM_UE] = {
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.name = "TRAM Double-bit",
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.synd_reg = TRP_ECC_DB_ERR_SYN0,
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.count_status_reg = TRP_ECC_ERROR_STATUS1,
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.ways_status_reg = TRP_ECC_ERROR_STATUS0,
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.reg_cnt = TRP_SYN_REG_CNT,
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.count_mask = ECC_DB_ERR_COUNT_MASK,
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.ways_mask = ECC_DB_ERR_WAYS_MASK,
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.ways_shift = ECC_DB_ERR_WAYS_SHIFT,
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},
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};
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static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
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{
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u32 sb_err_threshold;
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int ret;
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/*
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* Configure interrupt enable registers such that Tag, Data RAM related
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* interrupts are propagated to interrupt controller for servicing
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*/
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ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
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TRP0_INTERRUPT_ENABLE,
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TRP0_INTERRUPT_ENABLE);
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if (ret)
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return ret;
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ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
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SB_DB_TRP_INTERRUPT_ENABLE,
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SB_DB_TRP_INTERRUPT_ENABLE);
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if (ret)
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return ret;
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sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
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ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
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sb_err_threshold);
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if (ret)
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return ret;
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ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
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DRP0_INTERRUPT_ENABLE,
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DRP0_INTERRUPT_ENABLE);
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if (ret)
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return ret;
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ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
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SB_DB_DRP_INTERRUPT_ENABLE);
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return ret;
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}
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/* Clear the error interrupt and counter registers */
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static int
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qcom_llcc_clear_error_status(int err_type, struct llcc_drv_data *drv)
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{
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int ret = 0;
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switch (err_type) {
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case LLCC_DRAM_CE:
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case LLCC_DRAM_UE:
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ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
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DRP_TRP_INT_CLEAR);
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if (ret)
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return ret;
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ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
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DRP_TRP_CNT_CLEAR);
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if (ret)
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return ret;
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break;
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case LLCC_TRAM_CE:
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case LLCC_TRAM_UE:
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ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
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DRP_TRP_INT_CLEAR);
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if (ret)
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return ret;
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ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
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DRP_TRP_CNT_CLEAR);
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if (ret)
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return ret;
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break;
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default:
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ret = -EINVAL;
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edac_printk(KERN_CRIT, EDAC_LLCC, "Unexpected error type: %d\n",
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err_type);
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}
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return ret;
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}
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/* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/
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static int
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dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type)
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{
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struct llcc_edac_reg_data reg_data = edac_reg_data[err_type];
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int err_cnt, err_ways, ret, i;
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u32 synd_reg, synd_val;
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for (i = 0; i < reg_data.reg_cnt; i++) {
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synd_reg = reg_data.synd_reg + (i * 4);
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ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
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&synd_val);
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if (ret)
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goto clear;
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edac_printk(KERN_CRIT, EDAC_LLCC, "%s: ECC_SYN%d: 0x%8x\n",
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reg_data.name, i, synd_val);
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}
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ret = regmap_read(drv->regmap,
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drv->offsets[bank] + reg_data.count_status_reg,
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&err_cnt);
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if (ret)
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goto clear;
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err_cnt &= reg_data.count_mask;
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err_cnt >>= reg_data.count_shift;
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edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n",
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reg_data.name, err_cnt);
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ret = regmap_read(drv->regmap,
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drv->offsets[bank] + reg_data.ways_status_reg,
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&err_ways);
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if (ret)
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goto clear;
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err_ways &= reg_data.ways_mask;
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err_ways >>= reg_data.ways_shift;
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edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error ways: 0x%4x\n",
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reg_data.name, err_ways);
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clear:
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return qcom_llcc_clear_error_status(err_type, drv);
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}
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static int
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dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank)
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{
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struct llcc_drv_data *drv = edev_ctl->pvt_info;
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int ret;
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ret = dump_syn_reg_values(drv, bank, err_type);
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if (ret)
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return ret;
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switch (err_type) {
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case LLCC_DRAM_CE:
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edac_device_handle_ce(edev_ctl, 0, bank,
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"LLCC Data RAM correctable Error");
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break;
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case LLCC_DRAM_UE:
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edac_device_handle_ue(edev_ctl, 0, bank,
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"LLCC Data RAM uncorrectable Error");
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break;
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case LLCC_TRAM_CE:
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edac_device_handle_ce(edev_ctl, 0, bank,
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"LLCC Tag RAM correctable Error");
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break;
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case LLCC_TRAM_UE:
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edac_device_handle_ue(edev_ctl, 0, bank,
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"LLCC Tag RAM uncorrectable Error");
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break;
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default:
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ret = -EINVAL;
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edac_printk(KERN_CRIT, EDAC_LLCC, "Unexpected error type: %d\n",
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err_type);
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}
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return ret;
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}
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static irqreturn_t
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llcc_ecc_irq_handler(int irq, void *edev_ctl)
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{
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struct edac_device_ctl_info *edac_dev_ctl = edev_ctl;
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struct llcc_drv_data *drv = edac_dev_ctl->pvt_info;
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irqreturn_t irq_rc = IRQ_NONE;
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u32 drp_error, trp_error, i;
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bool irq_handled;
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int ret;
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/* Iterate over the banks and look for Tag RAM or Data RAM errors */
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for (i = 0; i < drv->num_banks; i++) {
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ret = regmap_read(drv->regmap,
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drv->offsets[i] + DRP_INTERRUPT_STATUS,
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&drp_error);
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if (!ret && (drp_error & SB_ECC_ERROR)) {
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edac_printk(KERN_CRIT, EDAC_LLCC,
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"Single Bit Error detected in Data RAM\n");
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ret = dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
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} else if (!ret && (drp_error & DB_ECC_ERROR)) {
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edac_printk(KERN_CRIT, EDAC_LLCC,
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"Double Bit Error detected in Data RAM\n");
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ret = dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
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}
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if (!ret)
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irq_handled = true;
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ret = regmap_read(drv->regmap,
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drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
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&trp_error);
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if (!ret && (trp_error & SB_ECC_ERROR)) {
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edac_printk(KERN_CRIT, EDAC_LLCC,
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"Single Bit Error detected in Tag RAM\n");
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ret = dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
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} else if (!ret && (trp_error & DB_ECC_ERROR)) {
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edac_printk(KERN_CRIT, EDAC_LLCC,
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"Double Bit Error detected in Tag RAM\n");
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ret = dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
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}
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if (!ret)
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irq_handled = true;
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}
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if (irq_handled)
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irq_rc = IRQ_HANDLED;
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return irq_rc;
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}
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static int qcom_llcc_edac_probe(struct platform_device *pdev)
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{
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struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
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struct edac_device_ctl_info *edev_ctl;
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struct device *dev = &pdev->dev;
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int ecc_irq;
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int rc;
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rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
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if (rc)
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return rc;
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/* Allocate edac control info */
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edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",
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llcc_driv_data->num_banks, 1,
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NULL, 0,
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edac_device_alloc_index());
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if (!edev_ctl)
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return -ENOMEM;
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edev_ctl->dev = dev;
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edev_ctl->mod_name = dev_name(dev);
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edev_ctl->dev_name = dev_name(dev);
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edev_ctl->ctl_name = "llcc";
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edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
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edev_ctl->pvt_info = llcc_driv_data;
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rc = edac_device_add_device(edev_ctl);
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if (rc)
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goto out_mem;
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platform_set_drvdata(pdev, edev_ctl);
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/* Request for ecc irq */
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ecc_irq = llcc_driv_data->ecc_irq;
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if (ecc_irq < 0) {
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rc = -ENODEV;
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goto out_dev;
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}
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rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
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IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl);
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if (rc)
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goto out_dev;
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return rc;
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out_dev:
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edac_device_del_device(edev_ctl->dev);
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out_mem:
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edac_device_free_ctl_info(edev_ctl);
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return rc;
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}
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static int qcom_llcc_edac_remove(struct platform_device *pdev)
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{
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struct edac_device_ctl_info *edev_ctl = dev_get_drvdata(&pdev->dev);
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edac_device_del_device(edev_ctl->dev);
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edac_device_free_ctl_info(edev_ctl);
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return 0;
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}
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static struct platform_driver qcom_llcc_edac_driver = {
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.probe = qcom_llcc_edac_probe,
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.remove = qcom_llcc_edac_remove,
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.driver = {
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.name = "qcom_llcc_edac",
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},
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};
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module_platform_driver(qcom_llcc_edac_driver);
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MODULE_DESCRIPTION("QCOM EDAC driver");
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MODULE_LICENSE("GPL v2");
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