847 строки
21 KiB
C
847 строки
21 KiB
C
/*********************************************************************
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*
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* Filename: via-ircc.h
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* Version: 1.0
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* Description: Driver for the VIA VT8231/VT8233 IrDA chipsets
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* Author: VIA Technologies, inc
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* Date : 08/06/2003
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Copyright (c) 1998-2003 VIA Technologies, Inc.
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This program is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free Software
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Foundation; either version 2, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, see <http://www.gnu.org/licenses/>.
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* Comment:
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* jul/08/2002 : Rx buffer length should use Rx ring ptr.
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* Oct/28/2002 : Add SB id for 3147 and 3177.
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* jul/09/2002 : only implement two kind of dongle currently.
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* Oct/02/2002 : work on VT8231 and VT8233 .
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* Aug/06/2003 : change driver format to pci driver .
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********************************************************************/
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#ifndef via_IRCC_H
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#define via_IRCC_H
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#include <linux/spinlock.h>
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#include <linux/pm.h>
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#include <linux/types.h>
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#include <asm/io.h>
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#define MAX_TX_WINDOW 7
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#define MAX_RX_WINDOW 7
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struct st_fifo_entry {
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int status;
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int len;
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};
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struct st_fifo {
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struct st_fifo_entry entries[MAX_RX_WINDOW + 2];
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int pending_bytes;
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int head;
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int tail;
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int len;
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};
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struct frame_cb {
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void *start; /* Start of frame in DMA mem */
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int len; /* Length of frame in DMA mem */
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};
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struct tx_fifo {
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struct frame_cb queue[MAX_TX_WINDOW + 2]; /* Info about frames in queue */
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int ptr; /* Currently being sent */
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int len; /* Length of queue */
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int free; /* Next free slot */
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void *tail; /* Next free start in DMA mem */
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};
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struct eventflag // for keeping track of Interrupt Events
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{
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//--------tx part
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unsigned char TxFIFOUnderRun;
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unsigned char EOMessage;
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unsigned char TxFIFOReady;
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unsigned char EarlyEOM;
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//--------rx part
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unsigned char PHYErr;
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unsigned char CRCErr;
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unsigned char RxFIFOOverRun;
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unsigned char EOPacket;
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unsigned char RxAvail;
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unsigned char TooLargePacket;
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unsigned char SIRBad;
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//--------unknown
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unsigned char Unknown;
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//----------
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unsigned char TimeOut;
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unsigned char RxDMATC;
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unsigned char TxDMATC;
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};
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/* Private data for each instance */
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struct via_ircc_cb {
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struct st_fifo st_fifo; /* Info about received frames */
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struct tx_fifo tx_fifo; /* Info about frames to be transmitted */
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struct net_device *netdev; /* Yes! we are some kind of netdevice */
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struct irlap_cb *irlap; /* The link layer we are binded to */
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struct qos_info qos; /* QoS capabilities for this device */
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chipio_t io; /* IrDA controller information */
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iobuff_t tx_buff; /* Transmit buffer */
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iobuff_t rx_buff; /* Receive buffer */
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dma_addr_t tx_buff_dma;
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dma_addr_t rx_buff_dma;
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__u8 ier; /* Interrupt enable register */
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spinlock_t lock; /* For serializing operations */
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__u32 flags; /* Interface flags */
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__u32 new_speed;
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int index; /* Instance index */
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struct eventflag EventFlag;
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unsigned int chip_id; /* to remember chip id */
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unsigned int RetryCount;
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unsigned int RxDataReady;
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unsigned int RxLastCount;
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};
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//---------I=Infrared, H=Host, M=Misc, T=Tx, R=Rx, ST=Status,
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// CF=Config, CT=Control, L=Low, H=High, C=Count
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#define I_CF_L_0 0x10
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#define I_CF_H_0 0x11
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#define I_SIR_BOF 0x12
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#define I_SIR_EOF 0x13
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#define I_ST_CT_0 0x15
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#define I_ST_L_1 0x16
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#define I_ST_H_1 0x17
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#define I_CF_L_1 0x18
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#define I_CF_H_1 0x19
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#define I_CF_L_2 0x1a
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#define I_CF_H_2 0x1b
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#define I_CF_3 0x1e
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#define H_CT 0x20
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#define H_ST 0x21
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#define M_CT 0x22
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#define TX_CT_1 0x23
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#define TX_CT_2 0x24
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#define TX_ST 0x25
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#define RX_CT 0x26
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#define RX_ST 0x27
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#define RESET 0x28
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#define P_ADDR 0x29
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#define RX_C_L 0x2a
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#define RX_C_H 0x2b
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#define RX_P_L 0x2c
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#define RX_P_H 0x2d
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#define TX_C_L 0x2e
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#define TX_C_H 0x2f
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#define TIMER 0x32
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#define I_CF_4 0x33
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#define I_T_C_L 0x34
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#define I_T_C_H 0x35
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#define VERSION 0x3f
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//-------------------------------
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#define StartAddr 0x10 // the first register address
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#define EndAddr 0x3f // the last register address
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#define GetBit(val,bit) val = (unsigned char) ((val>>bit) & 0x1)
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// Returns the bit
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#define SetBit(val,bit) val= (unsigned char ) (val | (0x1 << bit))
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// Sets bit to 1
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#define ResetBit(val,bit) val= (unsigned char ) (val & ~(0x1 << bit))
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// Sets bit to 0
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#define OFF 0
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#define ON 1
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#define DMA_TX_MODE 0x08
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#define DMA_RX_MODE 0x04
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#define DMA1 0
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#define DMA2 0xc0
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#define MASK1 DMA1+0x0a
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#define MASK2 DMA2+0x14
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#define Clk_bit 0x40
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#define Tx_bit 0x01
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#define Rd_Valid 0x08
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#define RxBit 0x08
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static void DisableDmaChannel(unsigned int channel)
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{
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switch (channel) { // 8 Bit DMA channels DMAC1
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case 0:
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outb(4, MASK1); //mask channel 0
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break;
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case 1:
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outb(5, MASK1); //Mask channel 1
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break;
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case 2:
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outb(6, MASK1); //Mask channel 2
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break;
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case 3:
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outb(7, MASK1); //Mask channel 3
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break;
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case 5:
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outb(5, MASK2); //Mask channel 5
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break;
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case 6:
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outb(6, MASK2); //Mask channel 6
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break;
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case 7:
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outb(7, MASK2); //Mask channel 7
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break;
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default:
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break;
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}
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}
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static unsigned char ReadLPCReg(int iRegNum)
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{
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unsigned char iVal;
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outb(0x87, 0x2e);
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outb(0x87, 0x2e);
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outb(iRegNum, 0x2e);
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iVal = inb(0x2f);
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outb(0xaa, 0x2e);
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return iVal;
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}
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static void WriteLPCReg(int iRegNum, unsigned char iVal)
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{
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outb(0x87, 0x2e);
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outb(0x87, 0x2e);
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outb(iRegNum, 0x2e);
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outb(iVal, 0x2f);
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outb(0xAA, 0x2e);
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}
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static __u8 ReadReg(unsigned int BaseAddr, int iRegNum)
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{
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return (__u8) inb(BaseAddr + iRegNum);
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}
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static void WriteReg(unsigned int BaseAddr, int iRegNum, unsigned char iVal)
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{
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outb(iVal, BaseAddr + iRegNum);
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}
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static int WriteRegBit(unsigned int BaseAddr, unsigned char RegNum,
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unsigned char BitPos, unsigned char value)
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{
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__u8 Rtemp, Wtemp;
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if (BitPos > 7) {
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return -1;
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}
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if ((RegNum < StartAddr) || (RegNum > EndAddr))
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return -1;
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Rtemp = ReadReg(BaseAddr, RegNum);
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if (value == 0)
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Wtemp = ResetBit(Rtemp, BitPos);
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else {
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if (value == 1)
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Wtemp = SetBit(Rtemp, BitPos);
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else
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return -1;
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}
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WriteReg(BaseAddr, RegNum, Wtemp);
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return 0;
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}
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static __u8 CheckRegBit(unsigned int BaseAddr, unsigned char RegNum,
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unsigned char BitPos)
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{
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__u8 temp;
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if (BitPos > 7)
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return 0xff;
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if ((RegNum < StartAddr) || (RegNum > EndAddr)) {
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// printf("what is the register %x!\n",RegNum);
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}
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temp = ReadReg(BaseAddr, RegNum);
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return GetBit(temp, BitPos);
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}
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static void SetMaxRxPacketSize(__u16 iobase, __u16 size)
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{
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__u16 low, high;
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if ((size & 0xe000) == 0) {
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low = size & 0x00ff;
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high = (size & 0x1f00) >> 8;
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WriteReg(iobase, I_CF_L_2, low);
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WriteReg(iobase, I_CF_H_2, high);
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}
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}
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//for both Rx and Tx
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static void SetFIFO(__u16 iobase, __u16 value)
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{
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switch (value) {
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case 128:
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WriteRegBit(iobase, 0x11, 0, 0);
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WriteRegBit(iobase, 0x11, 7, 1);
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break;
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case 64:
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WriteRegBit(iobase, 0x11, 0, 0);
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WriteRegBit(iobase, 0x11, 7, 0);
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break;
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case 32:
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WriteRegBit(iobase, 0x11, 0, 1);
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WriteRegBit(iobase, 0x11, 7, 0);
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break;
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default:
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WriteRegBit(iobase, 0x11, 0, 0);
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WriteRegBit(iobase, 0x11, 7, 0);
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}
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}
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#define CRC16(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,7,val) //0 for 32 CRC
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/*
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#define SetVFIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,5,val)
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#define SetFIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,6,val)
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#define SetMIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,5,val)
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#define SetSIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,4,val)
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*/
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#define SIRFilter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,3,val)
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#define Filter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,2,val)
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#define InvertTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,1,val)
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#define InvertRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,0,val)
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//****************************I_CF_H_0
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#define EnableTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,4,val)
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#define EnableRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,3,val)
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#define EnableDMA(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,2,val)
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#define SIRRecvAny(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,1,val)
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#define DiableTrans(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,0,val)
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//***************************I_SIR_BOF,I_SIR_EOF
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#define SetSIRBOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_BOF,val)
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#define SetSIREOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_EOF,val)
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#define GetSIRBOF(BaseAddr) ReadReg(BaseAddr,I_SIR_BOF)
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#define GetSIREOF(BaseAddr) ReadReg(BaseAddr,I_SIR_EOF)
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//*******************I_ST_CT_0
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#define EnPhys(BaseAddr,val) WriteRegBit(BaseAddr,I_ST_CT_0,7,val)
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#define IsModeError(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,6) //RO
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#define IsVFIROn(BaseAddr) CheckRegBit(BaseAddr,0x14,0) //RO for VT1211 only
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#define IsFIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,5) //RO
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#define IsMIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,4) //RO
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#define IsSIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,3) //RO
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#define IsEnableTX(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,2) //RO
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#define IsEnableRX(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,1) //RO
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#define Is16CRC(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,0) //RO
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//***************************I_CF_3
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#define DisableAdjacentPulseWidth(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,5,val) //1 disable
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#define DisablePulseWidthAdjust(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,4,val) //1 disable
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#define UseOneRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,1,val) //0 use two RX
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#define SlowIRRXLowActive(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,0,val) //0 show RX high=1 in SIR
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//***************************H_CT
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#define EnAllInt(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,7,val)
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#define TXStart(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,6,val)
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#define RXStart(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,5,val)
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#define ClearRXInt(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,4,val) // 1 clear
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//*****************H_ST
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#define IsRXInt(BaseAddr) CheckRegBit(BaseAddr,H_ST,4)
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#define GetIntIndentify(BaseAddr) ((ReadReg(BaseAddr,H_ST)&0xf1) >>1)
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#define IsHostBusy(BaseAddr) CheckRegBit(BaseAddr,H_ST,0)
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#define GetHostStatus(BaseAddr) ReadReg(BaseAddr,H_ST) //RO
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//**************************M_CT
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#define EnTXDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,7,val)
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#define EnRXDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,6,val)
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#define SwapDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,5,val)
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#define EnInternalLoop(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,4,val)
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#define EnExternalLoop(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,3,val)
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//**************************TX_CT_1
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#define EnTXFIFOHalfLevelInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,4,val) //half empty int (1 half)
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#define EnTXFIFOUnderrunEOMInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,5,val)
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#define EnTXFIFOReadyInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,6,val) //int when reach it threshold (setting by bit 4)
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//**************************TX_CT_2
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#define ForceUnderrun(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,7,val) // force an underrun int
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#define EnTXCRC(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,6,val) //1 for FIR,MIR...0 (not SIR)
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#define ForceBADCRC(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,5,val) //force an bad CRC
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#define SendSIP(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,4,val) //send indication pulse for prevent SIR disturb
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#define ClearEnTX(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,3,val) // opposite to EnTX
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//*****************TX_ST
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#define GetTXStatus(BaseAddr) ReadReg(BaseAddr,TX_ST) //RO
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//**************************RX_CT
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#define EnRXSpecInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,0,val)
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#define EnRXFIFOReadyInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,1,val) //enable int when reach it threshold (setting by bit 7)
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#define EnRXFIFOHalfLevelInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,7,val) //enable int when (1) half full...or (0) just not full
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//*****************RX_ST
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#define GetRXStatus(BaseAddr) ReadReg(BaseAddr,RX_ST) //RO
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//***********************P_ADDR
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#define SetPacketAddr(BaseAddr,addr) WriteReg(BaseAddr,P_ADDR,addr)
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//***********************I_CF_4
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#define EnGPIOtoRX2(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,7,val)
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#define EnTimerInt(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,1,val)
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#define ClearTimerInt(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,0,val)
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//***********************I_T_C_L
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#define WriteGIO(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_L,7,val)
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#define ReadGIO(BaseAddr) CheckRegBit(BaseAddr,I_T_C_L,7)
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#define ReadRX(BaseAddr) CheckRegBit(BaseAddr,I_T_C_L,3) //RO
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#define WriteTX(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_L,0,val)
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//***********************I_T_C_H
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#define EnRX2(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_H,7,val)
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#define ReadRX2(BaseAddr) CheckRegBit(BaseAddr,I_T_C_H,7)
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//**********************Version
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#define GetFIRVersion(BaseAddr) ReadReg(BaseAddr,VERSION)
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static void SetTimer(__u16 iobase, __u8 count)
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{
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EnTimerInt(iobase, OFF);
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WriteReg(iobase, TIMER, count);
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EnTimerInt(iobase, ON);
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}
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static void SetSendByte(__u16 iobase, __u32 count)
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{
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__u32 low, high;
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if ((count & 0xf000) == 0) {
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low = count & 0x00ff;
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high = (count & 0x0f00) >> 8;
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WriteReg(iobase, TX_C_L, low);
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WriteReg(iobase, TX_C_H, high);
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}
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}
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static void ResetChip(__u16 iobase, __u8 type)
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{
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__u8 value;
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value = (type + 2) << 4;
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WriteReg(iobase, RESET, type);
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}
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static int CkRxRecv(__u16 iobase, struct via_ircc_cb *self)
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{
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__u8 low, high;
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__u16 wTmp = 0, wTmp1 = 0, wTmp_new = 0;
|
|
|
|
low = ReadReg(iobase, RX_C_L);
|
|
high = ReadReg(iobase, RX_C_H);
|
|
wTmp1 = high;
|
|
wTmp = (wTmp1 << 8) | low;
|
|
udelay(10);
|
|
low = ReadReg(iobase, RX_C_L);
|
|
high = ReadReg(iobase, RX_C_H);
|
|
wTmp1 = high;
|
|
wTmp_new = (wTmp1 << 8) | low;
|
|
if (wTmp_new != wTmp)
|
|
return 1;
|
|
else
|
|
return 0;
|
|
|
|
}
|
|
|
|
static __u16 RxCurCount(__u16 iobase, struct via_ircc_cb * self)
|
|
{
|
|
__u8 low, high;
|
|
__u16 wTmp = 0, wTmp1 = 0;
|
|
|
|
low = ReadReg(iobase, RX_P_L);
|
|
high = ReadReg(iobase, RX_P_H);
|
|
wTmp1 = high;
|
|
wTmp = (wTmp1 << 8) | low;
|
|
return wTmp;
|
|
}
|
|
|
|
/* This Routine can only use in recevie_complete
|
|
* for it will update last count.
|
|
*/
|
|
|
|
static __u16 GetRecvByte(__u16 iobase, struct via_ircc_cb * self)
|
|
{
|
|
__u8 low, high;
|
|
__u16 wTmp, wTmp1, ret;
|
|
|
|
low = ReadReg(iobase, RX_P_L);
|
|
high = ReadReg(iobase, RX_P_H);
|
|
wTmp1 = high;
|
|
wTmp = (wTmp1 << 8) | low;
|
|
|
|
|
|
if (wTmp >= self->RxLastCount)
|
|
ret = wTmp - self->RxLastCount;
|
|
else
|
|
ret = (0x8000 - self->RxLastCount) + wTmp;
|
|
self->RxLastCount = wTmp;
|
|
|
|
/* RX_P is more actually the RX_C
|
|
low=ReadReg(iobase,RX_C_L);
|
|
high=ReadReg(iobase,RX_C_H);
|
|
|
|
if(!(high&0xe000)) {
|
|
temp=(high<<8)+low;
|
|
return temp;
|
|
}
|
|
else return 0;
|
|
*/
|
|
return ret;
|
|
}
|
|
|
|
static void Sdelay(__u16 scale)
|
|
{
|
|
__u8 bTmp;
|
|
int i, j;
|
|
|
|
for (j = 0; j < scale; j++) {
|
|
for (i = 0; i < 0x20; i++) {
|
|
bTmp = inb(0xeb);
|
|
outb(bTmp, 0xeb);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void Tdelay(__u16 scale)
|
|
{
|
|
__u8 bTmp;
|
|
int i, j;
|
|
|
|
for (j = 0; j < scale; j++) {
|
|
for (i = 0; i < 0x50; i++) {
|
|
bTmp = inb(0xeb);
|
|
outb(bTmp, 0xeb);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
static void ActClk(__u16 iobase, __u8 value)
|
|
{
|
|
__u8 bTmp;
|
|
bTmp = ReadReg(iobase, 0x34);
|
|
if (value)
|
|
WriteReg(iobase, 0x34, bTmp | Clk_bit);
|
|
else
|
|
WriteReg(iobase, 0x34, bTmp & ~Clk_bit);
|
|
}
|
|
|
|
static void ClkTx(__u16 iobase, __u8 Clk, __u8 Tx)
|
|
{
|
|
__u8 bTmp;
|
|
|
|
bTmp = ReadReg(iobase, 0x34);
|
|
if (Clk == 0)
|
|
bTmp &= ~Clk_bit;
|
|
else {
|
|
if (Clk == 1)
|
|
bTmp |= Clk_bit;
|
|
}
|
|
WriteReg(iobase, 0x34, bTmp);
|
|
Sdelay(1);
|
|
if (Tx == 0)
|
|
bTmp &= ~Tx_bit;
|
|
else {
|
|
if (Tx == 1)
|
|
bTmp |= Tx_bit;
|
|
}
|
|
WriteReg(iobase, 0x34, bTmp);
|
|
}
|
|
|
|
static void Wr_Byte(__u16 iobase, __u8 data)
|
|
{
|
|
__u8 bData = data;
|
|
// __u8 btmp;
|
|
int i;
|
|
|
|
ClkTx(iobase, 0, 1);
|
|
|
|
Tdelay(2);
|
|
ActClk(iobase, 1);
|
|
Tdelay(1);
|
|
|
|
for (i = 0; i < 8; i++) { //LDN
|
|
|
|
if ((bData >> i) & 0x01) {
|
|
ClkTx(iobase, 0, 1); //bit data = 1;
|
|
} else {
|
|
ClkTx(iobase, 0, 0); //bit data = 1;
|
|
}
|
|
Tdelay(2);
|
|
Sdelay(1);
|
|
ActClk(iobase, 1); //clk hi
|
|
Tdelay(1);
|
|
}
|
|
}
|
|
|
|
static __u8 Rd_Indx(__u16 iobase, __u8 addr, __u8 index)
|
|
{
|
|
__u8 data = 0, bTmp, data_bit;
|
|
int i;
|
|
|
|
bTmp = addr | (index << 1) | 0;
|
|
ClkTx(iobase, 0, 0);
|
|
Tdelay(2);
|
|
ActClk(iobase, 1);
|
|
udelay(1);
|
|
Wr_Byte(iobase, bTmp);
|
|
Sdelay(1);
|
|
ClkTx(iobase, 0, 0);
|
|
Tdelay(2);
|
|
for (i = 0; i < 10; i++) {
|
|
ActClk(iobase, 1);
|
|
Tdelay(1);
|
|
ActClk(iobase, 0);
|
|
Tdelay(1);
|
|
ClkTx(iobase, 0, 1);
|
|
Tdelay(1);
|
|
bTmp = ReadReg(iobase, 0x34);
|
|
if (!(bTmp & Rd_Valid))
|
|
break;
|
|
}
|
|
if (!(bTmp & Rd_Valid)) {
|
|
for (i = 0; i < 8; i++) {
|
|
ActClk(iobase, 1);
|
|
Tdelay(1);
|
|
ActClk(iobase, 0);
|
|
bTmp = ReadReg(iobase, 0x34);
|
|
data_bit = 1 << i;
|
|
if (bTmp & RxBit)
|
|
data |= data_bit;
|
|
else
|
|
data &= ~data_bit;
|
|
Tdelay(2);
|
|
}
|
|
} else {
|
|
for (i = 0; i < 2; i++) {
|
|
ActClk(iobase, 1);
|
|
Tdelay(1);
|
|
ActClk(iobase, 0);
|
|
Tdelay(2);
|
|
}
|
|
bTmp = ReadReg(iobase, 0x34);
|
|
}
|
|
for (i = 0; i < 1; i++) {
|
|
ActClk(iobase, 1);
|
|
Tdelay(1);
|
|
ActClk(iobase, 0);
|
|
Tdelay(2);
|
|
}
|
|
ClkTx(iobase, 0, 0);
|
|
Tdelay(1);
|
|
for (i = 0; i < 3; i++) {
|
|
ActClk(iobase, 1);
|
|
Tdelay(1);
|
|
ActClk(iobase, 0);
|
|
Tdelay(2);
|
|
}
|
|
return data;
|
|
}
|
|
|
|
static void Wr_Indx(__u16 iobase, __u8 addr, __u8 index, __u8 data)
|
|
{
|
|
int i;
|
|
__u8 bTmp;
|
|
|
|
ClkTx(iobase, 0, 0);
|
|
udelay(2);
|
|
ActClk(iobase, 1);
|
|
udelay(1);
|
|
bTmp = addr | (index << 1) | 1;
|
|
Wr_Byte(iobase, bTmp);
|
|
Wr_Byte(iobase, data);
|
|
for (i = 0; i < 2; i++) {
|
|
ClkTx(iobase, 0, 0);
|
|
Tdelay(2);
|
|
ActClk(iobase, 1);
|
|
Tdelay(1);
|
|
}
|
|
ActClk(iobase, 0);
|
|
}
|
|
|
|
static void ResetDongle(__u16 iobase)
|
|
{
|
|
int i;
|
|
ClkTx(iobase, 0, 0);
|
|
Tdelay(1);
|
|
for (i = 0; i < 30; i++) {
|
|
ActClk(iobase, 1);
|
|
Tdelay(1);
|
|
ActClk(iobase, 0);
|
|
Tdelay(1);
|
|
}
|
|
ActClk(iobase, 0);
|
|
}
|
|
|
|
static void SetSITmode(__u16 iobase)
|
|
{
|
|
|
|
__u8 bTmp;
|
|
|
|
bTmp = ReadLPCReg(0x28);
|
|
WriteLPCReg(0x28, bTmp | 0x10); //select ITMOFF
|
|
bTmp = ReadReg(iobase, 0x35);
|
|
WriteReg(iobase, 0x35, bTmp | 0x40); // Driver ITMOFF
|
|
WriteReg(iobase, 0x28, bTmp | 0x80); // enable All interrupt
|
|
}
|
|
|
|
static void SI_SetMode(__u16 iobase, int mode)
|
|
{
|
|
//__u32 dTmp;
|
|
__u8 bTmp;
|
|
|
|
WriteLPCReg(0x28, 0x70); // S/W Reset
|
|
SetSITmode(iobase);
|
|
ResetDongle(iobase);
|
|
udelay(10);
|
|
Wr_Indx(iobase, 0x40, 0x0, 0x17); //RX ,APEN enable,Normal power
|
|
Wr_Indx(iobase, 0x40, 0x1, mode); //Set Mode
|
|
Wr_Indx(iobase, 0x40, 0x2, 0xff); //Set power to FIR VFIR > 1m
|
|
bTmp = Rd_Indx(iobase, 0x40, 1);
|
|
}
|
|
|
|
static void InitCard(__u16 iobase)
|
|
{
|
|
ResetChip(iobase, 5);
|
|
WriteReg(iobase, I_ST_CT_0, 0x00); // open CHIP on
|
|
SetSIRBOF(iobase, 0xc0); // hardware default value
|
|
SetSIREOF(iobase, 0xc1);
|
|
}
|
|
|
|
static void CommonInit(__u16 iobase)
|
|
{
|
|
// EnTXCRC(iobase,0);
|
|
SwapDMA(iobase, OFF);
|
|
SetMaxRxPacketSize(iobase, 0x0fff); //set to max:4095
|
|
EnRXFIFOReadyInt(iobase, OFF);
|
|
EnRXFIFOHalfLevelInt(iobase, OFF);
|
|
EnTXFIFOHalfLevelInt(iobase, OFF);
|
|
EnTXFIFOUnderrunEOMInt(iobase, ON);
|
|
// EnTXFIFOReadyInt(iobase,ON);
|
|
InvertTX(iobase, OFF);
|
|
InvertRX(iobase, OFF);
|
|
// WriteLPCReg(0xF0,0); //(if VT1211 then do this)
|
|
if (IsSIROn(iobase)) {
|
|
SIRFilter(iobase, ON);
|
|
SIRRecvAny(iobase, ON);
|
|
} else {
|
|
SIRFilter(iobase, OFF);
|
|
SIRRecvAny(iobase, OFF);
|
|
}
|
|
EnRXSpecInt(iobase, ON);
|
|
WriteReg(iobase, I_ST_CT_0, 0x80);
|
|
EnableDMA(iobase, ON);
|
|
}
|
|
|
|
static void SetBaudRate(__u16 iobase, __u32 rate)
|
|
{
|
|
__u8 value = 11, temp;
|
|
|
|
if (IsSIROn(iobase)) {
|
|
switch (rate) {
|
|
case (__u32) (2400L):
|
|
value = 47;
|
|
break;
|
|
case (__u32) (9600L):
|
|
value = 11;
|
|
break;
|
|
case (__u32) (19200L):
|
|
value = 5;
|
|
break;
|
|
case (__u32) (38400L):
|
|
value = 2;
|
|
break;
|
|
case (__u32) (57600L):
|
|
value = 1;
|
|
break;
|
|
case (__u32) (115200L):
|
|
value = 0;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
} else if (IsMIROn(iobase)) {
|
|
value = 0; // will automatically be fixed in 1.152M
|
|
} else if (IsFIROn(iobase)) {
|
|
value = 0; // will automatically be fixed in 4M
|
|
}
|
|
temp = (ReadReg(iobase, I_CF_H_1) & 0x03);
|
|
temp |= value << 2;
|
|
WriteReg(iobase, I_CF_H_1, temp);
|
|
}
|
|
|
|
static void SetPulseWidth(__u16 iobase, __u8 width)
|
|
{
|
|
__u8 temp, temp1, temp2;
|
|
|
|
temp = (ReadReg(iobase, I_CF_L_1) & 0x1f);
|
|
temp1 = (ReadReg(iobase, I_CF_H_1) & 0xfc);
|
|
temp2 = (width & 0x07) << 5;
|
|
temp |= temp2;
|
|
temp2 = (width & 0x18) >> 3;
|
|
temp1 |= temp2;
|
|
WriteReg(iobase, I_CF_L_1, temp);
|
|
WriteReg(iobase, I_CF_H_1, temp1);
|
|
}
|
|
|
|
static void SetSendPreambleCount(__u16 iobase, __u8 count)
|
|
{
|
|
__u8 temp;
|
|
|
|
temp = ReadReg(iobase, I_CF_L_1) & 0xe0;
|
|
temp |= count;
|
|
WriteReg(iobase, I_CF_L_1, temp);
|
|
|
|
}
|
|
|
|
static void SetVFIR(__u16 BaseAddr, __u8 val)
|
|
{
|
|
__u8 tmp;
|
|
|
|
tmp = ReadReg(BaseAddr, I_CF_L_0);
|
|
WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
|
|
WriteRegBit(BaseAddr, I_CF_H_0, 5, val);
|
|
}
|
|
|
|
static void SetFIR(__u16 BaseAddr, __u8 val)
|
|
{
|
|
__u8 tmp;
|
|
|
|
WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
|
|
tmp = ReadReg(BaseAddr, I_CF_L_0);
|
|
WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
|
|
WriteRegBit(BaseAddr, I_CF_L_0, 6, val);
|
|
}
|
|
|
|
static void SetMIR(__u16 BaseAddr, __u8 val)
|
|
{
|
|
__u8 tmp;
|
|
|
|
WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
|
|
tmp = ReadReg(BaseAddr, I_CF_L_0);
|
|
WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
|
|
WriteRegBit(BaseAddr, I_CF_L_0, 5, val);
|
|
}
|
|
|
|
static void SetSIR(__u16 BaseAddr, __u8 val)
|
|
{
|
|
__u8 tmp;
|
|
|
|
WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
|
|
tmp = ReadReg(BaseAddr, I_CF_L_0);
|
|
WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
|
|
WriteRegBit(BaseAddr, I_CF_L_0, 4, val);
|
|
}
|
|
|
|
#endif /* via_IRCC_H */
|