1608 строки
40 KiB
C
1608 строки
40 KiB
C
/*
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* Derived from arch/powerpc/kernel/iommu.c
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*
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* Copyright IBM Corporation, 2006-2007
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* Copyright (C) 2006 Jon Mason <jdmason@kudzu.us>
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*
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* Author: Jon Mason <jdmason@kudzu.us>
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* Author: Muli Ben-Yehuda <muli@il.ibm.com>
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define pr_fmt(fmt) "Calgary: " fmt
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/crash_dump.h>
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#include <linux/dma-mapping.h>
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#include <linux/bitmap.h>
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#include <linux/pci_ids.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/scatterlist.h>
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#include <linux/iommu-helper.h>
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#include <asm/iommu.h>
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#include <asm/calgary.h>
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#include <asm/tce.h>
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#include <asm/pci-direct.h>
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#include <asm/dma.h>
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#include <asm/rio.h>
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#include <asm/bios_ebda.h>
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#include <asm/x86_init.h>
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#include <asm/iommu_table.h>
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#ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
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int use_calgary __read_mostly = 1;
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#else
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int use_calgary __read_mostly = 0;
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#endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
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#define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
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#define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
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/* register offsets inside the host bridge space */
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#define CALGARY_CONFIG_REG 0x0108
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#define PHB_CSR_OFFSET 0x0110 /* Channel Status */
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#define PHB_PLSSR_OFFSET 0x0120
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#define PHB_CONFIG_RW_OFFSET 0x0160
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#define PHB_IOBASE_BAR_LOW 0x0170
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#define PHB_IOBASE_BAR_HIGH 0x0180
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#define PHB_MEM_1_LOW 0x0190
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#define PHB_MEM_1_HIGH 0x01A0
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#define PHB_IO_ADDR_SIZE 0x01B0
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#define PHB_MEM_1_SIZE 0x01C0
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#define PHB_MEM_ST_OFFSET 0x01D0
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#define PHB_AER_OFFSET 0x0200
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#define PHB_CONFIG_0_HIGH 0x0220
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#define PHB_CONFIG_0_LOW 0x0230
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#define PHB_CONFIG_0_END 0x0240
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#define PHB_MEM_2_LOW 0x02B0
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#define PHB_MEM_2_HIGH 0x02C0
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#define PHB_MEM_2_SIZE_HIGH 0x02D0
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#define PHB_MEM_2_SIZE_LOW 0x02E0
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#define PHB_DOSHOLE_OFFSET 0x08E0
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/* CalIOC2 specific */
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#define PHB_SAVIOR_L2 0x0DB0
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#define PHB_PAGE_MIG_CTRL 0x0DA8
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#define PHB_PAGE_MIG_DEBUG 0x0DA0
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#define PHB_ROOT_COMPLEX_STATUS 0x0CB0
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/* PHB_CONFIG_RW */
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#define PHB_TCE_ENABLE 0x20000000
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#define PHB_SLOT_DISABLE 0x1C000000
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#define PHB_DAC_DISABLE 0x01000000
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#define PHB_MEM2_ENABLE 0x00400000
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#define PHB_MCSR_ENABLE 0x00100000
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/* TAR (Table Address Register) */
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#define TAR_SW_BITS 0x0000ffffffff800fUL
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#define TAR_VALID 0x0000000000000008UL
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/* CSR (Channel/DMA Status Register) */
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#define CSR_AGENT_MASK 0xffe0ffff
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/* CCR (Calgary Configuration Register) */
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#define CCR_2SEC_TIMEOUT 0x000000000000000EUL
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/* PMCR/PMDR (Page Migration Control/Debug Registers */
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#define PMR_SOFTSTOP 0x80000000
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#define PMR_SOFTSTOPFAULT 0x40000000
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#define PMR_HARDSTOP 0x20000000
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/*
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* The maximum PHB bus number.
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* x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
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* x3950M2: 4 chassis, 48 PHBs per chassis = 192
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* x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
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* x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
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*/
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#define MAX_PHB_BUS_NUM 256
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#define PHBS_PER_CALGARY 4
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/* register offsets in Calgary's internal register space */
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static const unsigned long tar_offsets[] = {
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0x0580 /* TAR0 */,
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0x0588 /* TAR1 */,
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0x0590 /* TAR2 */,
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0x0598 /* TAR3 */
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};
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static const unsigned long split_queue_offsets[] = {
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0x4870 /* SPLIT QUEUE 0 */,
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0x5870 /* SPLIT QUEUE 1 */,
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0x6870 /* SPLIT QUEUE 2 */,
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0x7870 /* SPLIT QUEUE 3 */
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};
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static const unsigned long phb_offsets[] = {
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0x8000 /* PHB0 */,
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0x9000 /* PHB1 */,
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0xA000 /* PHB2 */,
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0xB000 /* PHB3 */
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};
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/* PHB debug registers */
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static const unsigned long phb_debug_offsets[] = {
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0x4000 /* PHB 0 DEBUG */,
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0x5000 /* PHB 1 DEBUG */,
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0x6000 /* PHB 2 DEBUG */,
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0x7000 /* PHB 3 DEBUG */
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};
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/*
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* STUFF register for each debug PHB,
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* byte 1 = start bus number, byte 2 = end bus number
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*/
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#define PHB_DEBUG_STUFF_OFFSET 0x0020
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#define EMERGENCY_PAGES 32 /* = 128KB */
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unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
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static int translate_empty_slots __read_mostly = 0;
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static int calgary_detected __read_mostly = 0;
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static struct rio_table_hdr *rio_table_hdr __initdata;
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static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata;
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static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata;
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struct calgary_bus_info {
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void *tce_space;
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unsigned char translation_disabled;
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signed char phbid;
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void __iomem *bbar;
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};
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static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
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static void calgary_tce_cache_blast(struct iommu_table *tbl);
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static void calgary_dump_error_regs(struct iommu_table *tbl);
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static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
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static void calioc2_tce_cache_blast(struct iommu_table *tbl);
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static void calioc2_dump_error_regs(struct iommu_table *tbl);
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static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
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static void get_tce_space_from_tar(void);
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static const struct cal_chipset_ops calgary_chip_ops = {
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.handle_quirks = calgary_handle_quirks,
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.tce_cache_blast = calgary_tce_cache_blast,
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.dump_error_regs = calgary_dump_error_regs
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};
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static const struct cal_chipset_ops calioc2_chip_ops = {
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.handle_quirks = calioc2_handle_quirks,
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.tce_cache_blast = calioc2_tce_cache_blast,
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.dump_error_regs = calioc2_dump_error_regs
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};
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static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
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static inline int translation_enabled(struct iommu_table *tbl)
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{
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/* only PHBs with translation enabled have an IOMMU table */
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return (tbl != NULL);
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}
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static void iommu_range_reserve(struct iommu_table *tbl,
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unsigned long start_addr, unsigned int npages)
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{
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unsigned long index;
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unsigned long end;
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unsigned long flags;
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index = start_addr >> PAGE_SHIFT;
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/* bail out if we're asked to reserve a region we don't cover */
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if (index >= tbl->it_size)
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return;
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end = index + npages;
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if (end > tbl->it_size) /* don't go off the table */
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end = tbl->it_size;
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spin_lock_irqsave(&tbl->it_lock, flags);
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bitmap_set(tbl->it_map, index, npages);
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spin_unlock_irqrestore(&tbl->it_lock, flags);
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}
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static unsigned long iommu_range_alloc(struct device *dev,
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struct iommu_table *tbl,
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unsigned int npages)
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{
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unsigned long flags;
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unsigned long offset;
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unsigned long boundary_size;
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boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
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PAGE_SIZE) >> PAGE_SHIFT;
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BUG_ON(npages == 0);
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spin_lock_irqsave(&tbl->it_lock, flags);
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offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
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npages, 0, boundary_size, 0);
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if (offset == ~0UL) {
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tbl->chip_ops->tce_cache_blast(tbl);
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offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
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npages, 0, boundary_size, 0);
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if (offset == ~0UL) {
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pr_warn("IOMMU full\n");
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spin_unlock_irqrestore(&tbl->it_lock, flags);
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if (panic_on_overflow)
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panic("Calgary: fix the allocator.\n");
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else
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return DMA_ERROR_CODE;
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}
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}
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tbl->it_hint = offset + npages;
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BUG_ON(tbl->it_hint > tbl->it_size);
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spin_unlock_irqrestore(&tbl->it_lock, flags);
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return offset;
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}
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static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
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void *vaddr, unsigned int npages, int direction)
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{
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unsigned long entry;
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dma_addr_t ret;
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entry = iommu_range_alloc(dev, tbl, npages);
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if (unlikely(entry == DMA_ERROR_CODE)) {
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pr_warn("failed to allocate %u pages in iommu %p\n",
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npages, tbl);
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return DMA_ERROR_CODE;
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}
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/* set the return dma address */
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ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
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/* put the TCEs in the HW table */
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tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
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direction);
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return ret;
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}
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static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
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unsigned int npages)
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{
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unsigned long entry;
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unsigned long badend;
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unsigned long flags;
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/* were we called with bad_dma_address? */
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badend = DMA_ERROR_CODE + (EMERGENCY_PAGES * PAGE_SIZE);
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if (unlikely((dma_addr >= DMA_ERROR_CODE) && (dma_addr < badend))) {
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WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
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"address 0x%Lx\n", dma_addr);
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return;
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}
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entry = dma_addr >> PAGE_SHIFT;
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BUG_ON(entry + npages > tbl->it_size);
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tce_free(tbl, entry, npages);
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spin_lock_irqsave(&tbl->it_lock, flags);
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bitmap_clear(tbl->it_map, entry, npages);
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spin_unlock_irqrestore(&tbl->it_lock, flags);
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}
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static inline struct iommu_table *find_iommu_table(struct device *dev)
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{
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struct pci_dev *pdev;
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struct pci_bus *pbus;
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struct iommu_table *tbl;
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pdev = to_pci_dev(dev);
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/* search up the device tree for an iommu */
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pbus = pdev->bus;
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do {
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tbl = pci_iommu(pbus);
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if (tbl && tbl->it_busno == pbus->number)
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break;
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tbl = NULL;
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pbus = pbus->parent;
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} while (pbus);
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BUG_ON(tbl && (tbl->it_busno != pbus->number));
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return tbl;
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}
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static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
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int nelems,enum dma_data_direction dir,
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unsigned long attrs)
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{
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struct iommu_table *tbl = find_iommu_table(dev);
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struct scatterlist *s;
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int i;
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if (!translation_enabled(tbl))
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return;
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for_each_sg(sglist, s, nelems, i) {
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unsigned int npages;
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dma_addr_t dma = s->dma_address;
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unsigned int dmalen = s->dma_length;
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if (dmalen == 0)
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break;
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npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
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iommu_free(tbl, dma, npages);
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}
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}
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static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
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int nelems, enum dma_data_direction dir,
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unsigned long attrs)
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{
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struct iommu_table *tbl = find_iommu_table(dev);
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struct scatterlist *s;
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unsigned long vaddr;
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unsigned int npages;
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unsigned long entry;
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int i;
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for_each_sg(sg, s, nelems, i) {
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BUG_ON(!sg_page(s));
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vaddr = (unsigned long) sg_virt(s);
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npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
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entry = iommu_range_alloc(dev, tbl, npages);
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if (entry == DMA_ERROR_CODE) {
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/* makes sure unmap knows to stop */
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s->dma_length = 0;
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goto error;
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}
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s->dma_address = (entry << PAGE_SHIFT) | s->offset;
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/* insert into HW table */
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tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir);
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s->dma_length = s->length;
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}
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return nelems;
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error:
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calgary_unmap_sg(dev, sg, nelems, dir, 0);
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for_each_sg(sg, s, nelems, i) {
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sg->dma_address = DMA_ERROR_CODE;
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sg->dma_length = 0;
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}
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return 0;
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}
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static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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unsigned long attrs)
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{
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void *vaddr = page_address(page) + offset;
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unsigned long uaddr;
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unsigned int npages;
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struct iommu_table *tbl = find_iommu_table(dev);
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uaddr = (unsigned long)vaddr;
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npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
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return iommu_alloc(dev, tbl, vaddr, npages, dir);
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}
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static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
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size_t size, enum dma_data_direction dir,
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unsigned long attrs)
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{
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struct iommu_table *tbl = find_iommu_table(dev);
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unsigned int npages;
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npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
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iommu_free(tbl, dma_addr, npages);
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}
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static void* calgary_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag, unsigned long attrs)
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{
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void *ret = NULL;
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dma_addr_t mapping;
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unsigned int npages, order;
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struct iommu_table *tbl = find_iommu_table(dev);
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size = PAGE_ALIGN(size); /* size rounded up to full pages */
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npages = size >> PAGE_SHIFT;
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order = get_order(size);
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flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
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/* alloc enough pages (and possibly more) */
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ret = (void *)__get_free_pages(flag, order);
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if (!ret)
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goto error;
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memset(ret, 0, size);
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/* set up tces to cover the allocated range */
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mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
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if (mapping == DMA_ERROR_CODE)
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goto free;
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*dma_handle = mapping;
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return ret;
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free:
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free_pages((unsigned long)ret, get_order(size));
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ret = NULL;
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error:
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return ret;
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}
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static void calgary_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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unsigned long attrs)
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{
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unsigned int npages;
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struct iommu_table *tbl = find_iommu_table(dev);
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size = PAGE_ALIGN(size);
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npages = size >> PAGE_SHIFT;
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iommu_free(tbl, dma_handle, npages);
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free_pages((unsigned long)vaddr, get_order(size));
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}
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static struct dma_map_ops calgary_dma_ops = {
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.alloc = calgary_alloc_coherent,
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.free = calgary_free_coherent,
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.map_sg = calgary_map_sg,
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.unmap_sg = calgary_unmap_sg,
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.map_page = calgary_map_page,
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.unmap_page = calgary_unmap_page,
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};
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static inline void __iomem * busno_to_bbar(unsigned char num)
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{
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return bus_info[num].bbar;
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}
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|
|
static inline int busno_to_phbid(unsigned char num)
|
|
{
|
|
return bus_info[num].phbid;
|
|
}
|
|
|
|
static inline unsigned long split_queue_offset(unsigned char num)
|
|
{
|
|
size_t idx = busno_to_phbid(num);
|
|
|
|
return split_queue_offsets[idx];
|
|
}
|
|
|
|
static inline unsigned long tar_offset(unsigned char num)
|
|
{
|
|
size_t idx = busno_to_phbid(num);
|
|
|
|
return tar_offsets[idx];
|
|
}
|
|
|
|
static inline unsigned long phb_offset(unsigned char num)
|
|
{
|
|
size_t idx = busno_to_phbid(num);
|
|
|
|
return phb_offsets[idx];
|
|
}
|
|
|
|
static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
|
|
{
|
|
unsigned long target = ((unsigned long)bar) | offset;
|
|
return (void __iomem*)target;
|
|
}
|
|
|
|
static inline int is_calioc2(unsigned short device)
|
|
{
|
|
return (device == PCI_DEVICE_ID_IBM_CALIOC2);
|
|
}
|
|
|
|
static inline int is_calgary(unsigned short device)
|
|
{
|
|
return (device == PCI_DEVICE_ID_IBM_CALGARY);
|
|
}
|
|
|
|
static inline int is_cal_pci_dev(unsigned short device)
|
|
{
|
|
return (is_calgary(device) || is_calioc2(device));
|
|
}
|
|
|
|
static void calgary_tce_cache_blast(struct iommu_table *tbl)
|
|
{
|
|
u64 val;
|
|
u32 aer;
|
|
int i = 0;
|
|
void __iomem *bbar = tbl->bbar;
|
|
void __iomem *target;
|
|
|
|
/* disable arbitration on the bus */
|
|
target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
|
|
aer = readl(target);
|
|
writel(0, target);
|
|
|
|
/* read plssr to ensure it got there */
|
|
target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
|
|
val = readl(target);
|
|
|
|
/* poll split queues until all DMA activity is done */
|
|
target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
|
|
do {
|
|
val = readq(target);
|
|
i++;
|
|
} while ((val & 0xff) != 0xff && i < 100);
|
|
if (i == 100)
|
|
pr_warn("PCI bus not quiesced, continuing anyway\n");
|
|
|
|
/* invalidate TCE cache */
|
|
target = calgary_reg(bbar, tar_offset(tbl->it_busno));
|
|
writeq(tbl->tar_val, target);
|
|
|
|
/* enable arbitration */
|
|
target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
|
|
writel(aer, target);
|
|
(void)readl(target); /* flush */
|
|
}
|
|
|
|
static void calioc2_tce_cache_blast(struct iommu_table *tbl)
|
|
{
|
|
void __iomem *bbar = tbl->bbar;
|
|
void __iomem *target;
|
|
u64 val64;
|
|
u32 val;
|
|
int i = 0;
|
|
int count = 1;
|
|
unsigned char bus = tbl->it_busno;
|
|
|
|
begin:
|
|
printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
|
|
"sequence - count %d\n", bus, count);
|
|
|
|
/* 1. using the Page Migration Control reg set SoftStop */
|
|
target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
|
|
val = be32_to_cpu(readl(target));
|
|
printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
|
|
val |= PMR_SOFTSTOP;
|
|
printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
|
|
writel(cpu_to_be32(val), target);
|
|
|
|
/* 2. poll split queues until all DMA activity is done */
|
|
printk(KERN_DEBUG "2a. starting to poll split queues\n");
|
|
target = calgary_reg(bbar, split_queue_offset(bus));
|
|
do {
|
|
val64 = readq(target);
|
|
i++;
|
|
} while ((val64 & 0xff) != 0xff && i < 100);
|
|
if (i == 100)
|
|
pr_warn("CalIOC2: PCI bus not quiesced, continuing anyway\n");
|
|
|
|
/* 3. poll Page Migration DEBUG for SoftStopFault */
|
|
target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
|
|
val = be32_to_cpu(readl(target));
|
|
printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
|
|
|
|
/* 4. if SoftStopFault - goto (1) */
|
|
if (val & PMR_SOFTSTOPFAULT) {
|
|
if (++count < 100)
|
|
goto begin;
|
|
else {
|
|
pr_warn("CalIOC2: too many SoftStopFaults, aborting TCE cache flush sequence!\n");
|
|
return; /* pray for the best */
|
|
}
|
|
}
|
|
|
|
/* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
|
|
target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
|
|
printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
|
|
val = be32_to_cpu(readl(target));
|
|
printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
|
|
target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
|
|
val = be32_to_cpu(readl(target));
|
|
printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
|
|
|
|
/* 6. invalidate TCE cache */
|
|
printk(KERN_DEBUG "6. invalidating TCE cache\n");
|
|
target = calgary_reg(bbar, tar_offset(bus));
|
|
writeq(tbl->tar_val, target);
|
|
|
|
/* 7. Re-read PMCR */
|
|
printk(KERN_DEBUG "7a. Re-reading PMCR\n");
|
|
target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
|
|
val = be32_to_cpu(readl(target));
|
|
printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
|
|
|
|
/* 8. Remove HardStop */
|
|
printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
|
|
target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
|
|
val = 0;
|
|
printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
|
|
writel(cpu_to_be32(val), target);
|
|
val = be32_to_cpu(readl(target));
|
|
printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
|
|
}
|
|
|
|
static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
|
|
u64 limit)
|
|
{
|
|
unsigned int numpages;
|
|
|
|
limit = limit | 0xfffff;
|
|
limit++;
|
|
|
|
numpages = ((limit - start) >> PAGE_SHIFT);
|
|
iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
|
|
}
|
|
|
|
static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
|
|
{
|
|
void __iomem *target;
|
|
u64 low, high, sizelow;
|
|
u64 start, limit;
|
|
struct iommu_table *tbl = pci_iommu(dev->bus);
|
|
unsigned char busnum = dev->bus->number;
|
|
void __iomem *bbar = tbl->bbar;
|
|
|
|
/* peripheral MEM_1 region */
|
|
target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
|
|
low = be32_to_cpu(readl(target));
|
|
target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
|
|
high = be32_to_cpu(readl(target));
|
|
target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
|
|
sizelow = be32_to_cpu(readl(target));
|
|
|
|
start = (high << 32) | low;
|
|
limit = sizelow;
|
|
|
|
calgary_reserve_mem_region(dev, start, limit);
|
|
}
|
|
|
|
static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
|
|
{
|
|
void __iomem *target;
|
|
u32 val32;
|
|
u64 low, high, sizelow, sizehigh;
|
|
u64 start, limit;
|
|
struct iommu_table *tbl = pci_iommu(dev->bus);
|
|
unsigned char busnum = dev->bus->number;
|
|
void __iomem *bbar = tbl->bbar;
|
|
|
|
/* is it enabled? */
|
|
target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
|
|
val32 = be32_to_cpu(readl(target));
|
|
if (!(val32 & PHB_MEM2_ENABLE))
|
|
return;
|
|
|
|
target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
|
|
low = be32_to_cpu(readl(target));
|
|
target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
|
|
high = be32_to_cpu(readl(target));
|
|
target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
|
|
sizelow = be32_to_cpu(readl(target));
|
|
target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
|
|
sizehigh = be32_to_cpu(readl(target));
|
|
|
|
start = (high << 32) | low;
|
|
limit = (sizehigh << 32) | sizelow;
|
|
|
|
calgary_reserve_mem_region(dev, start, limit);
|
|
}
|
|
|
|
/*
|
|
* some regions of the IO address space do not get translated, so we
|
|
* must not give devices IO addresses in those regions. The regions
|
|
* are the 640KB-1MB region and the two PCI peripheral memory holes.
|
|
* Reserve all of them in the IOMMU bitmap to avoid giving them out
|
|
* later.
|
|
*/
|
|
static void __init calgary_reserve_regions(struct pci_dev *dev)
|
|
{
|
|
unsigned int npages;
|
|
u64 start;
|
|
struct iommu_table *tbl = pci_iommu(dev->bus);
|
|
|
|
/* reserve EMERGENCY_PAGES from bad_dma_address and up */
|
|
iommu_range_reserve(tbl, DMA_ERROR_CODE, EMERGENCY_PAGES);
|
|
|
|
/* avoid the BIOS/VGA first 640KB-1MB region */
|
|
/* for CalIOC2 - avoid the entire first MB */
|
|
if (is_calgary(dev->device)) {
|
|
start = (640 * 1024);
|
|
npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
|
|
} else { /* calioc2 */
|
|
start = 0;
|
|
npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
|
|
}
|
|
iommu_range_reserve(tbl, start, npages);
|
|
|
|
/* reserve the two PCI peripheral memory regions in IO space */
|
|
calgary_reserve_peripheral_mem_1(dev);
|
|
calgary_reserve_peripheral_mem_2(dev);
|
|
}
|
|
|
|
static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
|
|
{
|
|
u64 val64;
|
|
u64 table_phys;
|
|
void __iomem *target;
|
|
int ret;
|
|
struct iommu_table *tbl;
|
|
|
|
/* build TCE tables for each PHB */
|
|
ret = build_tce_table(dev, bbar);
|
|
if (ret)
|
|
return ret;
|
|
|
|
tbl = pci_iommu(dev->bus);
|
|
tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
|
|
|
|
if (is_kdump_kernel())
|
|
calgary_init_bitmap_from_tce_table(tbl);
|
|
else
|
|
tce_free(tbl, 0, tbl->it_size);
|
|
|
|
if (is_calgary(dev->device))
|
|
tbl->chip_ops = &calgary_chip_ops;
|
|
else if (is_calioc2(dev->device))
|
|
tbl->chip_ops = &calioc2_chip_ops;
|
|
else
|
|
BUG();
|
|
|
|
calgary_reserve_regions(dev);
|
|
|
|
/* set TARs for each PHB */
|
|
target = calgary_reg(bbar, tar_offset(dev->bus->number));
|
|
val64 = be64_to_cpu(readq(target));
|
|
|
|
/* zero out all TAR bits under sw control */
|
|
val64 &= ~TAR_SW_BITS;
|
|
table_phys = (u64)__pa(tbl->it_base);
|
|
|
|
val64 |= table_phys;
|
|
|
|
BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
|
|
val64 |= (u64) specified_table_size;
|
|
|
|
tbl->tar_val = cpu_to_be64(val64);
|
|
|
|
writeq(tbl->tar_val, target);
|
|
readq(target); /* flush */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __init calgary_free_bus(struct pci_dev *dev)
|
|
{
|
|
u64 val64;
|
|
struct iommu_table *tbl = pci_iommu(dev->bus);
|
|
void __iomem *target;
|
|
unsigned int bitmapsz;
|
|
|
|
target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
|
|
val64 = be64_to_cpu(readq(target));
|
|
val64 &= ~TAR_SW_BITS;
|
|
writeq(cpu_to_be64(val64), target);
|
|
readq(target); /* flush */
|
|
|
|
bitmapsz = tbl->it_size / BITS_PER_BYTE;
|
|
free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
|
|
tbl->it_map = NULL;
|
|
|
|
kfree(tbl);
|
|
|
|
set_pci_iommu(dev->bus, NULL);
|
|
|
|
/* Can't free bootmem allocated memory after system is up :-( */
|
|
bus_info[dev->bus->number].tce_space = NULL;
|
|
}
|
|
|
|
static void calgary_dump_error_regs(struct iommu_table *tbl)
|
|
{
|
|
void __iomem *bbar = tbl->bbar;
|
|
void __iomem *target;
|
|
u32 csr, plssr;
|
|
|
|
target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
|
|
csr = be32_to_cpu(readl(target));
|
|
|
|
target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
|
|
plssr = be32_to_cpu(readl(target));
|
|
|
|
/* If no error, the agent ID in the CSR is not valid */
|
|
pr_emerg("DMA error on Calgary PHB 0x%x, 0x%08x@CSR 0x%08x@PLSSR\n",
|
|
tbl->it_busno, csr, plssr);
|
|
}
|
|
|
|
static void calioc2_dump_error_regs(struct iommu_table *tbl)
|
|
{
|
|
void __iomem *bbar = tbl->bbar;
|
|
u32 csr, csmr, plssr, mck, rcstat;
|
|
void __iomem *target;
|
|
unsigned long phboff = phb_offset(tbl->it_busno);
|
|
unsigned long erroff;
|
|
u32 errregs[7];
|
|
int i;
|
|
|
|
/* dump CSR */
|
|
target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
|
|
csr = be32_to_cpu(readl(target));
|
|
/* dump PLSSR */
|
|
target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
|
|
plssr = be32_to_cpu(readl(target));
|
|
/* dump CSMR */
|
|
target = calgary_reg(bbar, phboff | 0x290);
|
|
csmr = be32_to_cpu(readl(target));
|
|
/* dump mck */
|
|
target = calgary_reg(bbar, phboff | 0x800);
|
|
mck = be32_to_cpu(readl(target));
|
|
|
|
pr_emerg("DMA error on CalIOC2 PHB 0x%x\n", tbl->it_busno);
|
|
|
|
pr_emerg("0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
|
|
csr, plssr, csmr, mck);
|
|
|
|
/* dump rest of error regs */
|
|
pr_emerg("");
|
|
for (i = 0; i < ARRAY_SIZE(errregs); i++) {
|
|
/* err regs are at 0x810 - 0x870 */
|
|
erroff = (0x810 + (i * 0x10));
|
|
target = calgary_reg(bbar, phboff | erroff);
|
|
errregs[i] = be32_to_cpu(readl(target));
|
|
pr_cont("0x%08x@0x%lx ", errregs[i], erroff);
|
|
}
|
|
pr_cont("\n");
|
|
|
|
/* root complex status */
|
|
target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
|
|
rcstat = be32_to_cpu(readl(target));
|
|
printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
|
|
PHB_ROOT_COMPLEX_STATUS);
|
|
}
|
|
|
|
static void calgary_watchdog(unsigned long data)
|
|
{
|
|
struct pci_dev *dev = (struct pci_dev *)data;
|
|
struct iommu_table *tbl = pci_iommu(dev->bus);
|
|
void __iomem *bbar = tbl->bbar;
|
|
u32 val32;
|
|
void __iomem *target;
|
|
|
|
target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
|
|
val32 = be32_to_cpu(readl(target));
|
|
|
|
/* If no error, the agent ID in the CSR is not valid */
|
|
if (val32 & CSR_AGENT_MASK) {
|
|
tbl->chip_ops->dump_error_regs(tbl);
|
|
|
|
/* reset error */
|
|
writel(0, target);
|
|
|
|
/* Disable bus that caused the error */
|
|
target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
|
|
PHB_CONFIG_RW_OFFSET);
|
|
val32 = be32_to_cpu(readl(target));
|
|
val32 |= PHB_SLOT_DISABLE;
|
|
writel(cpu_to_be32(val32), target);
|
|
readl(target); /* flush */
|
|
} else {
|
|
/* Reset the timer */
|
|
mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
|
|
}
|
|
}
|
|
|
|
static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
|
|
unsigned char busnum, unsigned long timeout)
|
|
{
|
|
u64 val64;
|
|
void __iomem *target;
|
|
unsigned int phb_shift = ~0; /* silence gcc */
|
|
u64 mask;
|
|
|
|
switch (busno_to_phbid(busnum)) {
|
|
case 0: phb_shift = (63 - 19);
|
|
break;
|
|
case 1: phb_shift = (63 - 23);
|
|
break;
|
|
case 2: phb_shift = (63 - 27);
|
|
break;
|
|
case 3: phb_shift = (63 - 35);
|
|
break;
|
|
default:
|
|
BUG_ON(busno_to_phbid(busnum));
|
|
}
|
|
|
|
target = calgary_reg(bbar, CALGARY_CONFIG_REG);
|
|
val64 = be64_to_cpu(readq(target));
|
|
|
|
/* zero out this PHB's timer bits */
|
|
mask = ~(0xFUL << phb_shift);
|
|
val64 &= mask;
|
|
val64 |= (timeout << phb_shift);
|
|
writeq(cpu_to_be64(val64), target);
|
|
readq(target); /* flush */
|
|
}
|
|
|
|
static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
|
|
{
|
|
unsigned char busnum = dev->bus->number;
|
|
void __iomem *bbar = tbl->bbar;
|
|
void __iomem *target;
|
|
u32 val;
|
|
|
|
/*
|
|
* CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
|
|
*/
|
|
target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
|
|
val = cpu_to_be32(readl(target));
|
|
val |= 0x00800000;
|
|
writel(cpu_to_be32(val), target);
|
|
}
|
|
|
|
static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
|
|
{
|
|
unsigned char busnum = dev->bus->number;
|
|
|
|
/*
|
|
* Give split completion a longer timeout on bus 1 for aic94xx
|
|
* http://bugzilla.kernel.org/show_bug.cgi?id=7180
|
|
*/
|
|
if (is_calgary(dev->device) && (busnum == 1))
|
|
calgary_set_split_completion_timeout(tbl->bbar, busnum,
|
|
CCR_2SEC_TIMEOUT);
|
|
}
|
|
|
|
static void __init calgary_enable_translation(struct pci_dev *dev)
|
|
{
|
|
u32 val32;
|
|
unsigned char busnum;
|
|
void __iomem *target;
|
|
void __iomem *bbar;
|
|
struct iommu_table *tbl;
|
|
|
|
busnum = dev->bus->number;
|
|
tbl = pci_iommu(dev->bus);
|
|
bbar = tbl->bbar;
|
|
|
|
/* enable TCE in PHB Config Register */
|
|
target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
|
|
val32 = be32_to_cpu(readl(target));
|
|
val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
|
|
|
|
printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
|
|
(dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
|
|
"Calgary" : "CalIOC2", busnum);
|
|
printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
|
|
"bus.\n");
|
|
|
|
writel(cpu_to_be32(val32), target);
|
|
readl(target); /* flush */
|
|
|
|
init_timer(&tbl->watchdog_timer);
|
|
tbl->watchdog_timer.function = &calgary_watchdog;
|
|
tbl->watchdog_timer.data = (unsigned long)dev;
|
|
mod_timer(&tbl->watchdog_timer, jiffies);
|
|
}
|
|
|
|
static void __init calgary_disable_translation(struct pci_dev *dev)
|
|
{
|
|
u32 val32;
|
|
unsigned char busnum;
|
|
void __iomem *target;
|
|
void __iomem *bbar;
|
|
struct iommu_table *tbl;
|
|
|
|
busnum = dev->bus->number;
|
|
tbl = pci_iommu(dev->bus);
|
|
bbar = tbl->bbar;
|
|
|
|
/* disable TCE in PHB Config Register */
|
|
target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
|
|
val32 = be32_to_cpu(readl(target));
|
|
val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
|
|
|
|
printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
|
|
writel(cpu_to_be32(val32), target);
|
|
readl(target); /* flush */
|
|
|
|
del_timer_sync(&tbl->watchdog_timer);
|
|
}
|
|
|
|
static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
|
|
{
|
|
pci_dev_get(dev);
|
|
set_pci_iommu(dev->bus, NULL);
|
|
|
|
/* is the device behind a bridge? */
|
|
if (dev->bus->parent)
|
|
dev->bus->parent->self = dev;
|
|
else
|
|
dev->bus->self = dev;
|
|
}
|
|
|
|
static int __init calgary_init_one(struct pci_dev *dev)
|
|
{
|
|
void __iomem *bbar;
|
|
struct iommu_table *tbl;
|
|
int ret;
|
|
|
|
bbar = busno_to_bbar(dev->bus->number);
|
|
ret = calgary_setup_tar(dev, bbar);
|
|
if (ret)
|
|
goto done;
|
|
|
|
pci_dev_get(dev);
|
|
|
|
if (dev->bus->parent) {
|
|
if (dev->bus->parent->self)
|
|
printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
|
|
"bus->parent->self!\n", dev);
|
|
dev->bus->parent->self = dev;
|
|
} else
|
|
dev->bus->self = dev;
|
|
|
|
tbl = pci_iommu(dev->bus);
|
|
tbl->chip_ops->handle_quirks(tbl, dev);
|
|
|
|
calgary_enable_translation(dev);
|
|
|
|
return 0;
|
|
|
|
done:
|
|
return ret;
|
|
}
|
|
|
|
static int __init calgary_locate_bbars(void)
|
|
{
|
|
int ret;
|
|
int rioidx, phb, bus;
|
|
void __iomem *bbar;
|
|
void __iomem *target;
|
|
unsigned long offset;
|
|
u8 start_bus, end_bus;
|
|
u32 val;
|
|
|
|
ret = -ENODATA;
|
|
for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
|
|
struct rio_detail *rio = rio_devs[rioidx];
|
|
|
|
if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
|
|
continue;
|
|
|
|
/* map entire 1MB of Calgary config space */
|
|
bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
|
|
if (!bbar)
|
|
goto error;
|
|
|
|
for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
|
|
offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
|
|
target = calgary_reg(bbar, offset);
|
|
|
|
val = be32_to_cpu(readl(target));
|
|
|
|
start_bus = (u8)((val & 0x00FF0000) >> 16);
|
|
end_bus = (u8)((val & 0x0000FF00) >> 8);
|
|
|
|
if (end_bus) {
|
|
for (bus = start_bus; bus <= end_bus; bus++) {
|
|
bus_info[bus].bbar = bbar;
|
|
bus_info[bus].phbid = phb;
|
|
}
|
|
} else {
|
|
bus_info[start_bus].bbar = bbar;
|
|
bus_info[start_bus].phbid = phb;
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
error:
|
|
/* scan bus_info and iounmap any bbars we previously ioremap'd */
|
|
for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
|
|
if (bus_info[bus].bbar)
|
|
iounmap(bus_info[bus].bbar);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __init calgary_init(void)
|
|
{
|
|
int ret;
|
|
struct pci_dev *dev = NULL;
|
|
struct calgary_bus_info *info;
|
|
|
|
ret = calgary_locate_bbars();
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Purely for kdump kernel case */
|
|
if (is_kdump_kernel())
|
|
get_tce_space_from_tar();
|
|
|
|
do {
|
|
dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
|
|
if (!dev)
|
|
break;
|
|
if (!is_cal_pci_dev(dev->device))
|
|
continue;
|
|
|
|
info = &bus_info[dev->bus->number];
|
|
if (info->translation_disabled) {
|
|
calgary_init_one_nontraslated(dev);
|
|
continue;
|
|
}
|
|
|
|
if (!info->tce_space && !translate_empty_slots)
|
|
continue;
|
|
|
|
ret = calgary_init_one(dev);
|
|
if (ret)
|
|
goto error;
|
|
} while (1);
|
|
|
|
dev = NULL;
|
|
for_each_pci_dev(dev) {
|
|
struct iommu_table *tbl;
|
|
|
|
tbl = find_iommu_table(&dev->dev);
|
|
|
|
if (translation_enabled(tbl))
|
|
dev->dev.archdata.dma_ops = &calgary_dma_ops;
|
|
}
|
|
|
|
return ret;
|
|
|
|
error:
|
|
do {
|
|
dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
|
|
if (!dev)
|
|
break;
|
|
if (!is_cal_pci_dev(dev->device))
|
|
continue;
|
|
|
|
info = &bus_info[dev->bus->number];
|
|
if (info->translation_disabled) {
|
|
pci_dev_put(dev);
|
|
continue;
|
|
}
|
|
if (!info->tce_space && !translate_empty_slots)
|
|
continue;
|
|
|
|
calgary_disable_translation(dev);
|
|
calgary_free_bus(dev);
|
|
pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
|
|
dev->dev.archdata.dma_ops = NULL;
|
|
} while (1);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static inline int __init determine_tce_table_size(void)
|
|
{
|
|
int ret;
|
|
|
|
if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
|
|
return specified_table_size;
|
|
|
|
if (is_kdump_kernel() && saved_max_pfn) {
|
|
/*
|
|
* Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
|
|
* TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
|
|
* larger table size has twice as many entries, so shift the
|
|
* max ram address by 13 to divide by 8K and then look at the
|
|
* order of the result to choose between 0-7.
|
|
*/
|
|
ret = get_order((saved_max_pfn * PAGE_SIZE) >> 13);
|
|
if (ret > TCE_TABLE_SIZE_8M)
|
|
ret = TCE_TABLE_SIZE_8M;
|
|
} else {
|
|
/*
|
|
* Use 8M by default (suggested by Muli) if it's not
|
|
* kdump kernel and saved_max_pfn isn't set.
|
|
*/
|
|
ret = TCE_TABLE_SIZE_8M;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __init build_detail_arrays(void)
|
|
{
|
|
unsigned long ptr;
|
|
unsigned numnodes, i;
|
|
int scal_detail_size, rio_detail_size;
|
|
|
|
numnodes = rio_table_hdr->num_scal_dev;
|
|
if (numnodes > MAX_NUMNODES){
|
|
printk(KERN_WARNING
|
|
"Calgary: MAX_NUMNODES too low! Defined as %d, "
|
|
"but system has %d nodes.\n",
|
|
MAX_NUMNODES, numnodes);
|
|
return -ENODEV;
|
|
}
|
|
|
|
switch (rio_table_hdr->version){
|
|
case 2:
|
|
scal_detail_size = 11;
|
|
rio_detail_size = 13;
|
|
break;
|
|
case 3:
|
|
scal_detail_size = 12;
|
|
rio_detail_size = 15;
|
|
break;
|
|
default:
|
|
printk(KERN_WARNING
|
|
"Calgary: Invalid Rio Grande Table Version: %d\n",
|
|
rio_table_hdr->version);
|
|
return -EPROTO;
|
|
}
|
|
|
|
ptr = ((unsigned long)rio_table_hdr) + 3;
|
|
for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
|
|
scal_devs[i] = (struct scal_detail *)ptr;
|
|
|
|
for (i = 0; i < rio_table_hdr->num_rio_dev;
|
|
i++, ptr += rio_detail_size)
|
|
rio_devs[i] = (struct rio_detail *)ptr;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
|
|
{
|
|
int dev;
|
|
u32 val;
|
|
|
|
if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
|
|
/*
|
|
* FIXME: properly scan for devices across the
|
|
* PCI-to-PCI bridge on every CalIOC2 port.
|
|
*/
|
|
return 1;
|
|
}
|
|
|
|
for (dev = 1; dev < 8; dev++) {
|
|
val = read_pci_config(bus, dev, 0, 0);
|
|
if (val != 0xffffffff)
|
|
break;
|
|
}
|
|
return (val != 0xffffffff);
|
|
}
|
|
|
|
/*
|
|
* calgary_init_bitmap_from_tce_table():
|
|
* Function for kdump case. In the second/kdump kernel initialize
|
|
* the bitmap based on the tce table entries obtained from first kernel
|
|
*/
|
|
static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
|
|
{
|
|
u64 *tp;
|
|
unsigned int index;
|
|
tp = ((u64 *)tbl->it_base);
|
|
for (index = 0 ; index < tbl->it_size; index++) {
|
|
if (*tp != 0x0)
|
|
set_bit(index, tbl->it_map);
|
|
tp++;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* get_tce_space_from_tar():
|
|
* Function for kdump case. Get the tce tables from first kernel
|
|
* by reading the contents of the base address register of calgary iommu
|
|
*/
|
|
static void __init get_tce_space_from_tar(void)
|
|
{
|
|
int bus;
|
|
void __iomem *target;
|
|
unsigned long tce_space;
|
|
|
|
for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
|
|
struct calgary_bus_info *info = &bus_info[bus];
|
|
unsigned short pci_device;
|
|
u32 val;
|
|
|
|
val = read_pci_config(bus, 0, 0, 0);
|
|
pci_device = (val & 0xFFFF0000) >> 16;
|
|
|
|
if (!is_cal_pci_dev(pci_device))
|
|
continue;
|
|
if (info->translation_disabled)
|
|
continue;
|
|
|
|
if (calgary_bus_has_devices(bus, pci_device) ||
|
|
translate_empty_slots) {
|
|
target = calgary_reg(bus_info[bus].bbar,
|
|
tar_offset(bus));
|
|
tce_space = be64_to_cpu(readq(target));
|
|
tce_space = tce_space & TAR_SW_BITS;
|
|
|
|
tce_space = tce_space & (~specified_table_size);
|
|
info->tce_space = (u64 *)__va(tce_space);
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
static int __init calgary_iommu_init(void)
|
|
{
|
|
int ret;
|
|
|
|
/* ok, we're trying to use Calgary - let's roll */
|
|
printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
|
|
|
|
ret = calgary_init();
|
|
if (ret) {
|
|
printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
|
|
"falling back to no_iommu\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int __init detect_calgary(void)
|
|
{
|
|
int bus;
|
|
void *tbl;
|
|
int calgary_found = 0;
|
|
unsigned long ptr;
|
|
unsigned int offset, prev_offset;
|
|
int ret;
|
|
|
|
/*
|
|
* if the user specified iommu=off or iommu=soft or we found
|
|
* another HW IOMMU already, bail out.
|
|
*/
|
|
if (no_iommu || iommu_detected)
|
|
return -ENODEV;
|
|
|
|
if (!use_calgary)
|
|
return -ENODEV;
|
|
|
|
if (!early_pci_allowed())
|
|
return -ENODEV;
|
|
|
|
printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
|
|
|
|
ptr = (unsigned long)phys_to_virt(get_bios_ebda());
|
|
|
|
rio_table_hdr = NULL;
|
|
prev_offset = 0;
|
|
offset = 0x180;
|
|
/*
|
|
* The next offset is stored in the 1st word.
|
|
* Only parse up until the offset increases:
|
|
*/
|
|
while (offset > prev_offset) {
|
|
/* The block id is stored in the 2nd word */
|
|
if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
|
|
/* set the pointer past the offset & block id */
|
|
rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
|
|
break;
|
|
}
|
|
prev_offset = offset;
|
|
offset = *((unsigned short *)(ptr + offset));
|
|
}
|
|
if (!rio_table_hdr) {
|
|
printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
|
|
"in EBDA - bailing!\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = build_detail_arrays();
|
|
if (ret) {
|
|
printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
specified_table_size = determine_tce_table_size();
|
|
|
|
for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
|
|
struct calgary_bus_info *info = &bus_info[bus];
|
|
unsigned short pci_device;
|
|
u32 val;
|
|
|
|
val = read_pci_config(bus, 0, 0, 0);
|
|
pci_device = (val & 0xFFFF0000) >> 16;
|
|
|
|
if (!is_cal_pci_dev(pci_device))
|
|
continue;
|
|
|
|
if (info->translation_disabled)
|
|
continue;
|
|
|
|
if (calgary_bus_has_devices(bus, pci_device) ||
|
|
translate_empty_slots) {
|
|
/*
|
|
* If it is kdump kernel, find and use tce tables
|
|
* from first kernel, else allocate tce tables here
|
|
*/
|
|
if (!is_kdump_kernel()) {
|
|
tbl = alloc_tce_table();
|
|
if (!tbl)
|
|
goto cleanup;
|
|
info->tce_space = tbl;
|
|
}
|
|
calgary_found = 1;
|
|
}
|
|
}
|
|
|
|
printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
|
|
calgary_found ? "found" : "not found");
|
|
|
|
if (calgary_found) {
|
|
iommu_detected = 1;
|
|
calgary_detected = 1;
|
|
printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
|
|
printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n",
|
|
specified_table_size);
|
|
|
|
x86_init.iommu.iommu_init = calgary_iommu_init;
|
|
}
|
|
return calgary_found;
|
|
|
|
cleanup:
|
|
for (--bus; bus >= 0; --bus) {
|
|
struct calgary_bus_info *info = &bus_info[bus];
|
|
|
|
if (info->tce_space)
|
|
free_tce_table(info->tce_space);
|
|
}
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static int __init calgary_parse_options(char *p)
|
|
{
|
|
unsigned int bridge;
|
|
unsigned long val;
|
|
size_t len;
|
|
ssize_t ret;
|
|
|
|
while (*p) {
|
|
if (!strncmp(p, "64k", 3))
|
|
specified_table_size = TCE_TABLE_SIZE_64K;
|
|
else if (!strncmp(p, "128k", 4))
|
|
specified_table_size = TCE_TABLE_SIZE_128K;
|
|
else if (!strncmp(p, "256k", 4))
|
|
specified_table_size = TCE_TABLE_SIZE_256K;
|
|
else if (!strncmp(p, "512k", 4))
|
|
specified_table_size = TCE_TABLE_SIZE_512K;
|
|
else if (!strncmp(p, "1M", 2))
|
|
specified_table_size = TCE_TABLE_SIZE_1M;
|
|
else if (!strncmp(p, "2M", 2))
|
|
specified_table_size = TCE_TABLE_SIZE_2M;
|
|
else if (!strncmp(p, "4M", 2))
|
|
specified_table_size = TCE_TABLE_SIZE_4M;
|
|
else if (!strncmp(p, "8M", 2))
|
|
specified_table_size = TCE_TABLE_SIZE_8M;
|
|
|
|
len = strlen("translate_empty_slots");
|
|
if (!strncmp(p, "translate_empty_slots", len))
|
|
translate_empty_slots = 1;
|
|
|
|
len = strlen("disable");
|
|
if (!strncmp(p, "disable", len)) {
|
|
p += len;
|
|
if (*p == '=')
|
|
++p;
|
|
if (*p == '\0')
|
|
break;
|
|
ret = kstrtoul(p, 0, &val);
|
|
if (ret)
|
|
break;
|
|
|
|
bridge = val;
|
|
if (bridge < MAX_PHB_BUS_NUM) {
|
|
printk(KERN_INFO "Calgary: disabling "
|
|
"translation for PHB %#x\n", bridge);
|
|
bus_info[bridge].translation_disabled = 1;
|
|
}
|
|
}
|
|
|
|
p = strpbrk(p, ",");
|
|
if (!p)
|
|
break;
|
|
|
|
p++; /* skip ',' */
|
|
}
|
|
return 1;
|
|
}
|
|
__setup("calgary=", calgary_parse_options);
|
|
|
|
static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
|
|
{
|
|
struct iommu_table *tbl;
|
|
unsigned int npages;
|
|
int i;
|
|
|
|
tbl = pci_iommu(dev->bus);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
|
|
|
|
/* Don't give out TCEs that map MEM resources */
|
|
if (!(r->flags & IORESOURCE_MEM))
|
|
continue;
|
|
|
|
/* 0-based? we reserve the whole 1st MB anyway */
|
|
if (!r->start)
|
|
continue;
|
|
|
|
/* cover the whole region */
|
|
npages = resource_size(r) >> PAGE_SHIFT;
|
|
npages++;
|
|
|
|
iommu_range_reserve(tbl, r->start, npages);
|
|
}
|
|
}
|
|
|
|
static int __init calgary_fixup_tce_spaces(void)
|
|
{
|
|
struct pci_dev *dev = NULL;
|
|
struct calgary_bus_info *info;
|
|
|
|
if (no_iommu || swiotlb || !calgary_detected)
|
|
return -ENODEV;
|
|
|
|
printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
|
|
|
|
do {
|
|
dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
|
|
if (!dev)
|
|
break;
|
|
if (!is_cal_pci_dev(dev->device))
|
|
continue;
|
|
|
|
info = &bus_info[dev->bus->number];
|
|
if (info->translation_disabled)
|
|
continue;
|
|
|
|
if (!info->tce_space)
|
|
continue;
|
|
|
|
calgary_fixup_one_tce_space(dev);
|
|
|
|
} while (1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* We need to be call after pcibios_assign_resources (fs_initcall level)
|
|
* and before device_initcall.
|
|
*/
|
|
rootfs_initcall(calgary_fixup_tce_spaces);
|
|
|
|
IOMMU_INIT_POST(detect_calgary);
|