246 строки
5.7 KiB
C
246 строки
5.7 KiB
C
/*
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* vSMPowered(tm) systems specific initialization
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* Copyright (C) 2005 ScaleMP Inc.
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*
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* Use of this code is subject to the terms and conditions of the
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* GNU general public license version 2. See "COPYING" or
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* http://www.gnu.org/licenses/gpl.html
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*
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* Ravikiran Thirumalai <kiran@scalemp.com>,
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* Shai Fultheim <shai@scalemp.com>
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* Paravirt ops integration: Glauber de Oliveira Costa <gcosta@redhat.com>,
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* Ravikiran Thirumalai <kiran@scalemp.com>
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*/
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#include <linux/init.h>
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#include <linux/pci_ids.h>
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#include <linux/pci_regs.h>
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <asm/apic.h>
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#include <asm/pci-direct.h>
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#include <asm/io.h>
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#include <asm/paravirt.h>
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#include <asm/setup.h>
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#define TOPOLOGY_REGISTER_OFFSET 0x10
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/* Flag below is initialized once during vSMP PCI initialization. */
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static int irq_routing_comply = 1;
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#if defined CONFIG_PCI && defined CONFIG_PARAVIRT
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/*
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* Interrupt control on vSMPowered systems:
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* ~AC is a shadow of IF. If IF is 'on' AC should be 'off'
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* and vice versa.
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*/
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asmlinkage __visible unsigned long vsmp_save_fl(void)
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{
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unsigned long flags = native_save_fl();
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if (!(flags & X86_EFLAGS_IF) || (flags & X86_EFLAGS_AC))
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flags &= ~X86_EFLAGS_IF;
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return flags;
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}
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PV_CALLEE_SAVE_REGS_THUNK(vsmp_save_fl);
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__visible void vsmp_restore_fl(unsigned long flags)
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{
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if (flags & X86_EFLAGS_IF)
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flags &= ~X86_EFLAGS_AC;
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else
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flags |= X86_EFLAGS_AC;
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native_restore_fl(flags);
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}
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PV_CALLEE_SAVE_REGS_THUNK(vsmp_restore_fl);
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asmlinkage __visible void vsmp_irq_disable(void)
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{
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unsigned long flags = native_save_fl();
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native_restore_fl((flags & ~X86_EFLAGS_IF) | X86_EFLAGS_AC);
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}
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PV_CALLEE_SAVE_REGS_THUNK(vsmp_irq_disable);
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asmlinkage __visible void vsmp_irq_enable(void)
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{
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unsigned long flags = native_save_fl();
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native_restore_fl((flags | X86_EFLAGS_IF) & (~X86_EFLAGS_AC));
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}
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PV_CALLEE_SAVE_REGS_THUNK(vsmp_irq_enable);
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static unsigned __init vsmp_patch(u8 type, u16 clobbers, void *ibuf,
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unsigned long addr, unsigned len)
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{
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switch (type) {
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case PARAVIRT_PATCH(pv_irq_ops.irq_enable):
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case PARAVIRT_PATCH(pv_irq_ops.irq_disable):
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case PARAVIRT_PATCH(pv_irq_ops.save_fl):
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case PARAVIRT_PATCH(pv_irq_ops.restore_fl):
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return paravirt_patch_default(type, clobbers, ibuf, addr, len);
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default:
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return native_patch(type, clobbers, ibuf, addr, len);
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}
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}
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static void __init set_vsmp_pv_ops(void)
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{
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void __iomem *address;
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unsigned int cap, ctl, cfg;
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/* set vSMP magic bits to indicate vSMP capable kernel */
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cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0);
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address = early_ioremap(cfg, 8);
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cap = readl(address);
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ctl = readl(address + 4);
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printk(KERN_INFO "vSMP CTL: capabilities:0x%08x control:0x%08x\n",
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cap, ctl);
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/* If possible, let the vSMP foundation route the interrupt optimally */
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#ifdef CONFIG_SMP
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if (cap & ctl & BIT(8)) {
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ctl &= ~BIT(8);
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/* Interrupt routing set to ignore */
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irq_routing_comply = 0;
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#ifdef CONFIG_PROC_FS
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/* Don't let users change irq affinity via procfs */
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no_irq_affinity = 1;
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#endif
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}
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#endif
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if (cap & ctl & (1 << 4)) {
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/* Setup irq ops and turn on vSMP IRQ fastpath handling */
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pv_irq_ops.irq_disable = PV_CALLEE_SAVE(vsmp_irq_disable);
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pv_irq_ops.irq_enable = PV_CALLEE_SAVE(vsmp_irq_enable);
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pv_irq_ops.save_fl = PV_CALLEE_SAVE(vsmp_save_fl);
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pv_irq_ops.restore_fl = PV_CALLEE_SAVE(vsmp_restore_fl);
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pv_init_ops.patch = vsmp_patch;
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ctl &= ~(1 << 4);
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}
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writel(ctl, address + 4);
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ctl = readl(address + 4);
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pr_info("vSMP CTL: control set to:0x%08x\n", ctl);
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early_iounmap(address, 8);
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}
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#else
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static void __init set_vsmp_pv_ops(void)
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{
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}
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#endif
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#ifdef CONFIG_PCI
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static int is_vsmp = -1;
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static void __init detect_vsmp_box(void)
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{
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is_vsmp = 0;
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if (!early_pci_allowed())
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return;
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/* Check if we are running on a ScaleMP vSMPowered box */
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if (read_pci_config(0, 0x1f, 0, PCI_VENDOR_ID) ==
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(PCI_VENDOR_ID_SCALEMP | (PCI_DEVICE_ID_SCALEMP_VSMP_CTL << 16)))
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is_vsmp = 1;
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}
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static int is_vsmp_box(void)
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{
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if (is_vsmp != -1)
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return is_vsmp;
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else {
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WARN_ON_ONCE(1);
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return 0;
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}
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}
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#else
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static void __init detect_vsmp_box(void)
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{
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}
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static int is_vsmp_box(void)
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{
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return 0;
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}
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#endif
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static void __init vsmp_cap_cpus(void)
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{
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#if !defined(CONFIG_X86_VSMP) && defined(CONFIG_SMP)
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void __iomem *address;
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unsigned int cfg, topology, node_shift, maxcpus;
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/*
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* CONFIG_X86_VSMP is not configured, so limit the number CPUs to the
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* ones present in the first board, unless explicitly overridden by
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* setup_max_cpus
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*/
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if (setup_max_cpus != NR_CPUS)
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return;
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/* Read the vSMP Foundation topology register */
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cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0);
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address = early_ioremap(cfg + TOPOLOGY_REGISTER_OFFSET, 4);
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if (WARN_ON(!address))
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return;
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topology = readl(address);
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node_shift = (topology >> 16) & 0x7;
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if (!node_shift)
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/* The value 0 should be decoded as 8 */
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node_shift = 8;
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maxcpus = (topology & ((1 << node_shift) - 1)) + 1;
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pr_info("vSMP CTL: Capping CPUs to %d (CONFIG_X86_VSMP is unset)\n",
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maxcpus);
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setup_max_cpus = maxcpus;
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early_iounmap(address, 4);
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#endif
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}
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static int apicid_phys_pkg_id(int initial_apic_id, int index_msb)
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{
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return hard_smp_processor_id() >> index_msb;
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}
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/*
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* In vSMP, all cpus should be capable of handling interrupts, regardless of
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* the APIC used.
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*/
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static void fill_vector_allocation_domain(int cpu, struct cpumask *retmask,
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const struct cpumask *mask)
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{
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cpumask_setall(retmask);
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}
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static void vsmp_apic_post_init(void)
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{
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/* need to update phys_pkg_id */
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apic->phys_pkg_id = apicid_phys_pkg_id;
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if (!irq_routing_comply)
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apic->vector_allocation_domain = fill_vector_allocation_domain;
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}
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void __init vsmp_init(void)
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{
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detect_vsmp_box();
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if (!is_vsmp_box())
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return;
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x86_platform.apic_post_init = vsmp_apic_post_init;
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vsmp_cap_cpus();
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set_vsmp_pv_ops();
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return;
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}
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