394 строки
9.3 KiB
C
394 строки
9.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 HiSilicon Limited, All Rights Reserved.
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* Author: Jun Ma <majun258@huawei.com>
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* Author: Yun Wu <wuyun.wu@huawei.com>
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*/
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#include <linux/acpi.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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/* Interrupt numbers per mbigen node supported */
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#define IRQS_PER_MBIGEN_NODE 128
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/* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
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#define RESERVED_IRQ_PER_MBIGEN_CHIP 64
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/* The maximum IRQ pin number of mbigen chip(start from 0) */
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#define MAXIMUM_IRQ_PIN_NUM 1407
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/**
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* In mbigen vector register
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* bit[21:12]: event id value
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* bit[11:0]: device id
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*/
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#define IRQ_EVENT_ID_SHIFT 12
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#define IRQ_EVENT_ID_MASK 0x3ff
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/* register range of each mbigen node */
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#define MBIGEN_NODE_OFFSET 0x1000
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/* offset of vector register in mbigen node */
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#define REG_MBIGEN_VEC_OFFSET 0x200
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/**
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* offset of clear register in mbigen node
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* This register is used to clear the status
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* of interrupt
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*/
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#define REG_MBIGEN_CLEAR_OFFSET 0xa000
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/**
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* offset of interrupt type register
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* This register is used to configure interrupt
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* trigger type
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*/
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#define REG_MBIGEN_TYPE_OFFSET 0x0
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/**
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* struct mbigen_device - holds the information of mbigen device.
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*
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* @pdev: pointer to the platform device structure of mbigen chip.
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* @base: mapped address of this mbigen chip.
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*/
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struct mbigen_device {
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struct platform_device *pdev;
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void __iomem *base;
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};
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static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
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{
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unsigned int nid, pin;
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hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
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nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
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pin = hwirq % IRQS_PER_MBIGEN_NODE;
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return pin * 4 + nid * MBIGEN_NODE_OFFSET
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+ REG_MBIGEN_VEC_OFFSET;
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}
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static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
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u32 *mask, u32 *addr)
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{
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unsigned int nid, irq_ofst, ofst;
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hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
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nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
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irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
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*mask = 1 << (irq_ofst % 32);
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ofst = irq_ofst / 32 * 4;
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*addr = ofst + nid * MBIGEN_NODE_OFFSET
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+ REG_MBIGEN_TYPE_OFFSET;
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}
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static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
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u32 *mask, u32 *addr)
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{
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unsigned int ofst = (hwirq / 32) * 4;
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*mask = 1 << (hwirq % 32);
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*addr = ofst + REG_MBIGEN_CLEAR_OFFSET;
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}
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static void mbigen_eoi_irq(struct irq_data *data)
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{
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void __iomem *base = data->chip_data;
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u32 mask, addr;
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get_mbigen_clear_reg(data->hwirq, &mask, &addr);
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writel_relaxed(mask, base + addr);
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irq_chip_eoi_parent(data);
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}
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static int mbigen_set_type(struct irq_data *data, unsigned int type)
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{
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void __iomem *base = data->chip_data;
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u32 mask, addr, val;
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if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
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return -EINVAL;
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get_mbigen_type_reg(data->hwirq, &mask, &addr);
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val = readl_relaxed(base + addr);
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if (type == IRQ_TYPE_LEVEL_HIGH)
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val |= mask;
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else
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val &= ~mask;
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writel_relaxed(val, base + addr);
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return 0;
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}
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static struct irq_chip mbigen_irq_chip = {
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.name = "mbigen-v2",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = mbigen_eoi_irq,
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.irq_set_type = mbigen_set_type,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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};
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static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
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{
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struct irq_data *d = irq_get_irq_data(desc->irq);
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void __iomem *base = d->chip_data;
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u32 val;
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if (!msg->address_lo && !msg->address_hi)
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return;
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base += get_mbigen_vec_reg(d->hwirq);
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val = readl_relaxed(base);
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val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
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val |= (msg->data << IRQ_EVENT_ID_SHIFT);
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/* The address of doorbell is encoded in mbigen register by default
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* So,we don't need to program the doorbell address at here
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*/
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writel_relaxed(val, base);
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}
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static int mbigen_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) {
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if (fwspec->param_count != 2)
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return -EINVAL;
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if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
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(fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
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return -EINVAL;
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else
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*hwirq = fwspec->param[0];
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/* If there is no valid irq type, just use the default type */
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if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
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(fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
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*type = fwspec->param[1];
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else
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return -EINVAL;
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return 0;
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}
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return -EINVAL;
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}
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static int mbigen_irq_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs,
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void *args)
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{
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struct irq_fwspec *fwspec = args;
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irq_hw_number_t hwirq;
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unsigned int type;
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struct mbigen_device *mgn_chip;
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int i, err;
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err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
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if (err)
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return err;
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err = platform_msi_domain_alloc(domain, virq, nr_irqs);
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if (err)
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return err;
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mgn_chip = platform_msi_get_host_data(domain);
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
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&mbigen_irq_chip, mgn_chip->base);
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return 0;
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}
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static void mbigen_irq_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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platform_msi_domain_free(domain, virq, nr_irqs);
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}
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static const struct irq_domain_ops mbigen_domain_ops = {
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.translate = mbigen_domain_translate,
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.alloc = mbigen_irq_domain_alloc,
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.free = mbigen_irq_domain_free,
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};
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static int mbigen_of_create_domain(struct platform_device *pdev,
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struct mbigen_device *mgn_chip)
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{
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struct device *parent;
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struct platform_device *child;
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struct irq_domain *domain;
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struct device_node *np;
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u32 num_pins;
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for_each_child_of_node(pdev->dev.of_node, np) {
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if (!of_property_read_bool(np, "interrupt-controller"))
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continue;
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parent = platform_bus_type.dev_root;
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child = of_platform_device_create(np, NULL, parent);
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if (!child) {
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of_node_put(np);
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return -ENOMEM;
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}
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if (of_property_read_u32(child->dev.of_node, "num-pins",
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&num_pins) < 0) {
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dev_err(&pdev->dev, "No num-pins property\n");
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of_node_put(np);
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return -EINVAL;
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}
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domain = platform_msi_create_device_domain(&child->dev, num_pins,
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mbigen_write_msg,
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&mbigen_domain_ops,
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mgn_chip);
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if (!domain) {
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of_node_put(np);
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return -ENOMEM;
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}
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}
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return 0;
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}
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#ifdef CONFIG_ACPI
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static int mbigen_acpi_create_domain(struct platform_device *pdev,
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struct mbigen_device *mgn_chip)
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{
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struct irq_domain *domain;
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u32 num_pins = 0;
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int ret;
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/*
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* "num-pins" is the total number of interrupt pins implemented in
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* this mbigen instance, and mbigen is an interrupt controller
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* connected to ITS converting wired interrupts into MSI, so we
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* use "num-pins" to alloc MSI vectors which are needed by client
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* devices connected to it.
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*
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* Here is the DSDT device node used for mbigen in firmware:
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* Device(MBI0) {
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* Name(_HID, "HISI0152")
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* Name(_UID, Zero)
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* Name(_CRS, ResourceTemplate() {
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* Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
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* })
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*
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* Name(_DSD, Package () {
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* ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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* Package () {
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* Package () {"num-pins", 378}
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* }
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* })
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* }
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*/
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ret = device_property_read_u32(&pdev->dev, "num-pins", &num_pins);
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if (ret || num_pins == 0)
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return -EINVAL;
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domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
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mbigen_write_msg,
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&mbigen_domain_ops,
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mgn_chip);
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if (!domain)
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return -ENOMEM;
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return 0;
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}
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#else
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static inline int mbigen_acpi_create_domain(struct platform_device *pdev,
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struct mbigen_device *mgn_chip)
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{
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return -ENODEV;
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}
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#endif
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static int mbigen_device_probe(struct platform_device *pdev)
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{
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struct mbigen_device *mgn_chip;
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struct resource *res;
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int err;
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mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
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if (!mgn_chip)
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return -ENOMEM;
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mgn_chip->pdev = pdev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -EINVAL;
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mgn_chip->base = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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if (!mgn_chip->base) {
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dev_err(&pdev->dev, "failed to ioremap %pR\n", res);
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return -ENOMEM;
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}
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if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
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err = mbigen_of_create_domain(pdev, mgn_chip);
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else if (ACPI_COMPANION(&pdev->dev))
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err = mbigen_acpi_create_domain(pdev, mgn_chip);
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else
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err = -EINVAL;
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if (err) {
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dev_err(&pdev->dev, "Failed to create mbi-gen irqdomain\n");
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return err;
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}
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platform_set_drvdata(pdev, mgn_chip);
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return 0;
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}
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static const struct of_device_id mbigen_of_match[] = {
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{ .compatible = "hisilicon,mbigen-v2" },
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{ /* END */ }
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};
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MODULE_DEVICE_TABLE(of, mbigen_of_match);
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static const struct acpi_device_id mbigen_acpi_match[] = {
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{ "HISI0152", 0 },
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{}
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};
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MODULE_DEVICE_TABLE(acpi, mbigen_acpi_match);
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static struct platform_driver mbigen_platform_driver = {
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.driver = {
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.name = "Hisilicon MBIGEN-V2",
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.of_match_table = mbigen_of_match,
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.acpi_match_table = ACPI_PTR(mbigen_acpi_match),
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.suppress_bind_attrs = true,
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},
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.probe = mbigen_device_probe,
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};
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module_platform_driver(mbigen_platform_driver);
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MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
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MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("HiSilicon MBI Generator driver");
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