WSL2-Linux-Kernel/arch/riscv/kernel
Linus Torvalds 2d385336af Updates for the interrupt subsystem:
Treewide:
 
     - Cleanup of setup_irq() which is not longer required because the
       memory allocator is available early. Most cleanup changes come
       through the various maintainer trees, so the final removal of
       setup_irq() is postponed towards the end of the merge window.
 
   Core:
 
     - Protection against unsafe invocation of interrupt handlers and unsafe
       interrupt injection including a fixup of the offending PCI/AER error
       injection mechanism.
 
       Invoking interrupt handlers from arbitrary contexts, i.e. outside of
       an actual interrupt, can cause inconsistent state on the fragile
       x86 interrupt affinity changing hardware trainwreck.
 
   Drivers:
 
     - Second wave of support for the new ARM GICv4.1
     - Multi-instance support for Xilinx and PLIC interrupt controllers
     - CPU-Hotplug support for PLIC
     - The obligatory new driver for X1000 TCU
     - Enhancements, cleanups and fixes all over the place
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Merge tag 'irq-core-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq updates from Thomas Gleixner:
 "Updates for the interrupt subsystem:

  Treewide:

    - Cleanup of setup_irq() which is not longer required because the
      memory allocator is available early.

      Most cleanup changes come through the various maintainer trees, so
      the final removal of setup_irq() is postponed towards the end of
      the merge window.

  Core:

    - Protection against unsafe invocation of interrupt handlers and
      unsafe interrupt injection including a fixup of the offending
      PCI/AER error injection mechanism.

      Invoking interrupt handlers from arbitrary contexts, i.e. outside
      of an actual interrupt, can cause inconsistent state on the
      fragile x86 interrupt affinity changing hardware trainwreck.

  Drivers:

    - Second wave of support for the new ARM GICv4.1

    - Multi-instance support for Xilinx and PLIC interrupt controllers

    - CPU-Hotplug support for PLIC

    - The obligatory new driver for X1000 TCU

    - Enhancements, cleanups and fixes all over the place"

* tag 'irq-core-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (58 commits)
  unicore32: Replace setup_irq() by request_irq()
  sh: Replace setup_irq() by request_irq()
  hexagon: Replace setup_irq() by request_irq()
  c6x: Replace setup_irq() by request_irq()
  alpha: Replace setup_irq() by request_irq()
  irqchip/gic-v4.1: Eagerly vmap vPEs
  irqchip/gic-v4.1: Add VSGI property setup
  irqchip/gic-v4.1: Add VSGI allocation/teardown
  irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction layer
  irqchip/gic-v4.1: Plumb set_vcpu_affinity SGI callbacks
  irqchip/gic-v4.1: Plumb get/set_irqchip_state SGI callbacks
  irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks
  irqchip/gic-v4.1: Add initial SGI configuration
  irqchip/gic-v4.1: Plumb skeletal VSGI irqchip
  irqchip/stm32: Retrigger both in eoi and unmask callbacks
  irqchip/gic-v3: Move irq_domain_update_bus_token to after checking for NULL domain
  irqchip/xilinx: Do not call irq_set_default_host()
  irqchip/xilinx: Enable generic irq multi handler
  irqchip/xilinx: Fill error code when irq domain registration fails
  irqchip/xilinx: Add support for multiple instances
  ...
2020-03-30 17:35:14 -07:00
..
vdso riscv: delete temporary files 2020-01-18 13:22:13 -08:00
.gitignore RISC-V: Build Infrastructure 2017-09-26 15:26:49 -07:00
Makefile riscv: add nommu support 2019-11-17 15:17:39 -08:00
asm-offsets.c riscv: abstract out CSR names for supervisor vs machine mode 2019-11-05 09:20:42 -08:00
cacheinfo.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
clint.c riscv: provide native clint access for M-mode 2019-11-17 15:17:39 -08:00
cpu.c RISC-V: Remove unsupported isa string info print 2019-10-28 11:13:59 -07:00
cpufeature.c riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
entry.S riscv: fix seccomp reject syscall code path 2020-03-05 13:58:15 -08:00
fpu.S riscv: abstract out CSR names for supervisor vs machine mode 2019-11-05 09:20:42 -08:00
ftrace.c riscv: ftrace: correct the condition logic in function graph tracer 2020-01-03 00:56:37 -08:00
head.S riscv: set pmp configuration if kernel is running in M-mode 2020-02-18 09:41:24 -08:00
head.h riscv: add prototypes for assembly language functions from head.S 2019-10-28 00:46:00 -07:00
irq.c riscv: prefix IRQ_ macro names with an RV_ namespace 2020-01-04 21:48:59 -08:00
mcount-dyn.S riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support 2018-04-02 19:59:13 -07:00
mcount.S RISC-V: remove the unused return_to_handler export 2018-10-22 17:38:12 -07:00
module-sections.c riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
module.c riscv: avoid the PIC offset of static percpu data in module beyond 2G limits 2020-03-03 10:27:45 -08:00
module.lds RISC-V: Add section of GOT.PLT for kernel module 2018-04-02 20:00:54 -07:00
perf_callchain.c riscv: abstract out CSR names for supervisor vs machine mode 2019-11-05 09:20:42 -08:00
perf_event.c RISC-V: Access CSRs using CSR numbers 2019-05-16 20:42:11 -07:00
perf_regs.c riscv: Add support for perf registers sampling 2019-09-05 00:48:58 -07:00
process.c riscv: Implement copy_thread_tls 2020-01-07 13:31:23 +01:00
ptrace.c riscv: fix seccomp reject syscall code path 2020-03-05 13:58:15 -08:00
reset.c riscv: cleanup the default power off implementation 2019-11-13 13:22:52 -08:00
riscv_ksyms.c riscv: Add KASAN support 2020-01-22 13:09:58 -08:00
sbi.c riscv: cleanup the default power off implementation 2019-11-13 13:22:52 -08:00
setup.c RISC-V Patches for the 5.6 Merge Window, Part 1 2020-01-31 11:23:29 -08:00
signal.c riscv: add nommu support 2019-11-17 15:17:39 -08:00
smp.c riscv: fix the IPI missing issue in nommu mode 2020-03-18 18:44:39 -07:00
smpboot.c riscv: provide native clint access for M-mode 2019-11-17 15:17:39 -08:00
stacktrace.c riscv: Add perf callchain support 2019-09-04 12:43:00 -07:00
sys_riscv.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
syscall_table.c riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
time.c riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
traps.c irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline 2020-03-16 15:48:54 +00:00
vdso.c riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
vmlinux.lds.S riscv: Add KASAN support 2020-01-22 13:09:58 -08:00