700 строки
15 KiB
C
700 строки
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef NVM_H
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#define NVM_H
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#include <linux/blkdev.h>
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#include <linux/types.h>
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#include <uapi/linux/lightnvm.h>
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enum {
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NVM_IO_OK = 0,
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NVM_IO_REQUEUE = 1,
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NVM_IO_DONE = 2,
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NVM_IO_ERR = 3,
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NVM_IOTYPE_NONE = 0,
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NVM_IOTYPE_GC = 1,
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};
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/* common format */
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#define NVM_GEN_CH_BITS (8)
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#define NVM_GEN_LUN_BITS (8)
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#define NVM_GEN_BLK_BITS (16)
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#define NVM_GEN_RESERVED (32)
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/* 1.2 format */
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#define NVM_12_PG_BITS (16)
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#define NVM_12_PL_BITS (4)
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#define NVM_12_SEC_BITS (4)
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#define NVM_12_RESERVED (8)
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/* 2.0 format */
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#define NVM_20_SEC_BITS (24)
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#define NVM_20_RESERVED (8)
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enum {
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NVM_OCSSD_SPEC_12 = 12,
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NVM_OCSSD_SPEC_20 = 20,
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};
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struct ppa_addr {
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/* Generic structure for all addresses */
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union {
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/* generic device format */
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struct {
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u64 ch : NVM_GEN_CH_BITS;
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u64 lun : NVM_GEN_LUN_BITS;
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u64 blk : NVM_GEN_BLK_BITS;
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u64 reserved : NVM_GEN_RESERVED;
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} a;
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/* 1.2 device format */
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struct {
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u64 ch : NVM_GEN_CH_BITS;
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u64 lun : NVM_GEN_LUN_BITS;
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u64 blk : NVM_GEN_BLK_BITS;
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u64 pg : NVM_12_PG_BITS;
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u64 pl : NVM_12_PL_BITS;
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u64 sec : NVM_12_SEC_BITS;
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u64 reserved : NVM_12_RESERVED;
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} g;
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/* 2.0 device format */
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struct {
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u64 grp : NVM_GEN_CH_BITS;
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u64 pu : NVM_GEN_LUN_BITS;
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u64 chk : NVM_GEN_BLK_BITS;
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u64 sec : NVM_20_SEC_BITS;
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u64 reserved : NVM_20_RESERVED;
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} m;
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struct {
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u64 line : 63;
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u64 is_cached : 1;
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} c;
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u64 ppa;
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};
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};
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struct nvm_rq;
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struct nvm_id;
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struct nvm_dev;
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struct nvm_tgt_dev;
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struct nvm_chk_meta;
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typedef int (nvm_id_fn)(struct nvm_dev *);
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typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev *, struct ppa_addr, u8 *);
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typedef int (nvm_op_set_bb_fn)(struct nvm_dev *, struct ppa_addr *, int, int);
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typedef int (nvm_get_chk_meta_fn)(struct nvm_dev *, sector_t, int,
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struct nvm_chk_meta *);
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typedef int (nvm_submit_io_fn)(struct nvm_dev *, struct nvm_rq *);
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typedef int (nvm_submit_io_sync_fn)(struct nvm_dev *, struct nvm_rq *);
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typedef void *(nvm_create_dma_pool_fn)(struct nvm_dev *, char *);
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typedef void (nvm_destroy_dma_pool_fn)(void *);
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typedef void *(nvm_dev_dma_alloc_fn)(struct nvm_dev *, void *, gfp_t,
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dma_addr_t *);
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typedef void (nvm_dev_dma_free_fn)(void *, void*, dma_addr_t);
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struct nvm_dev_ops {
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nvm_id_fn *identity;
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nvm_op_bb_tbl_fn *get_bb_tbl;
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nvm_op_set_bb_fn *set_bb_tbl;
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nvm_get_chk_meta_fn *get_chk_meta;
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nvm_submit_io_fn *submit_io;
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nvm_submit_io_sync_fn *submit_io_sync;
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nvm_create_dma_pool_fn *create_dma_pool;
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nvm_destroy_dma_pool_fn *destroy_dma_pool;
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nvm_dev_dma_alloc_fn *dev_dma_alloc;
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nvm_dev_dma_free_fn *dev_dma_free;
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};
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#ifdef CONFIG_NVM
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#include <linux/blkdev.h>
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#include <linux/file.h>
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#include <linux/dmapool.h>
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#include <uapi/linux/lightnvm.h>
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enum {
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/* HW Responsibilities */
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NVM_RSP_L2P = 1 << 0,
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NVM_RSP_ECC = 1 << 1,
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/* Physical Adressing Mode */
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NVM_ADDRMODE_LINEAR = 0,
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NVM_ADDRMODE_CHANNEL = 1,
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/* Plane programming mode for LUN */
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NVM_PLANE_SINGLE = 1,
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NVM_PLANE_DOUBLE = 2,
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NVM_PLANE_QUAD = 4,
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/* Status codes */
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NVM_RSP_SUCCESS = 0x0,
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NVM_RSP_NOT_CHANGEABLE = 0x1,
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NVM_RSP_ERR_FAILWRITE = 0x40ff,
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NVM_RSP_ERR_EMPTYPAGE = 0x42ff,
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NVM_RSP_ERR_FAILECC = 0x4281,
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NVM_RSP_ERR_FAILCRC = 0x4004,
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NVM_RSP_WARN_HIGHECC = 0x4700,
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/* Device opcodes */
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NVM_OP_PWRITE = 0x91,
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NVM_OP_PREAD = 0x92,
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NVM_OP_ERASE = 0x90,
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/* PPA Command Flags */
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NVM_IO_SNGL_ACCESS = 0x0,
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NVM_IO_DUAL_ACCESS = 0x1,
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NVM_IO_QUAD_ACCESS = 0x2,
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/* NAND Access Modes */
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NVM_IO_SUSPEND = 0x80,
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NVM_IO_SLC_MODE = 0x100,
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NVM_IO_SCRAMBLE_ENABLE = 0x200,
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/* Block Types */
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NVM_BLK_T_FREE = 0x0,
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NVM_BLK_T_BAD = 0x1,
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NVM_BLK_T_GRWN_BAD = 0x2,
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NVM_BLK_T_DEV = 0x4,
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NVM_BLK_T_HOST = 0x8,
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/* Memory capabilities */
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NVM_ID_CAP_SLC = 0x1,
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NVM_ID_CAP_CMD_SUSPEND = 0x2,
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NVM_ID_CAP_SCRAMBLE = 0x4,
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NVM_ID_CAP_ENCRYPT = 0x8,
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/* Memory types */
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NVM_ID_FMTYPE_SLC = 0,
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NVM_ID_FMTYPE_MLC = 1,
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/* Device capabilities */
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NVM_ID_DCAP_BBLKMGMT = 0x1,
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NVM_UD_DCAP_ECC = 0x2,
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};
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struct nvm_id_lp_mlc {
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u16 num_pairs;
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u8 pairs[886];
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};
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struct nvm_id_lp_tbl {
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__u8 id[8];
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struct nvm_id_lp_mlc mlc;
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};
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struct nvm_addrf_12 {
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u8 ch_len;
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u8 lun_len;
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u8 blk_len;
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u8 pg_len;
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u8 pln_len;
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u8 sec_len;
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u8 ch_offset;
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u8 lun_offset;
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u8 blk_offset;
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u8 pg_offset;
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u8 pln_offset;
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u8 sec_offset;
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u64 ch_mask;
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u64 lun_mask;
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u64 blk_mask;
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u64 pg_mask;
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u64 pln_mask;
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u64 sec_mask;
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};
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struct nvm_addrf {
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u8 ch_len;
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u8 lun_len;
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u8 chk_len;
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u8 sec_len;
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u8 rsv_len[2];
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u8 ch_offset;
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u8 lun_offset;
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u8 chk_offset;
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u8 sec_offset;
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u8 rsv_off[2];
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u64 ch_mask;
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u64 lun_mask;
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u64 chk_mask;
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u64 sec_mask;
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u64 rsv_mask[2];
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};
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enum {
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/* Chunk states */
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NVM_CHK_ST_FREE = 1 << 0,
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NVM_CHK_ST_CLOSED = 1 << 1,
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NVM_CHK_ST_OPEN = 1 << 2,
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NVM_CHK_ST_OFFLINE = 1 << 3,
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/* Chunk types */
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NVM_CHK_TP_W_SEQ = 1 << 0,
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NVM_CHK_TP_W_RAN = 1 << 1,
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NVM_CHK_TP_SZ_SPEC = 1 << 4,
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};
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/*
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* Note: The structure size is linked to nvme_nvm_chk_meta such that the same
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* buffer can be used when converting from little endian to cpu addressing.
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*/
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struct nvm_chk_meta {
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u8 state;
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u8 type;
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u8 wi;
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u8 rsvd[5];
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u64 slba;
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u64 cnlb;
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u64 wp;
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};
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struct nvm_target {
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struct list_head list;
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struct nvm_tgt_dev *dev;
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struct nvm_tgt_type *type;
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struct gendisk *disk;
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};
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#define ADDR_EMPTY (~0ULL)
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#define NVM_TARGET_DEFAULT_OP (101)
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#define NVM_TARGET_MIN_OP (3)
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#define NVM_TARGET_MAX_OP (80)
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#define NVM_VERSION_MAJOR 1
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#define NVM_VERSION_MINOR 0
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#define NVM_VERSION_PATCH 0
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#define NVM_MAX_VLBA (64) /* max logical blocks in a vector command */
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struct nvm_rq;
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typedef void (nvm_end_io_fn)(struct nvm_rq *);
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struct nvm_rq {
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struct nvm_tgt_dev *dev;
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struct bio *bio;
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union {
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struct ppa_addr ppa_addr;
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dma_addr_t dma_ppa_list;
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};
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struct ppa_addr *ppa_list;
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void *meta_list;
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dma_addr_t dma_meta_list;
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nvm_end_io_fn *end_io;
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uint8_t opcode;
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uint16_t nr_ppas;
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uint16_t flags;
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u64 ppa_status; /* ppa media status */
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int error;
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int is_seq; /* Sequential hint flag. 1.2 only */
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void *private;
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};
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static inline struct nvm_rq *nvm_rq_from_pdu(void *pdu)
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{
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return pdu - sizeof(struct nvm_rq);
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}
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static inline void *nvm_rq_to_pdu(struct nvm_rq *rqdata)
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{
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return rqdata + 1;
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}
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static inline struct ppa_addr *nvm_rq_to_ppa_list(struct nvm_rq *rqd)
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{
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return (rqd->nr_ppas > 1) ? rqd->ppa_list : &rqd->ppa_addr;
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}
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enum {
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NVM_BLK_ST_FREE = 0x1, /* Free block */
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NVM_BLK_ST_TGT = 0x2, /* Block in use by target */
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NVM_BLK_ST_BAD = 0x8, /* Bad block */
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};
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/* Instance geometry */
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struct nvm_geo {
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/* device reported version */
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u8 major_ver_id;
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u8 minor_ver_id;
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/* kernel short version */
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u8 version;
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/* instance specific geometry */
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int num_ch;
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int num_lun; /* per channel */
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/* calculated values */
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int all_luns; /* across channels */
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int all_chunks; /* across channels */
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int op; /* over-provision in instance */
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sector_t total_secs; /* across channels */
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/* chunk geometry */
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u32 num_chk; /* chunks per lun */
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u32 clba; /* sectors per chunk */
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u16 csecs; /* sector size */
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u16 sos; /* out-of-band area size */
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/* device write constrains */
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u32 ws_min; /* minimum write size */
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u32 ws_opt; /* optimal write size */
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u32 mw_cunits; /* distance required for successful read */
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u32 maxoc; /* maximum open chunks */
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u32 maxocpu; /* maximum open chunks per parallel unit */
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/* device capabilities */
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u32 mccap;
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/* device timings */
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u32 trdt; /* Avg. Tread (ns) */
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u32 trdm; /* Max Tread (ns) */
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u32 tprt; /* Avg. Tprog (ns) */
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u32 tprm; /* Max Tprog (ns) */
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u32 tbet; /* Avg. Terase (ns) */
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u32 tbem; /* Max Terase (ns) */
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/* generic address format */
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struct nvm_addrf addrf;
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/* 1.2 compatibility */
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u8 vmnt;
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u32 cap;
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u32 dom;
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u8 mtype;
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u8 fmtype;
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u16 cpar;
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u32 mpos;
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u8 num_pln;
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u8 pln_mode;
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u16 num_pg;
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u16 fpg_sz;
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};
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/* sub-device structure */
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struct nvm_tgt_dev {
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/* Device information */
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struct nvm_geo geo;
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/* Base ppas for target LUNs */
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struct ppa_addr *luns;
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struct request_queue *q;
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struct nvm_dev *parent;
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void *map;
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};
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struct nvm_dev {
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struct nvm_dev_ops *ops;
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struct list_head devices;
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/* Device information */
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struct nvm_geo geo;
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unsigned long *lun_map;
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void *dma_pool;
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/* Backend device */
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struct request_queue *q;
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char name[DISK_NAME_LEN];
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void *private_data;
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void *rmap;
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struct mutex mlock;
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spinlock_t lock;
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/* target management */
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struct list_head area_list;
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struct list_head targets;
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};
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static inline struct ppa_addr generic_to_dev_addr(struct nvm_dev *dev,
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struct ppa_addr r)
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{
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struct nvm_geo *geo = &dev->geo;
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struct ppa_addr l;
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if (geo->version == NVM_OCSSD_SPEC_12) {
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struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
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l.ppa = ((u64)r.g.ch) << ppaf->ch_offset;
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l.ppa |= ((u64)r.g.lun) << ppaf->lun_offset;
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l.ppa |= ((u64)r.g.blk) << ppaf->blk_offset;
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l.ppa |= ((u64)r.g.pg) << ppaf->pg_offset;
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l.ppa |= ((u64)r.g.pl) << ppaf->pln_offset;
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l.ppa |= ((u64)r.g.sec) << ppaf->sec_offset;
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} else {
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struct nvm_addrf *lbaf = &geo->addrf;
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l.ppa = ((u64)r.m.grp) << lbaf->ch_offset;
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l.ppa |= ((u64)r.m.pu) << lbaf->lun_offset;
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l.ppa |= ((u64)r.m.chk) << lbaf->chk_offset;
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l.ppa |= ((u64)r.m.sec) << lbaf->sec_offset;
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}
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return l;
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}
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static inline struct ppa_addr dev_to_generic_addr(struct nvm_dev *dev,
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struct ppa_addr r)
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{
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struct nvm_geo *geo = &dev->geo;
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struct ppa_addr l;
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l.ppa = 0;
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if (geo->version == NVM_OCSSD_SPEC_12) {
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struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
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l.g.ch = (r.ppa & ppaf->ch_mask) >> ppaf->ch_offset;
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l.g.lun = (r.ppa & ppaf->lun_mask) >> ppaf->lun_offset;
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l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset;
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l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset;
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l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset;
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l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sec_offset;
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} else {
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struct nvm_addrf *lbaf = &geo->addrf;
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l.m.grp = (r.ppa & lbaf->ch_mask) >> lbaf->ch_offset;
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l.m.pu = (r.ppa & lbaf->lun_mask) >> lbaf->lun_offset;
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l.m.chk = (r.ppa & lbaf->chk_mask) >> lbaf->chk_offset;
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l.m.sec = (r.ppa & lbaf->sec_mask) >> lbaf->sec_offset;
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}
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return l;
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}
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static inline u64 dev_to_chunk_addr(struct nvm_dev *dev, void *addrf,
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struct ppa_addr p)
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{
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struct nvm_geo *geo = &dev->geo;
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u64 caddr;
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if (geo->version == NVM_OCSSD_SPEC_12) {
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struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)addrf;
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caddr = (u64)p.g.pg << ppaf->pg_offset;
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caddr |= (u64)p.g.pl << ppaf->pln_offset;
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caddr |= (u64)p.g.sec << ppaf->sec_offset;
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} else {
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caddr = p.m.sec;
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}
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return caddr;
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}
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static inline struct ppa_addr nvm_ppa32_to_ppa64(struct nvm_dev *dev,
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void *addrf, u32 ppa32)
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{
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struct ppa_addr ppa64;
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ppa64.ppa = 0;
|
|
|
|
if (ppa32 == -1) {
|
|
ppa64.ppa = ADDR_EMPTY;
|
|
} else if (ppa32 & (1U << 31)) {
|
|
ppa64.c.line = ppa32 & ((~0U) >> 1);
|
|
ppa64.c.is_cached = 1;
|
|
} else {
|
|
struct nvm_geo *geo = &dev->geo;
|
|
|
|
if (geo->version == NVM_OCSSD_SPEC_12) {
|
|
struct nvm_addrf_12 *ppaf = addrf;
|
|
|
|
ppa64.g.ch = (ppa32 & ppaf->ch_mask) >>
|
|
ppaf->ch_offset;
|
|
ppa64.g.lun = (ppa32 & ppaf->lun_mask) >>
|
|
ppaf->lun_offset;
|
|
ppa64.g.blk = (ppa32 & ppaf->blk_mask) >>
|
|
ppaf->blk_offset;
|
|
ppa64.g.pg = (ppa32 & ppaf->pg_mask) >>
|
|
ppaf->pg_offset;
|
|
ppa64.g.pl = (ppa32 & ppaf->pln_mask) >>
|
|
ppaf->pln_offset;
|
|
ppa64.g.sec = (ppa32 & ppaf->sec_mask) >>
|
|
ppaf->sec_offset;
|
|
} else {
|
|
struct nvm_addrf *lbaf = addrf;
|
|
|
|
ppa64.m.grp = (ppa32 & lbaf->ch_mask) >>
|
|
lbaf->ch_offset;
|
|
ppa64.m.pu = (ppa32 & lbaf->lun_mask) >>
|
|
lbaf->lun_offset;
|
|
ppa64.m.chk = (ppa32 & lbaf->chk_mask) >>
|
|
lbaf->chk_offset;
|
|
ppa64.m.sec = (ppa32 & lbaf->sec_mask) >>
|
|
lbaf->sec_offset;
|
|
}
|
|
}
|
|
|
|
return ppa64;
|
|
}
|
|
|
|
static inline u32 nvm_ppa64_to_ppa32(struct nvm_dev *dev,
|
|
void *addrf, struct ppa_addr ppa64)
|
|
{
|
|
u32 ppa32 = 0;
|
|
|
|
if (ppa64.ppa == ADDR_EMPTY) {
|
|
ppa32 = ~0U;
|
|
} else if (ppa64.c.is_cached) {
|
|
ppa32 |= ppa64.c.line;
|
|
ppa32 |= 1U << 31;
|
|
} else {
|
|
struct nvm_geo *geo = &dev->geo;
|
|
|
|
if (geo->version == NVM_OCSSD_SPEC_12) {
|
|
struct nvm_addrf_12 *ppaf = addrf;
|
|
|
|
ppa32 |= ppa64.g.ch << ppaf->ch_offset;
|
|
ppa32 |= ppa64.g.lun << ppaf->lun_offset;
|
|
ppa32 |= ppa64.g.blk << ppaf->blk_offset;
|
|
ppa32 |= ppa64.g.pg << ppaf->pg_offset;
|
|
ppa32 |= ppa64.g.pl << ppaf->pln_offset;
|
|
ppa32 |= ppa64.g.sec << ppaf->sec_offset;
|
|
} else {
|
|
struct nvm_addrf *lbaf = addrf;
|
|
|
|
ppa32 |= ppa64.m.grp << lbaf->ch_offset;
|
|
ppa32 |= ppa64.m.pu << lbaf->lun_offset;
|
|
ppa32 |= ppa64.m.chk << lbaf->chk_offset;
|
|
ppa32 |= ppa64.m.sec << lbaf->sec_offset;
|
|
}
|
|
}
|
|
|
|
return ppa32;
|
|
}
|
|
|
|
static inline int nvm_next_ppa_in_chk(struct nvm_tgt_dev *dev,
|
|
struct ppa_addr *ppa)
|
|
{
|
|
struct nvm_geo *geo = &dev->geo;
|
|
int last = 0;
|
|
|
|
if (geo->version == NVM_OCSSD_SPEC_12) {
|
|
int sec = ppa->g.sec;
|
|
|
|
sec++;
|
|
if (sec == geo->ws_min) {
|
|
int pg = ppa->g.pg;
|
|
|
|
sec = 0;
|
|
pg++;
|
|
if (pg == geo->num_pg) {
|
|
int pl = ppa->g.pl;
|
|
|
|
pg = 0;
|
|
pl++;
|
|
if (pl == geo->num_pln)
|
|
last = 1;
|
|
|
|
ppa->g.pl = pl;
|
|
}
|
|
ppa->g.pg = pg;
|
|
}
|
|
ppa->g.sec = sec;
|
|
} else {
|
|
ppa->m.sec++;
|
|
if (ppa->m.sec == geo->clba)
|
|
last = 1;
|
|
}
|
|
|
|
return last;
|
|
}
|
|
|
|
typedef blk_qc_t (nvm_tgt_make_rq_fn)(struct request_queue *, struct bio *);
|
|
typedef sector_t (nvm_tgt_capacity_fn)(void *);
|
|
typedef void *(nvm_tgt_init_fn)(struct nvm_tgt_dev *, struct gendisk *,
|
|
int flags);
|
|
typedef void (nvm_tgt_exit_fn)(void *, bool);
|
|
typedef int (nvm_tgt_sysfs_init_fn)(struct gendisk *);
|
|
typedef void (nvm_tgt_sysfs_exit_fn)(struct gendisk *);
|
|
|
|
enum {
|
|
NVM_TGT_F_DEV_L2P = 0,
|
|
NVM_TGT_F_HOST_L2P = 1 << 0,
|
|
};
|
|
|
|
struct nvm_tgt_type {
|
|
const char *name;
|
|
unsigned int version[3];
|
|
int flags;
|
|
|
|
/* target entry points */
|
|
nvm_tgt_make_rq_fn *make_rq;
|
|
nvm_tgt_capacity_fn *capacity;
|
|
|
|
/* module-specific init/teardown */
|
|
nvm_tgt_init_fn *init;
|
|
nvm_tgt_exit_fn *exit;
|
|
|
|
/* sysfs */
|
|
nvm_tgt_sysfs_init_fn *sysfs_init;
|
|
nvm_tgt_sysfs_exit_fn *sysfs_exit;
|
|
|
|
/* For internal use */
|
|
struct list_head list;
|
|
struct module *owner;
|
|
};
|
|
|
|
extern int nvm_register_tgt_type(struct nvm_tgt_type *);
|
|
extern void nvm_unregister_tgt_type(struct nvm_tgt_type *);
|
|
|
|
extern void *nvm_dev_dma_alloc(struct nvm_dev *, gfp_t, dma_addr_t *);
|
|
extern void nvm_dev_dma_free(struct nvm_dev *, void *, dma_addr_t);
|
|
|
|
extern struct nvm_dev *nvm_alloc_dev(int);
|
|
extern int nvm_register(struct nvm_dev *);
|
|
extern void nvm_unregister(struct nvm_dev *);
|
|
|
|
extern int nvm_get_chunk_meta(struct nvm_tgt_dev *, struct ppa_addr,
|
|
int, struct nvm_chk_meta *);
|
|
extern int nvm_set_chunk_meta(struct nvm_tgt_dev *, struct ppa_addr *,
|
|
int, int);
|
|
extern int nvm_submit_io(struct nvm_tgt_dev *, struct nvm_rq *);
|
|
extern int nvm_submit_io_sync(struct nvm_tgt_dev *, struct nvm_rq *);
|
|
extern void nvm_end_io(struct nvm_rq *);
|
|
|
|
#else /* CONFIG_NVM */
|
|
struct nvm_dev_ops;
|
|
|
|
static inline struct nvm_dev *nvm_alloc_dev(int node)
|
|
{
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
static inline int nvm_register(struct nvm_dev *dev)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
static inline void nvm_unregister(struct nvm_dev *dev) {}
|
|
#endif /* CONFIG_NVM */
|
|
#endif /* LIGHTNVM.H */
|