357 строки
8.4 KiB
C
357 строки
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* drivers/i2c/busses/i2c-mt7621.c
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*
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* Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
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* Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
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* Copyright (C) 2018 Jan Breuer <jan.breuer@jaybee.cz>
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*
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* Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
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* (C) 2014 Sittisak <sittisaks@hotmail.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/reset.h>
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#define REG_SM0CFG2_REG 0x28
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#define REG_SM0CTL0_REG 0x40
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#define REG_SM0CTL1_REG 0x44
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#define REG_SM0D0_REG 0x50
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#define REG_SM0D1_REG 0x54
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#define REG_PINTEN_REG 0x5c
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#define REG_PINTST_REG 0x60
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#define REG_PINTCL_REG 0x64
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/* REG_SM0CFG2_REG */
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#define SM0CFG2_IS_AUTOMODE BIT(0)
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/* REG_SM0CTL0_REG */
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#define SM0CTL0_ODRAIN BIT(31)
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#define SM0CTL0_CLK_DIV_MASK (0x7ff << 16)
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#define SM0CTL0_CLK_DIV_MAX 0x7ff
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#define SM0CTL0_CS_STATUS BIT(4)
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#define SM0CTL0_SCL_STATE BIT(3)
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#define SM0CTL0_SDA_STATE BIT(2)
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#define SM0CTL0_EN BIT(1)
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#define SM0CTL0_SCL_STRETCH BIT(0)
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/* REG_SM0CTL1_REG */
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#define SM0CTL1_ACK_MASK (0xff << 16)
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#define SM0CTL1_PGLEN_MASK (0x7 << 8)
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#define SM0CTL1_PGLEN(x) ((((x) - 1) << 8) & SM0CTL1_PGLEN_MASK)
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#define SM0CTL1_READ (5 << 4)
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#define SM0CTL1_READ_LAST (4 << 4)
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#define SM0CTL1_STOP (3 << 4)
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#define SM0CTL1_WRITE (2 << 4)
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#define SM0CTL1_START (1 << 4)
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#define SM0CTL1_MODE_MASK (0x7 << 4)
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#define SM0CTL1_TRI BIT(0)
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/* timeout waiting for I2C devices to respond */
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#define TIMEOUT_MS 1000
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struct mtk_i2c {
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void __iomem *base;
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struct device *dev;
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struct i2c_adapter adap;
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u32 bus_freq;
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u32 clk_div;
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u32 flags;
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struct clk *clk;
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};
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static int mtk_i2c_wait_idle(struct mtk_i2c *i2c)
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{
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int ret;
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u32 val;
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ret = readl_relaxed_poll_timeout(i2c->base + REG_SM0CTL1_REG,
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val, !(val & SM0CTL1_TRI),
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10, TIMEOUT_MS * 1000);
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if (ret)
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dev_dbg(i2c->dev, "idle err(%d)\n", ret);
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return ret;
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}
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static void mtk_i2c_reset(struct mtk_i2c *i2c)
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{
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int ret;
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ret = device_reset(i2c->adap.dev.parent);
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if (ret)
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dev_err(i2c->dev, "I2C reset failed!\n");
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/*
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* Don't set SM0CTL0_ODRAIN as its bit meaning is inverted. To
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* configure open-drain mode, this bit needs to be cleared.
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*/
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iowrite32(((i2c->clk_div << 16) & SM0CTL0_CLK_DIV_MASK) | SM0CTL0_EN |
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SM0CTL0_SCL_STRETCH, i2c->base + REG_SM0CTL0_REG);
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iowrite32(0, i2c->base + REG_SM0CFG2_REG);
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}
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static void mtk_i2c_dump_reg(struct mtk_i2c *i2c)
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{
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dev_dbg(i2c->dev,
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"SM0CFG2 %08x, SM0CTL0 %08x, SM0CTL1 %08x, SM0D0 %08x, SM0D1 %08x\n",
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ioread32(i2c->base + REG_SM0CFG2_REG),
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ioread32(i2c->base + REG_SM0CTL0_REG),
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ioread32(i2c->base + REG_SM0CTL1_REG),
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ioread32(i2c->base + REG_SM0D0_REG),
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ioread32(i2c->base + REG_SM0D1_REG));
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}
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static int mtk_i2c_check_ack(struct mtk_i2c *i2c, u32 expected)
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{
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u32 ack = readl_relaxed(i2c->base + REG_SM0CTL1_REG);
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u32 ack_expected = (expected << 16) & SM0CTL1_ACK_MASK;
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return ((ack & ack_expected) == ack_expected) ? 0 : -ENXIO;
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}
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static int mtk_i2c_master_start(struct mtk_i2c *i2c)
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{
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iowrite32(SM0CTL1_START | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG);
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return mtk_i2c_wait_idle(i2c);
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}
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static int mtk_i2c_master_stop(struct mtk_i2c *i2c)
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{
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iowrite32(SM0CTL1_STOP | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG);
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return mtk_i2c_wait_idle(i2c);
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}
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static int mtk_i2c_master_cmd(struct mtk_i2c *i2c, u32 cmd, int page_len)
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{
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iowrite32(cmd | SM0CTL1_TRI | SM0CTL1_PGLEN(page_len),
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i2c->base + REG_SM0CTL1_REG);
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return mtk_i2c_wait_idle(i2c);
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}
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static int mtk_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
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int num)
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{
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struct mtk_i2c *i2c;
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struct i2c_msg *pmsg;
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u16 addr;
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int i, j, ret, len, page_len;
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u32 cmd;
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u32 data[2];
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i2c = i2c_get_adapdata(adap);
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for (i = 0; i < num; i++) {
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pmsg = &msgs[i];
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/* wait hardware idle */
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ret = mtk_i2c_wait_idle(i2c);
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if (ret)
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goto err_timeout;
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/* start sequence */
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ret = mtk_i2c_master_start(i2c);
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if (ret)
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goto err_timeout;
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/* write address */
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if (pmsg->flags & I2C_M_TEN) {
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/* 10 bits address */
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addr = 0xf0 | ((pmsg->addr >> 7) & 0x06);
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addr |= (pmsg->addr & 0xff) << 8;
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if (pmsg->flags & I2C_M_RD)
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addr |= 1;
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iowrite32(addr, i2c->base + REG_SM0D0_REG);
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ret = mtk_i2c_master_cmd(i2c, SM0CTL1_WRITE, 2);
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if (ret)
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goto err_timeout;
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} else {
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/* 7 bits address */
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addr = i2c_8bit_addr_from_msg(pmsg);
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iowrite32(addr, i2c->base + REG_SM0D0_REG);
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ret = mtk_i2c_master_cmd(i2c, SM0CTL1_WRITE, 1);
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if (ret)
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goto err_timeout;
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}
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/* check address ACK */
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if (!(pmsg->flags & I2C_M_IGNORE_NAK)) {
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ret = mtk_i2c_check_ack(i2c, BIT(0));
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if (ret)
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goto err_ack;
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}
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/* transfer data */
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for (len = pmsg->len, j = 0; len > 0; len -= 8, j += 8) {
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page_len = (len >= 8) ? 8 : len;
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if (pmsg->flags & I2C_M_RD) {
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cmd = (len > 8) ?
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SM0CTL1_READ : SM0CTL1_READ_LAST;
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} else {
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memcpy(data, &pmsg->buf[j], page_len);
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iowrite32(data[0], i2c->base + REG_SM0D0_REG);
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iowrite32(data[1], i2c->base + REG_SM0D1_REG);
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cmd = SM0CTL1_WRITE;
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}
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ret = mtk_i2c_master_cmd(i2c, cmd, page_len);
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if (ret)
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goto err_timeout;
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if (pmsg->flags & I2C_M_RD) {
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data[0] = ioread32(i2c->base + REG_SM0D0_REG);
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data[1] = ioread32(i2c->base + REG_SM0D1_REG);
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memcpy(&pmsg->buf[j], data, page_len);
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} else {
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if (!(pmsg->flags & I2C_M_IGNORE_NAK)) {
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ret = mtk_i2c_check_ack(i2c,
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(1 << page_len)
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- 1);
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if (ret)
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goto err_ack;
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}
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}
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}
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}
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ret = mtk_i2c_master_stop(i2c);
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if (ret)
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goto err_timeout;
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/* the return value is number of executed messages */
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return i;
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err_ack:
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ret = mtk_i2c_master_stop(i2c);
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if (ret)
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goto err_timeout;
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return -ENXIO;
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err_timeout:
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mtk_i2c_dump_reg(i2c);
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mtk_i2c_reset(i2c);
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return ret;
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}
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static u32 mtk_i2c_func(struct i2c_adapter *a)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
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}
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static const struct i2c_algorithm mtk_i2c_algo = {
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.master_xfer = mtk_i2c_master_xfer,
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.functionality = mtk_i2c_func,
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};
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static const struct of_device_id i2c_mtk_dt_ids[] = {
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{ .compatible = "mediatek,mt7621-i2c" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, i2c_mtk_dt_ids);
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static void mtk_i2c_init(struct mtk_i2c *i2c)
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{
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i2c->clk_div = clk_get_rate(i2c->clk) / i2c->bus_freq - 1;
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if (i2c->clk_div < 99)
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i2c->clk_div = 99;
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if (i2c->clk_div > SM0CTL0_CLK_DIV_MAX)
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i2c->clk_div = SM0CTL0_CLK_DIV_MAX;
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mtk_i2c_reset(i2c);
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}
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static int mtk_i2c_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct mtk_i2c *i2c;
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struct i2c_adapter *adap;
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int ret;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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i2c = devm_kzalloc(&pdev->dev, sizeof(struct mtk_i2c), GFP_KERNEL);
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if (!i2c)
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return -ENOMEM;
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i2c->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(i2c->base))
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return PTR_ERR(i2c->base);
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i2c->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(i2c->clk)) {
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dev_err(&pdev->dev, "no clock defined\n");
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return PTR_ERR(i2c->clk);
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}
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ret = clk_prepare_enable(i2c->clk);
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if (ret) {
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dev_err(&pdev->dev, "Unable to enable clock\n");
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return ret;
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}
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i2c->dev = &pdev->dev;
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if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
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&i2c->bus_freq))
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i2c->bus_freq = 100000;
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if (i2c->bus_freq == 0) {
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dev_warn(i2c->dev, "clock-frequency 0 not supported\n");
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return -EINVAL;
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}
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adap = &i2c->adap;
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adap->owner = THIS_MODULE;
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adap->algo = &mtk_i2c_algo;
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adap->retries = 3;
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adap->dev.parent = &pdev->dev;
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i2c_set_adapdata(adap, i2c);
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adap->dev.of_node = pdev->dev.of_node;
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strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
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platform_set_drvdata(pdev, i2c);
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mtk_i2c_init(i2c);
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ret = i2c_add_adapter(adap);
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if (ret < 0)
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return ret;
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dev_info(&pdev->dev, "clock %u kHz\n", i2c->bus_freq / 1000);
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return ret;
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}
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static int mtk_i2c_remove(struct platform_device *pdev)
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{
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struct mtk_i2c *i2c = platform_get_drvdata(pdev);
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clk_disable_unprepare(i2c->clk);
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i2c_del_adapter(&i2c->adap);
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return 0;
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}
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static struct platform_driver mtk_i2c_driver = {
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.probe = mtk_i2c_probe,
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.remove = mtk_i2c_remove,
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.driver = {
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.name = "i2c-mt7621",
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.of_match_table = i2c_mtk_dt_ids,
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},
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};
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module_platform_driver(mtk_i2c_driver);
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MODULE_AUTHOR("Steven Liu");
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MODULE_DESCRIPTION("MT7621 I2C host driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:MT7621-I2C");
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