149 строки
3.7 KiB
C
149 строки
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Clock based PWM controller
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*
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* Copyright (c) 2021 Nikita Travkin <nikita@trvn.ru>
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*
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* This is an "adapter" driver that allows PWM consumers to use
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* system clocks with duty cycle control as PWM outputs.
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*
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* Limitations:
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* - Due to the fact that exact behavior depends on the underlying
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* clock driver, various limitations are possible.
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* - Underlying clock may not be able to give 0% or 100% duty cycle
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* (constant off or on), exact behavior will depend on the clock.
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* - When the PWM is disabled, the clock will be disabled as well,
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* line state will depend on the clock.
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* - The clk API doesn't expose the necessary calls to implement
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* .get_state().
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*/
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#include <linux/kernel.h>
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#include <linux/math64.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/pwm.h>
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struct pwm_clk_chip {
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struct pwm_chip chip;
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struct clk *clk;
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bool clk_enabled;
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};
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#define to_pwm_clk_chip(_chip) container_of(_chip, struct pwm_clk_chip, chip)
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static int pwm_clk_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct pwm_clk_chip *pcchip = to_pwm_clk_chip(chip);
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int ret;
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u32 rate;
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u64 period = state->period;
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u64 duty_cycle = state->duty_cycle;
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if (!state->enabled) {
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if (pwm->state.enabled) {
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clk_disable(pcchip->clk);
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pcchip->clk_enabled = false;
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}
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return 0;
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} else if (!pwm->state.enabled) {
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ret = clk_enable(pcchip->clk);
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if (ret)
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return ret;
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pcchip->clk_enabled = true;
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}
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/*
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* We have to enable the clk before setting the rate and duty_cycle,
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* that however results in a window where the clk is on with a
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* (potentially) different setting. Also setting period and duty_cycle
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* are two separate calls, so that probably isn't atomic either.
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*/
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rate = DIV64_U64_ROUND_UP(NSEC_PER_SEC, period);
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ret = clk_set_rate(pcchip->clk, rate);
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if (ret)
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return ret;
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if (state->polarity == PWM_POLARITY_INVERSED)
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duty_cycle = period - duty_cycle;
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return clk_set_duty_cycle(pcchip->clk, duty_cycle, period);
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}
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static const struct pwm_ops pwm_clk_ops = {
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.apply = pwm_clk_apply,
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.owner = THIS_MODULE,
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};
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static int pwm_clk_probe(struct platform_device *pdev)
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{
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struct pwm_clk_chip *pcchip;
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int ret;
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pcchip = devm_kzalloc(&pdev->dev, sizeof(*pcchip), GFP_KERNEL);
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if (!pcchip)
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return -ENOMEM;
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pcchip->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(pcchip->clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(pcchip->clk),
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"Failed to get clock\n");
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pcchip->chip.dev = &pdev->dev;
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pcchip->chip.ops = &pwm_clk_ops;
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pcchip->chip.npwm = 1;
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ret = clk_prepare(pcchip->clk);
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if (ret < 0)
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return dev_err_probe(&pdev->dev, ret, "Failed to prepare clock\n");
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ret = pwmchip_add(&pcchip->chip);
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if (ret < 0) {
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clk_unprepare(pcchip->clk);
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return dev_err_probe(&pdev->dev, ret, "Failed to add pwm chip\n");
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}
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platform_set_drvdata(pdev, pcchip);
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return 0;
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}
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static int pwm_clk_remove(struct platform_device *pdev)
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{
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struct pwm_clk_chip *pcchip = platform_get_drvdata(pdev);
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pwmchip_remove(&pcchip->chip);
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if (pcchip->clk_enabled)
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clk_disable(pcchip->clk);
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clk_unprepare(pcchip->clk);
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return 0;
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}
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static const struct of_device_id pwm_clk_dt_ids[] = {
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{ .compatible = "clk-pwm", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, pwm_clk_dt_ids);
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static struct platform_driver pwm_clk_driver = {
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.driver = {
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.name = "pwm-clk",
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.of_match_table = pwm_clk_dt_ids,
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},
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.probe = pwm_clk_probe,
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.remove = pwm_clk_remove,
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};
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module_platform_driver(pwm_clk_driver);
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MODULE_ALIAS("platform:pwm-clk");
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MODULE_AUTHOR("Nikita Travkin <nikita@trvn.ru>");
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MODULE_DESCRIPTION("Clock based PWM driver");
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MODULE_LICENSE("GPL");
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