320 строки
7.4 KiB
C
320 строки
7.4 KiB
C
/*
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* arch/arm/mach-mv78xx0/pcie.c
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*
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* PCIe functions for Marvell MV78xx0 SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/mbus.h>
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#include <asm/irq.h>
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#include <asm/mach/pci.h>
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#include <plat/pcie.h>
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#include "common.h"
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struct pcie_port {
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u8 maj;
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u8 min;
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u8 root_bus_nr;
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void __iomem *base;
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spinlock_t conf_lock;
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char io_space_name[16];
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char mem_space_name[16];
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struct resource res[2];
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};
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static struct pcie_port pcie_port[8];
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static int num_pcie_ports;
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static struct resource pcie_io_space;
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static struct resource pcie_mem_space;
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void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
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{
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*dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE);
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*rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
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}
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static void __init mv78xx0_pcie_preinit(void)
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{
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int i;
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u32 size_each;
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u32 start;
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int win;
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pcie_io_space.name = "PCIe I/O Space";
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pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
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pcie_io_space.end =
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MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
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pcie_io_space.flags = IORESOURCE_IO;
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if (request_resource(&iomem_resource, &pcie_io_space))
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panic("can't allocate PCIe I/O space");
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pcie_mem_space.name = "PCIe MEM Space";
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pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE;
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pcie_mem_space.end =
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MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1;
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pcie_mem_space.flags = IORESOURCE_MEM;
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if (request_resource(&iomem_resource, &pcie_mem_space))
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panic("can't allocate PCIe MEM space");
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for (i = 0; i < num_pcie_ports; i++) {
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struct pcie_port *pp = pcie_port + i;
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snprintf(pp->io_space_name, sizeof(pp->io_space_name),
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"PCIe %d.%d I/O", pp->maj, pp->min);
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pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
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pp->res[0].name = pp->io_space_name;
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pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
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pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
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pp->res[0].flags = IORESOURCE_IO;
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snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
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"PCIe %d.%d MEM", pp->maj, pp->min);
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pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
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pp->res[1].name = pp->mem_space_name;
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pp->res[1].flags = IORESOURCE_MEM;
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}
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switch (num_pcie_ports) {
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case 0:
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size_each = 0;
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break;
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case 1:
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size_each = 0x30000000;
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break;
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case 2 ... 3:
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size_each = 0x10000000;
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break;
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case 4 ... 6:
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size_each = 0x08000000;
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break;
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case 7:
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size_each = 0x04000000;
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break;
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default:
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panic("invalid number of PCIe ports");
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}
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start = MV78XX0_PCIE_MEM_PHYS_BASE;
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for (i = 0; i < num_pcie_ports; i++) {
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struct pcie_port *pp = pcie_port + i;
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pp->res[1].start = start;
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pp->res[1].end = start + size_each - 1;
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start += size_each;
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}
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for (i = 0; i < num_pcie_ports; i++) {
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struct pcie_port *pp = pcie_port + i;
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if (request_resource(&pcie_io_space, &pp->res[0]))
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panic("can't allocate PCIe I/O sub-space");
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if (request_resource(&pcie_mem_space, &pp->res[1]))
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panic("can't allocate PCIe MEM sub-space");
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}
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win = 0;
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for (i = 0; i < num_pcie_ports; i++) {
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struct pcie_port *pp = pcie_port + i;
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mv78xx0_setup_pcie_io_win(win++, pp->res[0].start,
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pp->res[0].end - pp->res[0].start + 1,
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pp->maj, pp->min);
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mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
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pp->res[1].end - pp->res[1].start + 1,
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pp->maj, pp->min);
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}
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}
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static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
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{
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struct pcie_port *pp;
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if (nr >= num_pcie_ports)
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return 0;
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pp = &pcie_port[nr];
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pp->root_bus_nr = sys->busnr;
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/*
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* Generic PCIe unit setup.
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*/
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orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
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orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info);
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sys->resource[0] = &pp->res[0];
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sys->resource[1] = &pp->res[1];
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sys->resource[2] = NULL;
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return 1;
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}
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static struct pcie_port *bus_to_port(int bus)
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{
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int i;
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for (i = num_pcie_ports - 1; i >= 0; i--) {
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int rbus = pcie_port[i].root_bus_nr;
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if (rbus != -1 && rbus <= bus)
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break;
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}
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return i >= 0 ? pcie_port + i : NULL;
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}
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static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
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{
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/*
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* Don't go out when trying to access nonexisting devices
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* on the local bus.
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*/
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if (bus == pp->root_bus_nr && dev > 1)
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return 0;
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return 1;
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}
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static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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int size, u32 *val)
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{
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struct pcie_port *pp = bus_to_port(bus->number);
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unsigned long flags;
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int ret;
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if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
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*val = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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spin_lock_irqsave(&pp->conf_lock, flags);
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ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
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spin_unlock_irqrestore(&pp->conf_lock, flags);
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return ret;
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}
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static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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{
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struct pcie_port *pp = bus_to_port(bus->number);
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unsigned long flags;
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int ret;
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if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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spin_lock_irqsave(&pp->conf_lock, flags);
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ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
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spin_unlock_irqrestore(&pp->conf_lock, flags);
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return ret;
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}
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static struct pci_ops pcie_ops = {
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.read = pcie_rd_conf,
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.write = pcie_wr_conf,
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};
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static void __devinit rc_pci_fixup(struct pci_dev *dev)
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{
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/*
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* Prevent enumeration of root complex.
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*/
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if (dev->bus->parent == NULL && dev->devfn == 0) {
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int i;
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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dev->resource[i].start = 0;
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dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
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static struct pci_bus __init *
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mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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{
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struct pci_bus *bus;
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if (nr < num_pcie_ports) {
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bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
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} else {
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bus = NULL;
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BUG();
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}
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return bus;
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}
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static int __init mv78xx0_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct pcie_port *pp = bus_to_port(dev->bus->number);
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return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
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}
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static struct hw_pci mv78xx0_pci __initdata = {
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.nr_controllers = 8,
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.preinit = mv78xx0_pcie_preinit,
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.swizzle = pci_std_swizzle,
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.setup = mv78xx0_pcie_setup,
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.scan = mv78xx0_pcie_scan_bus,
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.map_irq = mv78xx0_pcie_map_irq,
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};
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static void __init add_pcie_port(int maj, int min, unsigned long base)
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{
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printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
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if (orion_pcie_link_up((void __iomem *)base)) {
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struct pcie_port *pp = &pcie_port[num_pcie_ports++];
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printk("link up\n");
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pp->maj = maj;
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pp->min = min;
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pp->root_bus_nr = -1;
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pp->base = (void __iomem *)base;
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spin_lock_init(&pp->conf_lock);
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memset(pp->res, 0, sizeof(pp->res));
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} else {
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printk("link down, ignoring\n");
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}
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}
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void __init mv78xx0_pcie_init(int init_port0, int init_port1)
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{
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if (init_port0) {
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add_pcie_port(0, 0, PCIE00_VIRT_BASE);
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if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
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add_pcie_port(0, 1, PCIE01_VIRT_BASE);
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add_pcie_port(0, 2, PCIE02_VIRT_BASE);
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add_pcie_port(0, 3, PCIE03_VIRT_BASE);
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}
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}
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if (init_port1) {
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add_pcie_port(1, 0, PCIE10_VIRT_BASE);
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if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) {
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add_pcie_port(1, 1, PCIE11_VIRT_BASE);
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add_pcie_port(1, 2, PCIE12_VIRT_BASE);
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add_pcie_port(1, 3, PCIE13_VIRT_BASE);
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}
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}
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pci_common_init(&mv78xx0_pci);
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}
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