353 строки
10 KiB
C
353 строки
10 KiB
C
/*
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* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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#ifndef IOATDMA_H
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#define IOATDMA_H
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#include <linux/dmaengine.h>
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#include "hw.h"
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#include "registers.h"
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#include <linux/init.h>
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#include <linux/dmapool.h>
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#include <linux/cache.h>
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#include <linux/pci_ids.h>
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#include <net/tcp.h>
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#define IOAT_DMA_VERSION "4.00"
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#define IOAT_LOW_COMPLETION_MASK 0xffffffc0
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#define IOAT_DMA_DCA_ANY_CPU ~0
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#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
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#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
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#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
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#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
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#define to_pdev(ioat_chan) ((ioat_chan)->device->pdev)
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#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
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/*
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* workaround for IOAT ver.3.0 null descriptor issue
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* (channel returns error when size is 0)
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*/
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#define NULL_DESC_BUFFER_SIZE 1
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enum ioat_irq_mode {
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IOAT_NOIRQ = 0,
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IOAT_MSIX,
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IOAT_MSI,
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IOAT_INTX
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};
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/**
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* struct ioatdma_device - internal representation of a IOAT device
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* @pdev: PCI-Express device
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* @reg_base: MMIO register space base address
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* @dma_pool: for allocating DMA descriptors
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* @common: embedded struct dma_device
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* @version: version of ioatdma device
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* @msix_entries: irq handlers
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* @idx: per channel data
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* @dca: direct cache access context
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* @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
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* @enumerate_channels: hw version specific channel enumeration
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* @reset_hw: hw version specific channel (re)initialization
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* @cleanup_fn: select between the v2 and v3 cleanup routines
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* @timer_fn: select between the v2 and v3 timer watchdog routines
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* @self_test: hardware version specific self test for each supported op type
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*
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* Note: the v3 cleanup routine supports raid operations
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*/
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struct ioatdma_device {
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struct pci_dev *pdev;
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void __iomem *reg_base;
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struct pci_pool *dma_pool;
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struct pci_pool *completion_pool;
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#define MAX_SED_POOLS 5
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struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
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struct dma_device common;
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u8 version;
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struct msix_entry msix_entries[4];
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struct ioat_chan_common *idx[4];
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struct dca_provider *dca;
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enum ioat_irq_mode irq_mode;
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u32 cap;
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void (*intr_quirk)(struct ioatdma_device *device);
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int (*enumerate_channels)(struct ioatdma_device *device);
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int (*reset_hw)(struct ioat_chan_common *chan);
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void (*cleanup_fn)(unsigned long data);
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void (*timer_fn)(unsigned long data);
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int (*self_test)(struct ioatdma_device *device);
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};
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struct ioat_chan_common {
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struct dma_chan common;
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void __iomem *reg_base;
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dma_addr_t last_completion;
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spinlock_t cleanup_lock;
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unsigned long state;
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#define IOAT_COMPLETION_PENDING 0
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#define IOAT_COMPLETION_ACK 1
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#define IOAT_RESET_PENDING 2
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#define IOAT_KOBJ_INIT_FAIL 3
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#define IOAT_RESHAPE_PENDING 4
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#define IOAT_RUN 5
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#define IOAT_CHAN_ACTIVE 6
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struct timer_list timer;
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#define COMPLETION_TIMEOUT msecs_to_jiffies(100)
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#define IDLE_TIMEOUT msecs_to_jiffies(2000)
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#define RESET_DELAY msecs_to_jiffies(100)
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struct ioatdma_device *device;
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dma_addr_t completion_dma;
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u64 *completion;
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struct tasklet_struct cleanup_task;
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struct kobject kobj;
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};
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struct ioat_sysfs_entry {
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struct attribute attr;
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ssize_t (*show)(struct dma_chan *, char *);
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};
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/**
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* struct ioat_dma_chan - internal representation of a DMA channel
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*/
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struct ioat_dma_chan {
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struct ioat_chan_common base;
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size_t xfercap; /* XFERCAP register value expanded out */
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spinlock_t desc_lock;
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struct list_head free_desc;
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struct list_head used_desc;
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int pending;
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u16 desccount;
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u16 active;
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};
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/**
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* struct ioat_sed_ent - wrapper around super extended hardware descriptor
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* @hw: hardware SED
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* @sed_dma: dma address for the SED
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* @list: list member
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* @parent: point to the dma descriptor that's the parent
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*/
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struct ioat_sed_ent {
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struct ioat_sed_raw_descriptor *hw;
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dma_addr_t dma;
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struct ioat_ring_ent *parent;
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unsigned int hw_pool;
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};
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static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
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{
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return container_of(c, struct ioat_chan_common, common);
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}
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static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
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{
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struct ioat_chan_common *chan = to_chan_common(c);
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return container_of(chan, struct ioat_dma_chan, base);
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}
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/* wrapper around hardware descriptor format + additional software fields */
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/**
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* struct ioat_desc_sw - wrapper around hardware descriptor
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* @hw: hardware DMA descriptor (for memcpy)
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* @node: this descriptor will either be on the free list,
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* or attached to a transaction list (tx_list)
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* @txd: the generic software descriptor for all engines
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* @id: identifier for debug
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*/
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struct ioat_desc_sw {
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struct ioat_dma_descriptor *hw;
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struct list_head node;
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size_t len;
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struct list_head tx_list;
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struct dma_async_tx_descriptor txd;
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#ifdef DEBUG
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int id;
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#endif
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};
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#ifdef DEBUG
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#define set_desc_id(desc, i) ((desc)->id = (i))
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#define desc_id(desc) ((desc)->id)
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#else
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#define set_desc_id(desc, i)
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#define desc_id(desc) (0)
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#endif
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static inline void
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__dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw,
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struct dma_async_tx_descriptor *tx, int id)
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{
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struct device *dev = to_dev(chan);
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dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
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" ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
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(unsigned long long) tx->phys,
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(unsigned long long) hw->next, tx->cookie, tx->flags,
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hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
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}
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#define dump_desc_dbg(c, d) \
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({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })
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static inline struct ioat_chan_common *
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ioat_chan_by_index(struct ioatdma_device *device, int index)
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{
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return device->idx[index];
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}
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static inline u64 ioat_chansts_32(struct ioat_chan_common *chan)
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{
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u8 ver = chan->device->version;
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u64 status;
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u32 status_lo;
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/* We need to read the low address first as this causes the
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* chipset to latch the upper bits for the subsequent read
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*/
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status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
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status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
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status <<= 32;
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status |= status_lo;
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return status;
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}
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#if BITS_PER_LONG == 64
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static inline u64 ioat_chansts(struct ioat_chan_common *chan)
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{
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u8 ver = chan->device->version;
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u64 status;
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/* With IOAT v3.3 the status register is 64bit. */
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if (ver >= IOAT_VER_3_3)
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status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver));
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else
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status = ioat_chansts_32(chan);
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return status;
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}
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#else
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#define ioat_chansts ioat_chansts_32
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#endif
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static inline void ioat_start(struct ioat_chan_common *chan)
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{
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u8 ver = chan->device->version;
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writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
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}
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static inline u64 ioat_chansts_to_addr(u64 status)
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{
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return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
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}
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static inline u32 ioat_chanerr(struct ioat_chan_common *chan)
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{
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return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
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}
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static inline void ioat_suspend(struct ioat_chan_common *chan)
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{
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u8 ver = chan->device->version;
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writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
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}
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static inline void ioat_reset(struct ioat_chan_common *chan)
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{
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u8 ver = chan->device->version;
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writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
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}
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static inline bool ioat_reset_pending(struct ioat_chan_common *chan)
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{
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u8 ver = chan->device->version;
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u8 cmd;
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cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
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return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
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}
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static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr)
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{
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struct ioat_chan_common *chan = &ioat->base;
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writel(addr & 0x00000000FFFFFFFF,
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chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
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writel(addr >> 32,
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chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
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}
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static inline bool is_ioat_active(unsigned long status)
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{
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return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
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}
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static inline bool is_ioat_idle(unsigned long status)
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{
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return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
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}
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static inline bool is_ioat_halted(unsigned long status)
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{
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return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
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}
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static inline bool is_ioat_suspended(unsigned long status)
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{
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return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
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}
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/* channel was fatally programmed */
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static inline bool is_ioat_bug(unsigned long err)
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{
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return !!err;
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}
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int ioat_probe(struct ioatdma_device *device);
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int ioat_register(struct ioatdma_device *device);
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int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
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int ioat_dma_self_test(struct ioatdma_device *device);
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void ioat_dma_remove(struct ioatdma_device *device);
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struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
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dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan);
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void ioat_init_channel(struct ioatdma_device *device,
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struct ioat_chan_common *chan, int idx);
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enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
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struct dma_tx_state *txstate);
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bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
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dma_addr_t *phys_complete);
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void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type);
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void ioat_kobject_del(struct ioatdma_device *device);
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int ioat_dma_setup_interrupts(struct ioatdma_device *device);
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void ioat_stop(struct ioat_chan_common *chan);
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extern const struct sysfs_ops ioat_sysfs_ops;
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extern struct ioat_sysfs_entry ioat_version_attr;
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extern struct ioat_sysfs_entry ioat_cap_attr;
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#endif /* IOATDMA_H */
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