600 строки
15 KiB
C
600 строки
15 KiB
C
/*
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* intel_idle.c - native hardware idle loop for modern Intel processors
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*
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* Copyright (c) 2010, Intel Corporation.
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* Len Brown <len.brown@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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/*
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* intel_idle is a cpuidle driver that loads on specific Intel processors
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* in lieu of the legacy ACPI processor_idle driver. The intent is to
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* make Linux more efficient on these processors, as intel_idle knows
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* more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
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*/
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/*
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* Design Assumptions
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*
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* All CPUs have same idle states as boot CPU
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*
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* Chipset BM_STS (bus master status) bit is a NOP
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* for preventing entry into deep C-stats
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*/
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/*
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* Known limitations
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*
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* The driver currently initializes for_each_online_cpu() upon modprobe.
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* It it unaware of subsequent processors hot-added to the system.
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* This means that if you boot with maxcpus=n and later online
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* processors above n, those processors will use C1 only.
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*
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* ACPI has a .suspend hack to turn off deep c-statees during suspend
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* to avoid complications with the lapic timer workaround.
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* Have not seen issues with suspend, but may need same workaround here.
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*
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* There is currently no kernel-based automatic probing/loading mechanism
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* if the driver is built as a module.
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*/
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/* un-comment DEBUG to enable pr_debug() statements */
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#define DEBUG
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#include <linux/kernel.h>
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#include <linux/cpuidle.h>
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#include <linux/clockchips.h>
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#include <linux/hrtimer.h> /* ktime_get_real() */
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#include <trace/events/power.h>
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#include <linux/sched.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/module.h>
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#include <asm/cpu_device_id.h>
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#include <asm/mwait.h>
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#include <asm/msr.h>
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#define INTEL_IDLE_VERSION "0.4"
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#define PREFIX "intel_idle: "
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static struct cpuidle_driver intel_idle_driver = {
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.name = "intel_idle",
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.owner = THIS_MODULE,
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};
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/* intel_idle.max_cstate=0 disables driver */
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static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
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static unsigned int mwait_substates;
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#define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
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/* Reliable LAPIC Timer States, bit 1 for C1 etc. */
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static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
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struct idle_cpu {
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struct cpuidle_state *state_table;
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/*
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* Hardware C-state auto-demotion may not always be optimal.
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* Indicate which enable bits to clear here.
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*/
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unsigned long auto_demotion_disable_flags;
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};
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static const struct idle_cpu *icpu;
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static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
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static int intel_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index);
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static struct cpuidle_state *cpuidle_state_table;
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/*
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* Set this flag for states where the HW flushes the TLB for us
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* and so we don't need cross-calls to keep it consistent.
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* If this flag is set, SW flushes the TLB, so even if the
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* HW doesn't do the flushing, this flag is safe to use.
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*/
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#define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
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/*
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* States are indexed by the cstate number,
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* which is also the index into the MWAIT hint array.
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* Thus C0 is a dummy.
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*/
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static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
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{ /* MWAIT C0 */ },
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{ /* MWAIT C1 */
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.name = "C1-NHM",
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.desc = "MWAIT 0x00",
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 3,
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.target_residency = 6,
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.enter = &intel_idle },
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{ /* MWAIT C2 */
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.name = "C3-NHM",
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.desc = "MWAIT 0x10",
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 20,
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.target_residency = 80,
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.enter = &intel_idle },
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{ /* MWAIT C3 */
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.name = "C6-NHM",
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.desc = "MWAIT 0x20",
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 200,
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.target_residency = 800,
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.enter = &intel_idle },
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};
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static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
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{ /* MWAIT C0 */ },
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{ /* MWAIT C1 */
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.name = "C1-SNB",
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.desc = "MWAIT 0x00",
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle },
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{ /* MWAIT C2 */
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.name = "C3-SNB",
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.desc = "MWAIT 0x10",
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 80,
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.target_residency = 211,
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.enter = &intel_idle },
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{ /* MWAIT C3 */
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.name = "C6-SNB",
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.desc = "MWAIT 0x20",
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 104,
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.target_residency = 345,
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.enter = &intel_idle },
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{ /* MWAIT C4 */
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.name = "C7-SNB",
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.desc = "MWAIT 0x30",
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 109,
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.target_residency = 345,
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.enter = &intel_idle },
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};
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static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
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{ /* MWAIT C0 */ },
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{ /* MWAIT C1 */
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.name = "C1-ATM",
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.desc = "MWAIT 0x00",
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 1,
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.target_residency = 4,
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.enter = &intel_idle },
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{ /* MWAIT C2 */
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.name = "C2-ATM",
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.desc = "MWAIT 0x10",
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 20,
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.target_residency = 80,
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.enter = &intel_idle },
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{ /* MWAIT C3 */ },
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{ /* MWAIT C4 */
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.name = "C4-ATM",
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.desc = "MWAIT 0x30",
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 100,
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.target_residency = 400,
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.enter = &intel_idle },
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{ /* MWAIT C5 */ },
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{ /* MWAIT C6 */
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.name = "C6-ATM",
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.desc = "MWAIT 0x52",
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 140,
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.target_residency = 560,
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.enter = &intel_idle },
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};
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static long get_driver_data(int cstate)
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{
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int driver_data;
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switch (cstate) {
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case 1: /* MWAIT C1 */
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driver_data = 0x00;
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break;
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case 2: /* MWAIT C2 */
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driver_data = 0x10;
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break;
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case 3: /* MWAIT C3 */
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driver_data = 0x20;
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break;
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case 4: /* MWAIT C4 */
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driver_data = 0x30;
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break;
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case 5: /* MWAIT C5 */
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driver_data = 0x40;
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break;
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case 6: /* MWAIT C6 */
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driver_data = 0x52;
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break;
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default:
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driver_data = 0x00;
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}
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return driver_data;
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}
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/**
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* intel_idle
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* @dev: cpuidle_device
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* @drv: cpuidle driver
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* @index: index of cpuidle state
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*
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* Must be called under local_irq_disable().
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*/
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static int intel_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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unsigned long ecx = 1; /* break on interrupt flag */
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struct cpuidle_state *state = &drv->states[index];
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struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
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unsigned long eax = (unsigned long)cpuidle_get_statedata(state_usage);
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unsigned int cstate;
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ktime_t kt_before, kt_after;
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s64 usec_delta;
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int cpu = smp_processor_id();
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cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
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/*
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* leave_mm() to avoid costly and often unnecessary wakeups
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* for flushing the user TLB's associated with the active mm.
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*/
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if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
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leave_mm(cpu);
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if (!(lapic_timer_reliable_states & (1 << (cstate))))
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
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kt_before = ktime_get_real();
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stop_critical_timings();
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if (!need_resched()) {
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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smp_mb();
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if (!need_resched())
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__mwait(eax, ecx);
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}
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start_critical_timings();
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kt_after = ktime_get_real();
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usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
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local_irq_enable();
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if (!(lapic_timer_reliable_states & (1 << (cstate))))
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
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/* Update cpuidle counters */
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dev->last_residency = (int)usec_delta;
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return index;
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}
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static void __setup_broadcast_timer(void *arg)
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{
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unsigned long reason = (unsigned long)arg;
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int cpu = smp_processor_id();
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reason = reason ?
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CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
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clockevents_notify(reason, &cpu);
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}
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static int setup_broadcast_cpuhp_notify(struct notifier_block *n,
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unsigned long action, void *hcpu)
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{
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int hotcpu = (unsigned long)hcpu;
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switch (action & 0xf) {
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case CPU_ONLINE:
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smp_call_function_single(hotcpu, __setup_broadcast_timer,
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(void *)true, 1);
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block setup_broadcast_notifier = {
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.notifier_call = setup_broadcast_cpuhp_notify,
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};
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static void auto_demotion_disable(void *dummy)
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{
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unsigned long long msr_bits;
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rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
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msr_bits &= ~(icpu->auto_demotion_disable_flags);
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wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
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}
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static const struct idle_cpu idle_cpu_nehalem = {
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.state_table = nehalem_cstates,
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.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
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};
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static const struct idle_cpu idle_cpu_atom = {
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.state_table = atom_cstates,
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};
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static const struct idle_cpu idle_cpu_lincroft = {
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.state_table = atom_cstates,
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.auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
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};
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static const struct idle_cpu idle_cpu_snb = {
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.state_table = snb_cstates,
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};
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#define ICPU(model, cpu) \
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{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
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static const struct x86_cpu_id intel_idle_ids[] = {
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ICPU(0x1a, idle_cpu_nehalem),
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ICPU(0x1e, idle_cpu_nehalem),
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ICPU(0x1f, idle_cpu_nehalem),
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ICPU(0x25, idle_cpu_nehalem),
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ICPU(0x2c, idle_cpu_nehalem),
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ICPU(0x2e, idle_cpu_nehalem),
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ICPU(0x1c, idle_cpu_atom),
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ICPU(0x26, idle_cpu_lincroft),
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ICPU(0x2f, idle_cpu_nehalem),
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ICPU(0x2a, idle_cpu_snb),
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ICPU(0x2d, idle_cpu_snb),
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{}
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};
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MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
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/*
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* intel_idle_probe()
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*/
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static int intel_idle_probe(void)
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{
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unsigned int eax, ebx, ecx;
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const struct x86_cpu_id *id;
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if (max_cstate == 0) {
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pr_debug(PREFIX "disabled\n");
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return -EPERM;
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}
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id = x86_match_cpu(intel_idle_ids);
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if (!id) {
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if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
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boot_cpu_data.x86 == 6)
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pr_debug(PREFIX "does not run on family %d model %d\n",
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boot_cpu_data.x86, boot_cpu_data.x86_model);
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return -ENODEV;
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}
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if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
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return -ENODEV;
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cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
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if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
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!(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
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!mwait_substates)
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return -ENODEV;
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pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
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icpu = (const struct idle_cpu *)id->driver_data;
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cpuidle_state_table = icpu->state_table;
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if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
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lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
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else {
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on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
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register_cpu_notifier(&setup_broadcast_notifier);
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}
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pr_debug(PREFIX "v" INTEL_IDLE_VERSION
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" model 0x%X\n", boot_cpu_data.x86_model);
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pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
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lapic_timer_reliable_states);
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return 0;
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}
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/*
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* intel_idle_cpuidle_devices_uninit()
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* unregister, free cpuidle_devices
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*/
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static void intel_idle_cpuidle_devices_uninit(void)
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{
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int i;
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struct cpuidle_device *dev;
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for_each_online_cpu(i) {
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dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
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cpuidle_unregister_device(dev);
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}
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free_percpu(intel_idle_cpuidle_devices);
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return;
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}
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/*
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* intel_idle_cpuidle_driver_init()
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* allocate, initialize cpuidle_states
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*/
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static int intel_idle_cpuidle_driver_init(void)
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{
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int cstate;
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struct cpuidle_driver *drv = &intel_idle_driver;
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drv->state_count = 1;
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for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
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int num_substates;
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if (cstate > max_cstate) {
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printk(PREFIX "max_cstate %d reached\n",
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max_cstate);
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break;
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}
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/* does the state exist in CPUID.MWAIT? */
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num_substates = (mwait_substates >> ((cstate) * 4))
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& MWAIT_SUBSTATE_MASK;
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if (num_substates == 0)
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continue;
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/* is the state not enabled? */
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if (cpuidle_state_table[cstate].enter == NULL) {
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/* does the driver not know about the state? */
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if (*cpuidle_state_table[cstate].name == '\0')
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pr_debug(PREFIX "unaware of model 0x%x"
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" MWAIT %d please"
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" contact lenb@kernel.org",
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boot_cpu_data.x86_model, cstate);
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continue;
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}
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if ((cstate > 2) &&
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!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
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mark_tsc_unstable("TSC halts in idle"
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" states deeper than C2");
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drv->states[drv->state_count] = /* structure copy */
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cpuidle_state_table[cstate];
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drv->state_count += 1;
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}
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if (icpu->auto_demotion_disable_flags)
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on_each_cpu(auto_demotion_disable, NULL, 1);
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return 0;
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}
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/*
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* intel_idle_cpu_init()
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* allocate, initialize, register cpuidle_devices
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* @cpu: cpu/core to initialize
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*/
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int intel_idle_cpu_init(int cpu)
|
|
{
|
|
int cstate;
|
|
struct cpuidle_device *dev;
|
|
|
|
dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
|
|
|
|
dev->state_count = 1;
|
|
|
|
for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
|
|
int num_substates;
|
|
|
|
if (cstate > max_cstate) {
|
|
printk(PREFIX "max_cstate %d reached\n", max_cstate);
|
|
break;
|
|
}
|
|
|
|
/* does the state exist in CPUID.MWAIT? */
|
|
num_substates = (mwait_substates >> ((cstate) * 4))
|
|
& MWAIT_SUBSTATE_MASK;
|
|
if (num_substates == 0)
|
|
continue;
|
|
/* is the state not enabled? */
|
|
if (cpuidle_state_table[cstate].enter == NULL)
|
|
continue;
|
|
|
|
dev->states_usage[dev->state_count].driver_data =
|
|
(void *)get_driver_data(cstate);
|
|
|
|
dev->state_count += 1;
|
|
}
|
|
|
|
dev->cpu = cpu;
|
|
|
|
if (cpuidle_register_device(dev)) {
|
|
pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
|
|
intel_idle_cpuidle_devices_uninit();
|
|
return -EIO;
|
|
}
|
|
|
|
if (icpu->auto_demotion_disable_flags)
|
|
smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(intel_idle_cpu_init);
|
|
|
|
static int __init intel_idle_init(void)
|
|
{
|
|
int retval, i;
|
|
|
|
/* Do not load intel_idle at all for now if idle= is passed */
|
|
if (boot_option_idle_override != IDLE_NO_OVERRIDE)
|
|
return -ENODEV;
|
|
|
|
retval = intel_idle_probe();
|
|
if (retval)
|
|
return retval;
|
|
|
|
intel_idle_cpuidle_driver_init();
|
|
retval = cpuidle_register_driver(&intel_idle_driver);
|
|
if (retval) {
|
|
printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
|
|
cpuidle_get_driver()->name);
|
|
return retval;
|
|
}
|
|
|
|
intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
|
|
if (intel_idle_cpuidle_devices == NULL)
|
|
return -ENOMEM;
|
|
|
|
for_each_online_cpu(i) {
|
|
retval = intel_idle_cpu_init(i);
|
|
if (retval) {
|
|
cpuidle_unregister_driver(&intel_idle_driver);
|
|
return retval;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit intel_idle_exit(void)
|
|
{
|
|
intel_idle_cpuidle_devices_uninit();
|
|
cpuidle_unregister_driver(&intel_idle_driver);
|
|
|
|
if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) {
|
|
on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
|
|
unregister_cpu_notifier(&setup_broadcast_notifier);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
module_init(intel_idle_init);
|
|
module_exit(intel_idle_exit);
|
|
|
|
module_param(max_cstate, int, 0444);
|
|
|
|
MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
|
|
MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
|
|
MODULE_LICENSE("GPL");
|