258 строки
7.0 KiB
C
258 строки
7.0 KiB
C
/*
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* linux/arch/arm/plat-nomadik/timer.c
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*
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* Copyright (C) 2008 STMicroelectronics
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* Copyright (C) 2010 Alessandro Rubini
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* Copyright (C) 2010 Linus Walleij for ST-Ericsson
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/clockchips.h>
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#include <linux/clk.h>
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#include <linux/jiffies.h>
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#include <linux/err.h>
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#include <linux/cnt32_to_63.h>
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#include <linux/timer.h>
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#include <asm/mach/time.h>
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#include <plat/mtu.h>
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void __iomem *mtu_base; /* Assigned by machine code */
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/*
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* Kernel assumes that sched_clock can be called early
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* but the MTU may not yet be initialized.
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*/
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static cycle_t nmdk_read_timer_dummy(struct clocksource *cs)
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{
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return 0;
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}
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/* clocksource: MTU decrements, so we negate the value being read. */
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static cycle_t nmdk_read_timer(struct clocksource *cs)
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{
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return -readl(mtu_base + MTU_VAL(0));
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}
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static struct clocksource nmdk_clksrc = {
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.name = "mtu_0",
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.rating = 200,
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.read = nmdk_read_timer_dummy,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/*
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* Override the global weak sched_clock symbol with this
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* local implementation which uses the clocksource to get some
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* better resolution when scheduling the kernel.
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*
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* Because the hardware timer period may be quite short
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* (32.3 secs on the 133 MHz MTU timer selection on ux500)
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* and because cnt32_to_63() needs to be called at least once per
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* half period to work properly, a kernel keepwarm() timer is set up
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* to ensure this requirement is always met.
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*
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* Also the sched_clock timer will wrap around at some point,
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* here we set it to run continously for a year.
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*/
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#define SCHED_CLOCK_MIN_WRAP 3600*24*365
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static struct timer_list cnt32_to_63_keepwarm_timer;
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static u32 sched_mult;
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static u32 sched_shift;
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unsigned long long notrace sched_clock(void)
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{
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u64 cycles;
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if (unlikely(!mtu_base))
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return 0;
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cycles = cnt32_to_63(-readl(mtu_base + MTU_VAL(0)));
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/*
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* sched_mult is guaranteed to be even so will
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* shift out bit 63
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*/
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return (cycles * sched_mult) >> sched_shift;
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}
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/* Just kick sched_clock every so often */
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static void cnt32_to_63_keepwarm(unsigned long data)
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{
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mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data));
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(void) sched_clock();
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}
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/*
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* Set up a timer to keep sched_clock():s 32_to_63 algorithm warm
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* once in half a 32bit timer wrap interval.
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*/
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static void __init nmdk_sched_clock_init(unsigned long rate)
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{
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u32 v;
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unsigned long delta;
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u64 days;
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/* Find the apropriate mult and shift factors */
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clocks_calc_mult_shift(&sched_mult, &sched_shift,
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rate, NSEC_PER_SEC, SCHED_CLOCK_MIN_WRAP);
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/* We need to multiply by an even number to get rid of bit 63 */
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if (sched_mult & 1)
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sched_mult++;
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/* Let's see what we get, take max counter and scale it */
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days = (0xFFFFFFFFFFFFFFFFLLU * sched_mult) >> sched_shift;
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do_div(days, NSEC_PER_SEC);
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do_div(days, (3600*24));
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pr_info("sched_clock: using %d bits @ %lu Hz wrap in %lu days\n",
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(64 - sched_shift), rate, (unsigned long) days);
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/*
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* Program a timer to kick us at half 32bit wraparound
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* Formula: seconds per wrap = (2^32) / f
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*/
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v = 0xFFFFFFFFUL / rate;
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/* We want half of the wrap time to keep cnt32_to_63 warm */
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v /= 2;
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pr_debug("sched_clock: prescaled timer rate: %lu Hz, "
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"initialize keepwarm timer every %d seconds\n", rate, v);
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/* Convert seconds to jiffies */
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delta = msecs_to_jiffies(v*1000);
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setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, delta);
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mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + delta));
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}
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/* Clockevent device: use one-shot mode */
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static void nmdk_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *dev)
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{
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u32 cr;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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pr_err("%s: periodic mode not supported\n", __func__);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Load highest value, enable device, enable interrupts */
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cr = readl(mtu_base + MTU_CR(1));
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writel(0, mtu_base + MTU_LR(1));
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writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
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writel(1 << 1, mtu_base + MTU_IMSC);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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/* disable irq */
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writel(0, mtu_base + MTU_IMSC);
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/* disable timer */
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cr = readl(mtu_base + MTU_CR(1));
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cr &= ~MTU_CRn_ENA;
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writel(cr, mtu_base + MTU_CR(1));
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/* load some high default value */
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writel(0xffffffff, mtu_base + MTU_LR(1));
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break;
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
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{
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/* writing the value has immediate effect */
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writel(evt, mtu_base + MTU_LR(1));
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return 0;
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}
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static struct clock_event_device nmdk_clkevt = {
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.name = "mtu_1",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 200,
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.set_mode = nmdk_clkevt_mode,
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.set_next_event = nmdk_clkevt_next,
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};
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/*
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* IRQ Handler for timer 1 of the MTU block.
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*/
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static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evdev = dev_id;
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writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
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evdev->event_handler(evdev);
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return IRQ_HANDLED;
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}
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static struct irqaction nmdk_timer_irq = {
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.name = "Nomadik Timer Tick",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = nmdk_timer_interrupt,
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.dev_id = &nmdk_clkevt,
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};
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void __init nmdk_timer_init(void)
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{
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unsigned long rate;
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struct clk *clk0;
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u32 cr = MTU_CRn_32BITS;
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clk0 = clk_get_sys("mtu0", NULL);
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BUG_ON(IS_ERR(clk0));
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clk_enable(clk0);
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/*
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* Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
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* for ux500.
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* Use a divide-by-16 counter if the tick rate is more than 32MHz.
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* At 32 MHz, the timer (with 32 bit counter) can be programmed
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* to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
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* with 16 gives too low timer resolution.
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*/
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rate = clk_get_rate(clk0);
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if (rate > 32000000) {
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rate /= 16;
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cr |= MTU_CRn_PRESCALE_16;
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} else {
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cr |= MTU_CRn_PRESCALE_1;
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}
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clocksource_calc_mult_shift(&nmdk_clksrc, rate, MTU_MIN_RANGE);
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/* Timer 0 is the free running clocksource */
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writel(cr, mtu_base + MTU_CR(0));
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writel(0, mtu_base + MTU_LR(0));
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writel(0, mtu_base + MTU_BGLR(0));
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writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
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/* Now the clock source is ready */
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nmdk_clksrc.read = nmdk_read_timer;
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if (clocksource_register(&nmdk_clksrc))
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pr_err("timer: failed to initialize clock source %s\n",
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nmdk_clksrc.name);
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nmdk_sched_clock_init(rate);
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/* Timer 1 is used for events */
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clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
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writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
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nmdk_clkevt.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
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nmdk_clkevt.min_delta_ns =
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clockevent_delta2ns(0x00000002, &nmdk_clkevt);
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nmdk_clkevt.cpumask = cpumask_of(0);
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/* Register irq and clockevents */
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setup_irq(IRQ_MTU0, &nmdk_timer_irq);
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clockevents_register_device(&nmdk_clkevt);
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}
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