270 строки
6.2 KiB
C
270 строки
6.2 KiB
C
/*
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* linux/arch/alpha/kernel/sys_nautilus.c
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*
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* Copyright (C) 1995 David A Rusling
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* Copyright (C) 1998 Richard Henderson
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* Copyright (C) 1999 Alpha Processor, Inc.,
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* (David Daniel, Stig Telfer, Soohoon Lee)
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*
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* Code supporting NAUTILUS systems.
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*
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*
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* NAUTILUS has the following I/O features:
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*
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* a) Driven by AMD 751 aka IRONGATE (northbridge):
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* 4 PCI slots
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* 1 AGP slot
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*
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* b) Driven by ALI M1543C (southbridge)
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* 2 ISA slots
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* 2 IDE connectors
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* 1 dual drive capable FDD controller
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* 2 serial ports
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* 1 ECP/EPP/SP parallel port
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* 2 USB ports
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/reboot.h>
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#include <linux/bootmem.h>
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#include <linux/bitops.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/pgtable.h>
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#include <asm/core_irongate.h>
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#include <asm/hwrpb.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "err_impl.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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static void __init
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nautilus_init_irq(void)
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{
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if (alpha_using_srm) {
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alpha_mv.device_interrupt = srm_device_interrupt;
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}
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init_i8259a_irqs();
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common_init_isa_dma();
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}
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static int __init
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nautilus_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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/* Preserve the IRQ set up by the console. */
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u8 irq;
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
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return irq;
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}
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void
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nautilus_kill_arch(int mode)
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{
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struct pci_bus *bus = pci_isa_hose->bus;
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u32 pmuport;
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int off;
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switch (mode) {
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case LINUX_REBOOT_CMD_RESTART:
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if (! alpha_using_srm) {
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u8 t8;
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pci_bus_read_config_byte(bus, 0x38, 0x43, &t8);
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pci_bus_write_config_byte(bus, 0x38, 0x43, t8 | 0x80);
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outb(1, 0x92);
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outb(0, 0x92);
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/* NOTREACHED */
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}
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break;
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case LINUX_REBOOT_CMD_POWER_OFF:
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/* Assume M1543C */
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off = 0x2000; /* SLP_TYPE = 0, SLP_EN = 1 */
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pci_bus_read_config_dword(bus, 0x88, 0x10, &pmuport);
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if (!pmuport) {
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/* M1535D/D+ */
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off = 0x3400; /* SLP_TYPE = 5, SLP_EN = 1 */
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pci_bus_read_config_dword(bus, 0x88, 0xe0, &pmuport);
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}
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pmuport &= 0xfffe;
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outw(0xffff, pmuport); /* Clear pending events. */
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outw(off, pmuport + 4);
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/* NOTREACHED */
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break;
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}
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}
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/* Perform analysis of a machine check that arrived from the system (NMI) */
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static void
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naut_sys_machine_check(unsigned long vector, unsigned long la_ptr,
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struct pt_regs *regs)
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{
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printk("PC %lx RA %lx\n", regs->pc, regs->r26);
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irongate_pci_clr_err();
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}
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/* Machine checks can come from two sources - those on the CPU and those
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in the system. They are analysed separately but all starts here. */
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void
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nautilus_machine_check(unsigned long vector, unsigned long la_ptr,
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struct pt_regs *regs)
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{
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char *mchk_class;
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/* Now for some analysis. Machine checks fall into two classes --
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those picked up by the system, and those picked up by the CPU.
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Add to that the two levels of severity - correctable or not. */
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if (vector == SCB_Q_SYSMCHK
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&& ((IRONGATE0->dramms & 0x300) == 0x300)) {
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unsigned long nmi_ctl;
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/* Clear ALI NMI */
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nmi_ctl = inb(0x61);
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nmi_ctl |= 0x0c;
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outb(nmi_ctl, 0x61);
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nmi_ctl &= ~0x0c;
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outb(nmi_ctl, 0x61);
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/* Write again clears error bits. */
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IRONGATE0->stat_cmd = IRONGATE0->stat_cmd & ~0x100;
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mb();
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IRONGATE0->stat_cmd;
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/* Write again clears error bits. */
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IRONGATE0->dramms = IRONGATE0->dramms;
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mb();
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IRONGATE0->dramms;
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draina();
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wrmces(0x7);
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mb();
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return;
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}
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if (vector == SCB_Q_SYSERR)
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mchk_class = "Correctable";
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else if (vector == SCB_Q_SYSMCHK)
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mchk_class = "Fatal";
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else {
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ev6_machine_check(vector, la_ptr, regs);
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return;
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}
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printk(KERN_CRIT "NAUTILUS Machine check 0x%lx "
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"[%s System Machine Check (NMI)]\n",
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vector, mchk_class);
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naut_sys_machine_check(vector, la_ptr, regs);
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/* Tell the PALcode to clear the machine check */
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draina();
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wrmces(0x7);
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mb();
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}
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extern void free_reserved_mem(void *, void *);
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static struct resource irongate_mem = {
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.name = "Irongate PCI MEM",
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.flags = IORESOURCE_MEM,
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};
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void __init
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nautilus_init_pci(void)
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{
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struct pci_controller *hose = hose_head;
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struct pci_bus *bus;
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struct pci_dev *irongate;
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unsigned long bus_align, bus_size, pci_mem;
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unsigned long memtop = max_low_pfn << PAGE_SHIFT;
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/* Scan our single hose. */
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bus = pci_scan_bus(0, alpha_mv.pci_ops, hose);
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hose->bus = bus;
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irongate = pci_find_slot(0, 0);
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bus->self = irongate;
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bus->resource[1] = &irongate_mem;
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pci_bus_size_bridges(bus);
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/* IO port range. */
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bus->resource[0]->start = 0;
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bus->resource[0]->end = 0xffff;
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/* Set up PCI memory range - limit is hardwired to 0xffffffff,
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base must be at aligned to 16Mb. */
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bus_align = bus->resource[1]->start;
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bus_size = bus->resource[1]->end + 1 - bus_align;
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if (bus_align < 0x1000000UL)
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bus_align = 0x1000000UL;
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pci_mem = (0x100000000UL - bus_size) & -bus_align;
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bus->resource[1]->start = pci_mem;
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bus->resource[1]->end = 0xffffffffUL;
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if (request_resource(&iomem_resource, bus->resource[1]) < 0)
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printk(KERN_ERR "Failed to request MEM on hose 0\n");
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if (pci_mem < memtop)
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memtop = pci_mem;
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if (memtop > alpha_mv.min_mem_address) {
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free_reserved_mem(__va(alpha_mv.min_mem_address),
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__va(memtop));
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printk("nautilus_init_pci: %ldk freed\n",
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(memtop - alpha_mv.min_mem_address) >> 10);
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}
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if ((IRONGATE0->dev_vendor >> 16) > 0x7006) /* Albacore? */
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IRONGATE0->pci_mem = pci_mem;
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pci_bus_assign_resources(bus);
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pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
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}
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/*
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* The System Vectors
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*/
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struct alpha_machine_vector nautilus_mv __initmv = {
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.vector_name = "Nautilus",
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DO_EV6_MMU,
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DO_DEFAULT_RTC,
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DO_IRONGATE_IO,
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.machine_check = nautilus_machine_check,
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
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.min_io_address = DEFAULT_IO_BASE,
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.min_mem_address = IRONGATE_DEFAULT_MEM_BASE,
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.nr_irqs = 16,
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.device_interrupt = isa_device_interrupt,
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.init_arch = irongate_init_arch,
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.init_irq = nautilus_init_irq,
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.init_rtc = common_init_rtc,
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.init_pci = nautilus_init_pci,
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.kill_arch = nautilus_kill_arch,
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.pci_map_irq = nautilus_map_irq,
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.pci_swizzle = common_swizzle,
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};
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ALIAS_MV(nautilus)
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