587 строки
17 KiB
C
587 строки
17 KiB
C
/*
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* intel TCO Watchdog Driver
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*
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* (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
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* provide warranty for any of this software. This material is
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* provided "AS-IS" and at no charge.
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*
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* The TCO watchdog is implemented in the following I/O controller hubs:
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* (See the intel documentation on http://developer.intel.com.)
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* document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
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* document number 290687-002, 298242-027: 82801BA (ICH2)
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* document number 290733-003, 290739-013: 82801CA (ICH3-S)
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* document number 290716-001, 290718-007: 82801CAM (ICH3-M)
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* document number 290744-001, 290745-025: 82801DB (ICH4)
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* document number 252337-001, 252663-008: 82801DBM (ICH4-M)
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* document number 273599-001, 273645-002: 82801E (C-ICH)
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* document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
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* document number 300641-004, 300884-013: 6300ESB
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* document number 301473-002, 301474-026: 82801F (ICH6)
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* document number 313082-001, 313075-006: 631xESB, 632xESB
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* document number 307013-003, 307014-024: 82801G (ICH7)
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* document number 322896-001, 322897-001: NM10
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* document number 313056-003, 313057-017: 82801H (ICH8)
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* document number 316972-004, 316973-012: 82801I (ICH9)
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* document number 319973-002, 319974-002: 82801J (ICH10)
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* document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
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* document number 320066-003, 320257-008: EP80597 (IICH)
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* document number 324645-001, 324646-001: Cougar Point (CPT)
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* document number TBD : Patsburg (PBG)
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* document number TBD : DH89xxCC
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* document number TBD : Panther Point
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* document number TBD : Lynx Point
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* document number TBD : Lynx Point-LP
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*/
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/*
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* Includes, defines, variables, module parameters, ...
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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/* Module and version information */
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#define DRV_NAME "iTCO_wdt"
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#define DRV_VERSION "1.10"
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/* Includes */
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#include <linux/module.h> /* For module specific items */
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#include <linux/moduleparam.h> /* For new moduleparam's */
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#include <linux/types.h> /* For standard types (like size_t) */
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#include <linux/errno.h> /* For the -ENODEV/... values */
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#include <linux/kernel.h> /* For printk/panic/... */
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#include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
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(WATCHDOG_MINOR) */
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#include <linux/watchdog.h> /* For the watchdog specific items */
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#include <linux/init.h> /* For __init/__exit/... */
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#include <linux/fs.h> /* For file operations */
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#include <linux/platform_device.h> /* For platform_driver framework */
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#include <linux/pci.h> /* For pci functions */
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#include <linux/ioport.h> /* For io-port access */
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#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
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#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
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#include <linux/io.h> /* For inb/outb/... */
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#include <linux/mfd/core.h>
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#include <linux/mfd/lpc_ich.h>
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#include "iTCO_vendor.h"
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/* Address definitions for the TCO */
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/* TCO base address */
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#define TCOBASE (iTCO_wdt_private.tco_res->start)
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/* SMI Control and Enable Register */
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#define SMI_EN (iTCO_wdt_private.smi_res->start)
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#define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
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#define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
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#define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
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#define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
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#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
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#define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
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#define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
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#define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
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#define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
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/* internal variables */
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static struct { /* this is private data for the iTCO_wdt device */
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/* TCO version/generation */
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unsigned int iTCO_version;
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struct resource *tco_res;
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struct resource *smi_res;
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struct resource *gcs_res;
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/* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
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unsigned long __iomem *gcs;
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/* the lock for io operations */
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spinlock_t io_lock;
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struct platform_device *dev;
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/* the PCI-device */
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struct pci_dev *pdev;
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} iTCO_wdt_private;
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/* module parameters */
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#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
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static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
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module_param(heartbeat, int, 0);
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MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
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"5..76 (TCO v1) or 3..614 (TCO v2), default="
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__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static int turn_SMI_watchdog_clear_off = 1;
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module_param(turn_SMI_watchdog_clear_off, int, 0);
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MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
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"Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
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/*
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* Some TCO specific functions
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*/
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static inline unsigned int seconds_to_ticks(int seconds)
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{
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/* the internal timer is stored as ticks which decrement
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* every 0.6 seconds */
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return (seconds * 10) / 6;
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}
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static void iTCO_wdt_set_NO_REBOOT_bit(void)
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{
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u32 val32;
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/* Set the NO_REBOOT bit: this disables reboots */
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if (iTCO_wdt_private.iTCO_version == 2) {
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val32 = readl(iTCO_wdt_private.gcs);
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val32 |= 0x00000020;
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writel(val32, iTCO_wdt_private.gcs);
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} else if (iTCO_wdt_private.iTCO_version == 1) {
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pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
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val32 |= 0x00000002;
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pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
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}
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}
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static int iTCO_wdt_unset_NO_REBOOT_bit(void)
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{
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int ret = 0;
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u32 val32;
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/* Unset the NO_REBOOT bit: this enables reboots */
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if (iTCO_wdt_private.iTCO_version == 2) {
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val32 = readl(iTCO_wdt_private.gcs);
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val32 &= 0xffffffdf;
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writel(val32, iTCO_wdt_private.gcs);
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val32 = readl(iTCO_wdt_private.gcs);
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if (val32 & 0x00000020)
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ret = -EIO;
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} else if (iTCO_wdt_private.iTCO_version == 1) {
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pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
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val32 &= 0xfffffffd;
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pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
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pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
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if (val32 & 0x00000002)
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ret = -EIO;
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}
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return ret; /* returns: 0 = OK, -EIO = Error */
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}
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static int iTCO_wdt_start(struct watchdog_device *wd_dev)
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{
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unsigned int val;
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spin_lock(&iTCO_wdt_private.io_lock);
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iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout);
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/* disable chipset's NO_REBOOT bit */
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if (iTCO_wdt_unset_NO_REBOOT_bit()) {
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spin_unlock(&iTCO_wdt_private.io_lock);
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pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
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return -EIO;
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}
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/* Force the timer to its reload value by writing to the TCO_RLD
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register */
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if (iTCO_wdt_private.iTCO_version == 2)
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outw(0x01, TCO_RLD);
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else if (iTCO_wdt_private.iTCO_version == 1)
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outb(0x01, TCO_RLD);
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/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
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val = inw(TCO1_CNT);
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val &= 0xf7ff;
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outw(val, TCO1_CNT);
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val = inw(TCO1_CNT);
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spin_unlock(&iTCO_wdt_private.io_lock);
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if (val & 0x0800)
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return -1;
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return 0;
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}
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static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
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{
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unsigned int val;
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spin_lock(&iTCO_wdt_private.io_lock);
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iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res);
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/* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
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val = inw(TCO1_CNT);
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val |= 0x0800;
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outw(val, TCO1_CNT);
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val = inw(TCO1_CNT);
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/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
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iTCO_wdt_set_NO_REBOOT_bit();
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spin_unlock(&iTCO_wdt_private.io_lock);
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if ((val & 0x0800) == 0)
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return -1;
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return 0;
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}
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static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
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{
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spin_lock(&iTCO_wdt_private.io_lock);
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iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout);
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/* Reload the timer by writing to the TCO Timer Counter register */
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if (iTCO_wdt_private.iTCO_version == 2)
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outw(0x01, TCO_RLD);
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else if (iTCO_wdt_private.iTCO_version == 1) {
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/* Reset the timeout status bit so that the timer
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* needs to count down twice again before rebooting */
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outw(0x0008, TCO1_STS); /* write 1 to clear bit */
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outb(0x01, TCO_RLD);
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}
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spin_unlock(&iTCO_wdt_private.io_lock);
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return 0;
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}
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static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
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{
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unsigned int val16;
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unsigned char val8;
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unsigned int tmrval;
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tmrval = seconds_to_ticks(t);
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/* For TCO v1 the timer counts down twice before rebooting */
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if (iTCO_wdt_private.iTCO_version == 1)
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tmrval /= 2;
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/* from the specs: */
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/* "Values of 0h-3h are ignored and should not be attempted" */
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if (tmrval < 0x04)
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return -EINVAL;
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if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
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((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
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return -EINVAL;
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iTCO_vendor_pre_set_heartbeat(tmrval);
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/* Write new heartbeat to watchdog */
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if (iTCO_wdt_private.iTCO_version == 2) {
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spin_lock(&iTCO_wdt_private.io_lock);
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val16 = inw(TCOv2_TMR);
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val16 &= 0xfc00;
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val16 |= tmrval;
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outw(val16, TCOv2_TMR);
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val16 = inw(TCOv2_TMR);
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spin_unlock(&iTCO_wdt_private.io_lock);
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if ((val16 & 0x3ff) != tmrval)
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return -EINVAL;
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} else if (iTCO_wdt_private.iTCO_version == 1) {
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spin_lock(&iTCO_wdt_private.io_lock);
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val8 = inb(TCOv1_TMR);
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val8 &= 0xc0;
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val8 |= (tmrval & 0xff);
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outb(val8, TCOv1_TMR);
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val8 = inb(TCOv1_TMR);
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spin_unlock(&iTCO_wdt_private.io_lock);
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if ((val8 & 0x3f) != tmrval)
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return -EINVAL;
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}
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wd_dev->timeout = t;
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return 0;
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}
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static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
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{
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unsigned int val16;
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unsigned char val8;
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unsigned int time_left = 0;
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/* read the TCO Timer */
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if (iTCO_wdt_private.iTCO_version == 2) {
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spin_lock(&iTCO_wdt_private.io_lock);
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val16 = inw(TCO_RLD);
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val16 &= 0x3ff;
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spin_unlock(&iTCO_wdt_private.io_lock);
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time_left = (val16 * 6) / 10;
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} else if (iTCO_wdt_private.iTCO_version == 1) {
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spin_lock(&iTCO_wdt_private.io_lock);
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val8 = inb(TCO_RLD);
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val8 &= 0x3f;
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if (!(inw(TCO1_STS) & 0x0008))
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val8 += (inb(TCOv1_TMR) & 0x3f);
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spin_unlock(&iTCO_wdt_private.io_lock);
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time_left = (val8 * 6) / 10;
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}
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return time_left;
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}
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/*
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* Kernel Interfaces
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*/
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static const struct watchdog_info ident = {
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.options = WDIOF_SETTIMEOUT |
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WDIOF_KEEPALIVEPING |
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WDIOF_MAGICCLOSE,
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.firmware_version = 0,
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.identity = DRV_NAME,
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};
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static const struct watchdog_ops iTCO_wdt_ops = {
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.owner = THIS_MODULE,
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.start = iTCO_wdt_start,
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.stop = iTCO_wdt_stop,
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.ping = iTCO_wdt_ping,
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.set_timeout = iTCO_wdt_set_timeout,
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.get_timeleft = iTCO_wdt_get_timeleft,
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};
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static struct watchdog_device iTCO_wdt_watchdog_dev = {
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.info = &ident,
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.ops = &iTCO_wdt_ops,
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};
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/*
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* Init & exit routines
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*/
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static void iTCO_wdt_cleanup(void)
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{
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/* Stop the timer before we leave */
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if (!nowayout)
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iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
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/* Deregister */
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watchdog_unregister_device(&iTCO_wdt_watchdog_dev);
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/* release resources */
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release_region(iTCO_wdt_private.tco_res->start,
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resource_size(iTCO_wdt_private.tco_res));
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release_region(iTCO_wdt_private.smi_res->start,
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resource_size(iTCO_wdt_private.smi_res));
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if (iTCO_wdt_private.iTCO_version == 2) {
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iounmap(iTCO_wdt_private.gcs);
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release_mem_region(iTCO_wdt_private.gcs_res->start,
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resource_size(iTCO_wdt_private.gcs_res));
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}
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iTCO_wdt_private.tco_res = NULL;
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iTCO_wdt_private.smi_res = NULL;
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iTCO_wdt_private.gcs_res = NULL;
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iTCO_wdt_private.gcs = NULL;
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}
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static int iTCO_wdt_probe(struct platform_device *dev)
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{
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int ret = -ENODEV;
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unsigned long val32;
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struct lpc_ich_info *ich_info = dev->dev.platform_data;
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if (!ich_info)
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goto out;
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spin_lock_init(&iTCO_wdt_private.io_lock);
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iTCO_wdt_private.tco_res =
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platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO);
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if (!iTCO_wdt_private.tco_res)
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goto out;
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iTCO_wdt_private.smi_res =
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platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI);
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if (!iTCO_wdt_private.smi_res)
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goto out;
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iTCO_wdt_private.iTCO_version = ich_info->iTCO_version;
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iTCO_wdt_private.dev = dev;
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iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent);
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/*
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* Get the Memory-Mapped GCS register, we need it for the
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* NO_REBOOT flag (TCO v2).
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*/
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if (iTCO_wdt_private.iTCO_version == 2) {
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iTCO_wdt_private.gcs_res = platform_get_resource(dev,
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IORESOURCE_MEM,
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ICH_RES_MEM_GCS);
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if (!iTCO_wdt_private.gcs_res)
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goto out;
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if (!request_mem_region(iTCO_wdt_private.gcs_res->start,
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resource_size(iTCO_wdt_private.gcs_res), dev->name)) {
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ret = -EBUSY;
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goto out;
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}
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iTCO_wdt_private.gcs = ioremap(iTCO_wdt_private.gcs_res->start,
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resource_size(iTCO_wdt_private.gcs_res));
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if (!iTCO_wdt_private.gcs) {
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ret = -EIO;
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goto unreg_gcs;
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}
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}
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/* Check chipset's NO_REBOOT bit */
|
|
if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
|
|
pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
|
|
ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
|
|
goto unmap_gcs;
|
|
}
|
|
|
|
/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
|
|
iTCO_wdt_set_NO_REBOOT_bit();
|
|
|
|
/* The TCO logic uses the TCO_EN bit in the SMI_EN register */
|
|
if (!request_region(iTCO_wdt_private.smi_res->start,
|
|
resource_size(iTCO_wdt_private.smi_res), dev->name)) {
|
|
pr_err("I/O address 0x%04llx already in use, device disabled\n",
|
|
(u64)SMI_EN);
|
|
ret = -EBUSY;
|
|
goto unmap_gcs;
|
|
}
|
|
if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) {
|
|
/*
|
|
* Bit 13: TCO_EN -> 0
|
|
* Disables TCO logic generating an SMI#
|
|
*/
|
|
val32 = inl(SMI_EN);
|
|
val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
|
|
outl(val32, SMI_EN);
|
|
}
|
|
|
|
if (!request_region(iTCO_wdt_private.tco_res->start,
|
|
resource_size(iTCO_wdt_private.tco_res), dev->name)) {
|
|
pr_err("I/O address 0x%04llx already in use, device disabled\n",
|
|
(u64)TCOBASE);
|
|
ret = -EBUSY;
|
|
goto unreg_smi;
|
|
}
|
|
|
|
pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
|
|
ich_info->name, ich_info->iTCO_version, (u64)TCOBASE);
|
|
|
|
/* Clear out the (probably old) status */
|
|
outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
|
|
outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
|
|
outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */
|
|
|
|
iTCO_wdt_watchdog_dev.bootstatus = 0;
|
|
iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT;
|
|
watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout);
|
|
iTCO_wdt_watchdog_dev.parent = dev->dev.parent;
|
|
|
|
/* Make sure the watchdog is not running */
|
|
iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
|
|
|
|
/* Check that the heartbeat value is within it's range;
|
|
if not reset to the default */
|
|
if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) {
|
|
iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT);
|
|
pr_info("timeout value out of range, using %d\n",
|
|
WATCHDOG_TIMEOUT);
|
|
}
|
|
|
|
ret = watchdog_register_device(&iTCO_wdt_watchdog_dev);
|
|
if (ret != 0) {
|
|
pr_err("cannot register watchdog device (err=%d)\n", ret);
|
|
goto unreg_tco;
|
|
}
|
|
|
|
pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
|
|
heartbeat, nowayout);
|
|
|
|
return 0;
|
|
|
|
unreg_tco:
|
|
release_region(iTCO_wdt_private.tco_res->start,
|
|
resource_size(iTCO_wdt_private.tco_res));
|
|
unreg_smi:
|
|
release_region(iTCO_wdt_private.smi_res->start,
|
|
resource_size(iTCO_wdt_private.smi_res));
|
|
unmap_gcs:
|
|
if (iTCO_wdt_private.iTCO_version == 2)
|
|
iounmap(iTCO_wdt_private.gcs);
|
|
unreg_gcs:
|
|
if (iTCO_wdt_private.iTCO_version == 2)
|
|
release_mem_region(iTCO_wdt_private.gcs_res->start,
|
|
resource_size(iTCO_wdt_private.gcs_res));
|
|
out:
|
|
iTCO_wdt_private.tco_res = NULL;
|
|
iTCO_wdt_private.smi_res = NULL;
|
|
iTCO_wdt_private.gcs_res = NULL;
|
|
iTCO_wdt_private.gcs = NULL;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int iTCO_wdt_remove(struct platform_device *dev)
|
|
{
|
|
if (iTCO_wdt_private.tco_res || iTCO_wdt_private.smi_res)
|
|
iTCO_wdt_cleanup();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void iTCO_wdt_shutdown(struct platform_device *dev)
|
|
{
|
|
iTCO_wdt_stop(NULL);
|
|
}
|
|
|
|
static struct platform_driver iTCO_wdt_driver = {
|
|
.probe = iTCO_wdt_probe,
|
|
.remove = iTCO_wdt_remove,
|
|
.shutdown = iTCO_wdt_shutdown,
|
|
.driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = DRV_NAME,
|
|
},
|
|
};
|
|
|
|
static int __init iTCO_wdt_init_module(void)
|
|
{
|
|
int err;
|
|
|
|
pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
|
|
|
|
err = platform_driver_register(&iTCO_wdt_driver);
|
|
if (err)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit iTCO_wdt_cleanup_module(void)
|
|
{
|
|
platform_driver_unregister(&iTCO_wdt_driver);
|
|
pr_info("Watchdog Module Unloaded\n");
|
|
}
|
|
|
|
module_init(iTCO_wdt_init_module);
|
|
module_exit(iTCO_wdt_cleanup_module);
|
|
|
|
MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
|
|
MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
|
|
MODULE_VERSION(DRV_VERSION);
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|