971 строка
24 KiB
Plaintext
971 строка
24 KiB
Plaintext
# x86 Opcode Maps
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#
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# This is (mostly) based on following documentations.
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# - Intel(R) 64 and IA-32 Architectures Software Developer's Manual Vol.2C
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# (#326018-047US, June 2013)
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#
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#<Opcode maps>
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# Table: table-name
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# Referrer: escaped-name
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# AVXcode: avx-code
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# opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
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# (or)
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# opcode: escape # escaped-name
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# EndTable
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#
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#<group maps>
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# GrpTable: GrpXXX
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# reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
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# EndTable
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#
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# AVX Superscripts
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# (v): this opcode requires VEX prefix.
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# (v1): this opcode only supports 128bit VEX.
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#
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# Last Prefix Superscripts
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# - (66): the last prefix is 0x66
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# - (F3): the last prefix is 0xF3
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# - (F2): the last prefix is 0xF2
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# - (!F3) : the last prefix is not 0xF3 (including non-last prefix case)
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# - (66&F2): Both 0x66 and 0xF2 prefixes are specified.
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Table: one byte opcode
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Referrer:
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AVXcode:
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# 0x00 - 0x0f
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00: ADD Eb,Gb
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01: ADD Ev,Gv
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02: ADD Gb,Eb
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03: ADD Gv,Ev
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04: ADD AL,Ib
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05: ADD rAX,Iz
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06: PUSH ES (i64)
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07: POP ES (i64)
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08: OR Eb,Gb
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09: OR Ev,Gv
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0a: OR Gb,Eb
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0b: OR Gv,Ev
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0c: OR AL,Ib
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0d: OR rAX,Iz
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0e: PUSH CS (i64)
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0f: escape # 2-byte escape
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# 0x10 - 0x1f
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10: ADC Eb,Gb
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11: ADC Ev,Gv
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12: ADC Gb,Eb
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13: ADC Gv,Ev
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14: ADC AL,Ib
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15: ADC rAX,Iz
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16: PUSH SS (i64)
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17: POP SS (i64)
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18: SBB Eb,Gb
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19: SBB Ev,Gv
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1a: SBB Gb,Eb
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1b: SBB Gv,Ev
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1c: SBB AL,Ib
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1d: SBB rAX,Iz
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1e: PUSH DS (i64)
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1f: POP DS (i64)
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# 0x20 - 0x2f
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20: AND Eb,Gb
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21: AND Ev,Gv
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22: AND Gb,Eb
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23: AND Gv,Ev
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24: AND AL,Ib
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25: AND rAx,Iz
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26: SEG=ES (Prefix)
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27: DAA (i64)
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28: SUB Eb,Gb
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29: SUB Ev,Gv
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2a: SUB Gb,Eb
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2b: SUB Gv,Ev
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2c: SUB AL,Ib
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2d: SUB rAX,Iz
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2e: SEG=CS (Prefix)
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2f: DAS (i64)
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# 0x30 - 0x3f
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30: XOR Eb,Gb
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31: XOR Ev,Gv
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32: XOR Gb,Eb
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33: XOR Gv,Ev
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34: XOR AL,Ib
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35: XOR rAX,Iz
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36: SEG=SS (Prefix)
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37: AAA (i64)
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38: CMP Eb,Gb
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39: CMP Ev,Gv
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3a: CMP Gb,Eb
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3b: CMP Gv,Ev
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3c: CMP AL,Ib
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3d: CMP rAX,Iz
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3e: SEG=DS (Prefix)
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3f: AAS (i64)
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# 0x40 - 0x4f
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40: INC eAX (i64) | REX (o64)
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41: INC eCX (i64) | REX.B (o64)
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42: INC eDX (i64) | REX.X (o64)
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43: INC eBX (i64) | REX.XB (o64)
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44: INC eSP (i64) | REX.R (o64)
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45: INC eBP (i64) | REX.RB (o64)
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46: INC eSI (i64) | REX.RX (o64)
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47: INC eDI (i64) | REX.RXB (o64)
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48: DEC eAX (i64) | REX.W (o64)
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49: DEC eCX (i64) | REX.WB (o64)
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4a: DEC eDX (i64) | REX.WX (o64)
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4b: DEC eBX (i64) | REX.WXB (o64)
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4c: DEC eSP (i64) | REX.WR (o64)
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4d: DEC eBP (i64) | REX.WRB (o64)
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4e: DEC eSI (i64) | REX.WRX (o64)
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4f: DEC eDI (i64) | REX.WRXB (o64)
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# 0x50 - 0x5f
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50: PUSH rAX/r8 (d64)
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51: PUSH rCX/r9 (d64)
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52: PUSH rDX/r10 (d64)
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53: PUSH rBX/r11 (d64)
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54: PUSH rSP/r12 (d64)
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55: PUSH rBP/r13 (d64)
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56: PUSH rSI/r14 (d64)
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57: PUSH rDI/r15 (d64)
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58: POP rAX/r8 (d64)
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59: POP rCX/r9 (d64)
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5a: POP rDX/r10 (d64)
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5b: POP rBX/r11 (d64)
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5c: POP rSP/r12 (d64)
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5d: POP rBP/r13 (d64)
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5e: POP rSI/r14 (d64)
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5f: POP rDI/r15 (d64)
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# 0x60 - 0x6f
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60: PUSHA/PUSHAD (i64)
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61: POPA/POPAD (i64)
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62: BOUND Gv,Ma (i64)
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63: ARPL Ew,Gw (i64) | MOVSXD Gv,Ev (o64)
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64: SEG=FS (Prefix)
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65: SEG=GS (Prefix)
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66: Operand-Size (Prefix)
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67: Address-Size (Prefix)
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68: PUSH Iz (d64)
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69: IMUL Gv,Ev,Iz
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6a: PUSH Ib (d64)
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6b: IMUL Gv,Ev,Ib
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6c: INS/INSB Yb,DX
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6d: INS/INSW/INSD Yz,DX
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6e: OUTS/OUTSB DX,Xb
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6f: OUTS/OUTSW/OUTSD DX,Xz
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# 0x70 - 0x7f
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70: JO Jb
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71: JNO Jb
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72: JB/JNAE/JC Jb
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73: JNB/JAE/JNC Jb
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74: JZ/JE Jb
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75: JNZ/JNE Jb
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76: JBE/JNA Jb
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77: JNBE/JA Jb
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78: JS Jb
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79: JNS Jb
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7a: JP/JPE Jb
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7b: JNP/JPO Jb
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7c: JL/JNGE Jb
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7d: JNL/JGE Jb
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7e: JLE/JNG Jb
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7f: JNLE/JG Jb
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# 0x80 - 0x8f
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80: Grp1 Eb,Ib (1A)
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81: Grp1 Ev,Iz (1A)
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82: Grp1 Eb,Ib (1A),(i64)
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83: Grp1 Ev,Ib (1A)
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84: TEST Eb,Gb
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85: TEST Ev,Gv
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86: XCHG Eb,Gb
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87: XCHG Ev,Gv
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88: MOV Eb,Gb
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89: MOV Ev,Gv
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8a: MOV Gb,Eb
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8b: MOV Gv,Ev
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8c: MOV Ev,Sw
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8d: LEA Gv,M
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8e: MOV Sw,Ew
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8f: Grp1A (1A) | POP Ev (d64)
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# 0x90 - 0x9f
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90: NOP | PAUSE (F3) | XCHG r8,rAX
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91: XCHG rCX/r9,rAX
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92: XCHG rDX/r10,rAX
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93: XCHG rBX/r11,rAX
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94: XCHG rSP/r12,rAX
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95: XCHG rBP/r13,rAX
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96: XCHG rSI/r14,rAX
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97: XCHG rDI/r15,rAX
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98: CBW/CWDE/CDQE
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99: CWD/CDQ/CQO
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9a: CALLF Ap (i64)
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9b: FWAIT/WAIT
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9c: PUSHF/D/Q Fv (d64)
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9d: POPF/D/Q Fv (d64)
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9e: SAHF
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9f: LAHF
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# 0xa0 - 0xaf
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a0: MOV AL,Ob
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a1: MOV rAX,Ov
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a2: MOV Ob,AL
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a3: MOV Ov,rAX
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a4: MOVS/B Yb,Xb
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a5: MOVS/W/D/Q Yv,Xv
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a6: CMPS/B Xb,Yb
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a7: CMPS/W/D Xv,Yv
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a8: TEST AL,Ib
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a9: TEST rAX,Iz
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aa: STOS/B Yb,AL
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ab: STOS/W/D/Q Yv,rAX
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ac: LODS/B AL,Xb
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ad: LODS/W/D/Q rAX,Xv
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ae: SCAS/B AL,Yb
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# Note: The May 2011 Intel manual shows Xv for the second parameter of the
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# next instruction but Yv is correct
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af: SCAS/W/D/Q rAX,Yv
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# 0xb0 - 0xbf
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b0: MOV AL/R8L,Ib
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b1: MOV CL/R9L,Ib
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b2: MOV DL/R10L,Ib
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b3: MOV BL/R11L,Ib
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b4: MOV AH/R12L,Ib
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b5: MOV CH/R13L,Ib
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b6: MOV DH/R14L,Ib
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b7: MOV BH/R15L,Ib
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b8: MOV rAX/r8,Iv
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b9: MOV rCX/r9,Iv
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ba: MOV rDX/r10,Iv
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bb: MOV rBX/r11,Iv
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bc: MOV rSP/r12,Iv
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bd: MOV rBP/r13,Iv
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be: MOV rSI/r14,Iv
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bf: MOV rDI/r15,Iv
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# 0xc0 - 0xcf
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c0: Grp2 Eb,Ib (1A)
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c1: Grp2 Ev,Ib (1A)
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c2: RETN Iw (f64)
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c3: RETN
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c4: LES Gz,Mp (i64) | VEX+2byte (Prefix)
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c5: LDS Gz,Mp (i64) | VEX+1byte (Prefix)
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c6: Grp11A Eb,Ib (1A)
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c7: Grp11B Ev,Iz (1A)
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c8: ENTER Iw,Ib
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c9: LEAVE (d64)
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ca: RETF Iw
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cb: RETF
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cc: INT3
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cd: INT Ib
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ce: INTO (i64)
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cf: IRET/D/Q
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# 0xd0 - 0xdf
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d0: Grp2 Eb,1 (1A)
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d1: Grp2 Ev,1 (1A)
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d2: Grp2 Eb,CL (1A)
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d3: Grp2 Ev,CL (1A)
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d4: AAM Ib (i64)
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d5: AAD Ib (i64)
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d6:
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d7: XLAT/XLATB
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d8: ESC
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d9: ESC
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da: ESC
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db: ESC
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dc: ESC
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dd: ESC
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de: ESC
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df: ESC
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# 0xe0 - 0xef
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# Note: "forced64" is Intel CPU behavior: they ignore 0x66 prefix
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# in 64-bit mode. AMD CPUs accept 0x66 prefix, it causes RIP truncation
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# to 16 bits. In 32-bit mode, 0x66 is accepted by both Intel and AMD.
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e0: LOOPNE/LOOPNZ Jb (f64)
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e1: LOOPE/LOOPZ Jb (f64)
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e2: LOOP Jb (f64)
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e3: JrCXZ Jb (f64)
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e4: IN AL,Ib
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e5: IN eAX,Ib
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e6: OUT Ib,AL
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e7: OUT Ib,eAX
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# With 0x66 prefix in 64-bit mode, for AMD CPUs immediate offset
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# in "near" jumps and calls is 16-bit. For CALL,
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# push of return address is 16-bit wide, RSP is decremented by 2
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# but is not truncated to 16 bits, unlike RIP.
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e8: CALL Jz (f64)
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e9: JMP-near Jz (f64)
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ea: JMP-far Ap (i64)
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eb: JMP-short Jb (f64)
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ec: IN AL,DX
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ed: IN eAX,DX
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ee: OUT DX,AL
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ef: OUT DX,eAX
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# 0xf0 - 0xff
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f0: LOCK (Prefix)
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f1:
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f2: REPNE (Prefix) | XACQUIRE (Prefix)
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f3: REP/REPE (Prefix) | XRELEASE (Prefix)
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f4: HLT
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f5: CMC
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f6: Grp3_1 Eb (1A)
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f7: Grp3_2 Ev (1A)
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f8: CLC
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f9: STC
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fa: CLI
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fb: STI
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fc: CLD
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fd: STD
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fe: Grp4 (1A)
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ff: Grp5 (1A)
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EndTable
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Table: 2-byte opcode (0x0f)
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Referrer: 2-byte escape
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AVXcode: 1
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# 0x0f 0x00-0x0f
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00: Grp6 (1A)
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01: Grp7 (1A)
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02: LAR Gv,Ew
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03: LSL Gv,Ew
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04:
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05: SYSCALL (o64)
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06: CLTS
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07: SYSRET (o64)
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08: INVD
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09: WBINVD
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0a:
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0b: UD2 (1B)
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0c:
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# AMD's prefetch group. Intel supports prefetchw(/1) only.
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0d: GrpP
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0e: FEMMS
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# 3DNow! uses the last imm byte as opcode extension.
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0f: 3DNow! Pq,Qq,Ib
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# 0x0f 0x10-0x1f
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# NOTE: According to Intel SDM opcode map, vmovups and vmovupd has no operands
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# but it actually has operands. And also, vmovss and vmovsd only accept 128bit.
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# MOVSS/MOVSD has too many forms(3) on SDM. This map just shows a typical form.
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# Many AVX instructions lack v1 superscript, according to Intel AVX-Prgramming
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# Reference A.1
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10: vmovups Vps,Wps | vmovupd Vpd,Wpd (66) | vmovss Vx,Hx,Wss (F3),(v1) | vmovsd Vx,Hx,Wsd (F2),(v1)
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11: vmovups Wps,Vps | vmovupd Wpd,Vpd (66) | vmovss Wss,Hx,Vss (F3),(v1) | vmovsd Wsd,Hx,Vsd (F2),(v1)
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12: vmovlps Vq,Hq,Mq (v1) | vmovhlps Vq,Hq,Uq (v1) | vmovlpd Vq,Hq,Mq (66),(v1) | vmovsldup Vx,Wx (F3) | vmovddup Vx,Wx (F2)
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13: vmovlps Mq,Vq (v1) | vmovlpd Mq,Vq (66),(v1)
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14: vunpcklps Vx,Hx,Wx | vunpcklpd Vx,Hx,Wx (66)
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15: vunpckhps Vx,Hx,Wx | vunpckhpd Vx,Hx,Wx (66)
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16: vmovhps Vdq,Hq,Mq (v1) | vmovlhps Vdq,Hq,Uq (v1) | vmovhpd Vdq,Hq,Mq (66),(v1) | vmovshdup Vx,Wx (F3)
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17: vmovhps Mq,Vq (v1) | vmovhpd Mq,Vq (66),(v1)
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18: Grp16 (1A)
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19:
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1a: BNDCL Ev,Gv | BNDCU Ev,Gv | BNDMOV Gv,Ev | BNDLDX Gv,Ev,Gv
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1b: BNDCN Ev,Gv | BNDMOV Ev,Gv | BNDMK Gv,Ev | BNDSTX Ev,GV,Gv
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1c:
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1d:
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1e:
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1f: NOP Ev
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# 0x0f 0x20-0x2f
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20: MOV Rd,Cd
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21: MOV Rd,Dd
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22: MOV Cd,Rd
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23: MOV Dd,Rd
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24:
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25:
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26:
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27:
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28: vmovaps Vps,Wps | vmovapd Vpd,Wpd (66)
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29: vmovaps Wps,Vps | vmovapd Wpd,Vpd (66)
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2a: cvtpi2ps Vps,Qpi | cvtpi2pd Vpd,Qpi (66) | vcvtsi2ss Vss,Hss,Ey (F3),(v1) | vcvtsi2sd Vsd,Hsd,Ey (F2),(v1)
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2b: vmovntps Mps,Vps | vmovntpd Mpd,Vpd (66)
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2c: cvttps2pi Ppi,Wps | cvttpd2pi Ppi,Wpd (66) | vcvttss2si Gy,Wss (F3),(v1) | vcvttsd2si Gy,Wsd (F2),(v1)
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2d: cvtps2pi Ppi,Wps | cvtpd2pi Qpi,Wpd (66) | vcvtss2si Gy,Wss (F3),(v1) | vcvtsd2si Gy,Wsd (F2),(v1)
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2e: vucomiss Vss,Wss (v1) | vucomisd Vsd,Wsd (66),(v1)
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2f: vcomiss Vss,Wss (v1) | vcomisd Vsd,Wsd (66),(v1)
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# 0x0f 0x30-0x3f
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30: WRMSR
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31: RDTSC
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32: RDMSR
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33: RDPMC
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34: SYSENTER
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35: SYSEXIT
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36:
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37: GETSEC
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38: escape # 3-byte escape 1
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39:
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3a: escape # 3-byte escape 2
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3b:
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3c:
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3d:
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3e:
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3f:
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# 0x0f 0x40-0x4f
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40: CMOVO Gv,Ev
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41: CMOVNO Gv,Ev
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42: CMOVB/C/NAE Gv,Ev
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43: CMOVAE/NB/NC Gv,Ev
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44: CMOVE/Z Gv,Ev
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45: CMOVNE/NZ Gv,Ev
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46: CMOVBE/NA Gv,Ev
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47: CMOVA/NBE Gv,Ev
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48: CMOVS Gv,Ev
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49: CMOVNS Gv,Ev
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4a: CMOVP/PE Gv,Ev
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4b: CMOVNP/PO Gv,Ev
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4c: CMOVL/NGE Gv,Ev
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4d: CMOVNL/GE Gv,Ev
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4e: CMOVLE/NG Gv,Ev
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4f: CMOVNLE/G Gv,Ev
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# 0x0f 0x50-0x5f
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50: vmovmskps Gy,Ups | vmovmskpd Gy,Upd (66)
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51: vsqrtps Vps,Wps | vsqrtpd Vpd,Wpd (66) | vsqrtss Vss,Hss,Wss (F3),(v1) | vsqrtsd Vsd,Hsd,Wsd (F2),(v1)
|
|
52: vrsqrtps Vps,Wps | vrsqrtss Vss,Hss,Wss (F3),(v1)
|
|
53: vrcpps Vps,Wps | vrcpss Vss,Hss,Wss (F3),(v1)
|
|
54: vandps Vps,Hps,Wps | vandpd Vpd,Hpd,Wpd (66)
|
|
55: vandnps Vps,Hps,Wps | vandnpd Vpd,Hpd,Wpd (66)
|
|
56: vorps Vps,Hps,Wps | vorpd Vpd,Hpd,Wpd (66)
|
|
57: vxorps Vps,Hps,Wps | vxorpd Vpd,Hpd,Wpd (66)
|
|
58: vaddps Vps,Hps,Wps | vaddpd Vpd,Hpd,Wpd (66) | vaddss Vss,Hss,Wss (F3),(v1) | vaddsd Vsd,Hsd,Wsd (F2),(v1)
|
|
59: vmulps Vps,Hps,Wps | vmulpd Vpd,Hpd,Wpd (66) | vmulss Vss,Hss,Wss (F3),(v1) | vmulsd Vsd,Hsd,Wsd (F2),(v1)
|
|
5a: vcvtps2pd Vpd,Wps | vcvtpd2ps Vps,Wpd (66) | vcvtss2sd Vsd,Hx,Wss (F3),(v1) | vcvtsd2ss Vss,Hx,Wsd (F2),(v1)
|
|
5b: vcvtdq2ps Vps,Wdq | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3)
|
|
5c: vsubps Vps,Hps,Wps | vsubpd Vpd,Hpd,Wpd (66) | vsubss Vss,Hss,Wss (F3),(v1) | vsubsd Vsd,Hsd,Wsd (F2),(v1)
|
|
5d: vminps Vps,Hps,Wps | vminpd Vpd,Hpd,Wpd (66) | vminss Vss,Hss,Wss (F3),(v1) | vminsd Vsd,Hsd,Wsd (F2),(v1)
|
|
5e: vdivps Vps,Hps,Wps | vdivpd Vpd,Hpd,Wpd (66) | vdivss Vss,Hss,Wss (F3),(v1) | vdivsd Vsd,Hsd,Wsd (F2),(v1)
|
|
5f: vmaxps Vps,Hps,Wps | vmaxpd Vpd,Hpd,Wpd (66) | vmaxss Vss,Hss,Wss (F3),(v1) | vmaxsd Vsd,Hsd,Wsd (F2),(v1)
|
|
# 0x0f 0x60-0x6f
|
|
60: punpcklbw Pq,Qd | vpunpcklbw Vx,Hx,Wx (66),(v1)
|
|
61: punpcklwd Pq,Qd | vpunpcklwd Vx,Hx,Wx (66),(v1)
|
|
62: punpckldq Pq,Qd | vpunpckldq Vx,Hx,Wx (66),(v1)
|
|
63: packsswb Pq,Qq | vpacksswb Vx,Hx,Wx (66),(v1)
|
|
64: pcmpgtb Pq,Qq | vpcmpgtb Vx,Hx,Wx (66),(v1)
|
|
65: pcmpgtw Pq,Qq | vpcmpgtw Vx,Hx,Wx (66),(v1)
|
|
66: pcmpgtd Pq,Qq | vpcmpgtd Vx,Hx,Wx (66),(v1)
|
|
67: packuswb Pq,Qq | vpackuswb Vx,Hx,Wx (66),(v1)
|
|
68: punpckhbw Pq,Qd | vpunpckhbw Vx,Hx,Wx (66),(v1)
|
|
69: punpckhwd Pq,Qd | vpunpckhwd Vx,Hx,Wx (66),(v1)
|
|
6a: punpckhdq Pq,Qd | vpunpckhdq Vx,Hx,Wx (66),(v1)
|
|
6b: packssdw Pq,Qd | vpackssdw Vx,Hx,Wx (66),(v1)
|
|
6c: vpunpcklqdq Vx,Hx,Wx (66),(v1)
|
|
6d: vpunpckhqdq Vx,Hx,Wx (66),(v1)
|
|
6e: movd/q Pd,Ey | vmovd/q Vy,Ey (66),(v1)
|
|
6f: movq Pq,Qq | vmovdqa Vx,Wx (66) | vmovdqu Vx,Wx (F3)
|
|
# 0x0f 0x70-0x7f
|
|
70: pshufw Pq,Qq,Ib | vpshufd Vx,Wx,Ib (66),(v1) | vpshufhw Vx,Wx,Ib (F3),(v1) | vpshuflw Vx,Wx,Ib (F2),(v1)
|
|
71: Grp12 (1A)
|
|
72: Grp13 (1A)
|
|
73: Grp14 (1A)
|
|
74: pcmpeqb Pq,Qq | vpcmpeqb Vx,Hx,Wx (66),(v1)
|
|
75: pcmpeqw Pq,Qq | vpcmpeqw Vx,Hx,Wx (66),(v1)
|
|
76: pcmpeqd Pq,Qq | vpcmpeqd Vx,Hx,Wx (66),(v1)
|
|
# Note: Remove (v), because vzeroall and vzeroupper becomes emms without VEX.
|
|
77: emms | vzeroupper | vzeroall
|
|
78: VMREAD Ey,Gy
|
|
79: VMWRITE Gy,Ey
|
|
7a:
|
|
7b:
|
|
7c: vhaddpd Vpd,Hpd,Wpd (66) | vhaddps Vps,Hps,Wps (F2)
|
|
7d: vhsubpd Vpd,Hpd,Wpd (66) | vhsubps Vps,Hps,Wps (F2)
|
|
7e: movd/q Ey,Pd | vmovd/q Ey,Vy (66),(v1) | vmovq Vq,Wq (F3),(v1)
|
|
7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqu Wx,Vx (F3)
|
|
# 0x0f 0x80-0x8f
|
|
# Note: "forced64" is Intel CPU behavior (see comment about CALL insn).
|
|
80: JO Jz (f64)
|
|
81: JNO Jz (f64)
|
|
82: JB/JC/JNAE Jz (f64)
|
|
83: JAE/JNB/JNC Jz (f64)
|
|
84: JE/JZ Jz (f64)
|
|
85: JNE/JNZ Jz (f64)
|
|
86: JBE/JNA Jz (f64)
|
|
87: JA/JNBE Jz (f64)
|
|
88: JS Jz (f64)
|
|
89: JNS Jz (f64)
|
|
8a: JP/JPE Jz (f64)
|
|
8b: JNP/JPO Jz (f64)
|
|
8c: JL/JNGE Jz (f64)
|
|
8d: JNL/JGE Jz (f64)
|
|
8e: JLE/JNG Jz (f64)
|
|
8f: JNLE/JG Jz (f64)
|
|
# 0x0f 0x90-0x9f
|
|
90: SETO Eb
|
|
91: SETNO Eb
|
|
92: SETB/C/NAE Eb
|
|
93: SETAE/NB/NC Eb
|
|
94: SETE/Z Eb
|
|
95: SETNE/NZ Eb
|
|
96: SETBE/NA Eb
|
|
97: SETA/NBE Eb
|
|
98: SETS Eb
|
|
99: SETNS Eb
|
|
9a: SETP/PE Eb
|
|
9b: SETNP/PO Eb
|
|
9c: SETL/NGE Eb
|
|
9d: SETNL/GE Eb
|
|
9e: SETLE/NG Eb
|
|
9f: SETNLE/G Eb
|
|
# 0x0f 0xa0-0xaf
|
|
a0: PUSH FS (d64)
|
|
a1: POP FS (d64)
|
|
a2: CPUID
|
|
a3: BT Ev,Gv
|
|
a4: SHLD Ev,Gv,Ib
|
|
a5: SHLD Ev,Gv,CL
|
|
a6: GrpPDLK
|
|
a7: GrpRNG
|
|
a8: PUSH GS (d64)
|
|
a9: POP GS (d64)
|
|
aa: RSM
|
|
ab: BTS Ev,Gv
|
|
ac: SHRD Ev,Gv,Ib
|
|
ad: SHRD Ev,Gv,CL
|
|
ae: Grp15 (1A),(1C)
|
|
af: IMUL Gv,Ev
|
|
# 0x0f 0xb0-0xbf
|
|
b0: CMPXCHG Eb,Gb
|
|
b1: CMPXCHG Ev,Gv
|
|
b2: LSS Gv,Mp
|
|
b3: BTR Ev,Gv
|
|
b4: LFS Gv,Mp
|
|
b5: LGS Gv,Mp
|
|
b6: MOVZX Gv,Eb
|
|
b7: MOVZX Gv,Ew
|
|
b8: JMPE (!F3) | POPCNT Gv,Ev (F3)
|
|
b9: Grp10 (1A)
|
|
ba: Grp8 Ev,Ib (1A)
|
|
bb: BTC Ev,Gv
|
|
bc: BSF Gv,Ev (!F3) | TZCNT Gv,Ev (F3)
|
|
bd: BSR Gv,Ev (!F3) | LZCNT Gv,Ev (F3)
|
|
be: MOVSX Gv,Eb
|
|
bf: MOVSX Gv,Ew
|
|
# 0x0f 0xc0-0xcf
|
|
c0: XADD Eb,Gb
|
|
c1: XADD Ev,Gv
|
|
c2: vcmpps Vps,Hps,Wps,Ib | vcmppd Vpd,Hpd,Wpd,Ib (66) | vcmpss Vss,Hss,Wss,Ib (F3),(v1) | vcmpsd Vsd,Hsd,Wsd,Ib (F2),(v1)
|
|
c3: movnti My,Gy
|
|
c4: pinsrw Pq,Ry/Mw,Ib | vpinsrw Vdq,Hdq,Ry/Mw,Ib (66),(v1)
|
|
c5: pextrw Gd,Nq,Ib | vpextrw Gd,Udq,Ib (66),(v1)
|
|
c6: vshufps Vps,Hps,Wps,Ib | vshufpd Vpd,Hpd,Wpd,Ib (66)
|
|
c7: Grp9 (1A)
|
|
c8: BSWAP RAX/EAX/R8/R8D
|
|
c9: BSWAP RCX/ECX/R9/R9D
|
|
ca: BSWAP RDX/EDX/R10/R10D
|
|
cb: BSWAP RBX/EBX/R11/R11D
|
|
cc: BSWAP RSP/ESP/R12/R12D
|
|
cd: BSWAP RBP/EBP/R13/R13D
|
|
ce: BSWAP RSI/ESI/R14/R14D
|
|
cf: BSWAP RDI/EDI/R15/R15D
|
|
# 0x0f 0xd0-0xdf
|
|
d0: vaddsubpd Vpd,Hpd,Wpd (66) | vaddsubps Vps,Hps,Wps (F2)
|
|
d1: psrlw Pq,Qq | vpsrlw Vx,Hx,Wx (66),(v1)
|
|
d2: psrld Pq,Qq | vpsrld Vx,Hx,Wx (66),(v1)
|
|
d3: psrlq Pq,Qq | vpsrlq Vx,Hx,Wx (66),(v1)
|
|
d4: paddq Pq,Qq | vpaddq Vx,Hx,Wx (66),(v1)
|
|
d5: pmullw Pq,Qq | vpmullw Vx,Hx,Wx (66),(v1)
|
|
d6: vmovq Wq,Vq (66),(v1) | movq2dq Vdq,Nq (F3) | movdq2q Pq,Uq (F2)
|
|
d7: pmovmskb Gd,Nq | vpmovmskb Gd,Ux (66),(v1)
|
|
d8: psubusb Pq,Qq | vpsubusb Vx,Hx,Wx (66),(v1)
|
|
d9: psubusw Pq,Qq | vpsubusw Vx,Hx,Wx (66),(v1)
|
|
da: pminub Pq,Qq | vpminub Vx,Hx,Wx (66),(v1)
|
|
db: pand Pq,Qq | vpand Vx,Hx,Wx (66),(v1)
|
|
dc: paddusb Pq,Qq | vpaddusb Vx,Hx,Wx (66),(v1)
|
|
dd: paddusw Pq,Qq | vpaddusw Vx,Hx,Wx (66),(v1)
|
|
de: pmaxub Pq,Qq | vpmaxub Vx,Hx,Wx (66),(v1)
|
|
df: pandn Pq,Qq | vpandn Vx,Hx,Wx (66),(v1)
|
|
# 0x0f 0xe0-0xef
|
|
e0: pavgb Pq,Qq | vpavgb Vx,Hx,Wx (66),(v1)
|
|
e1: psraw Pq,Qq | vpsraw Vx,Hx,Wx (66),(v1)
|
|
e2: psrad Pq,Qq | vpsrad Vx,Hx,Wx (66),(v1)
|
|
e3: pavgw Pq,Qq | vpavgw Vx,Hx,Wx (66),(v1)
|
|
e4: pmulhuw Pq,Qq | vpmulhuw Vx,Hx,Wx (66),(v1)
|
|
e5: pmulhw Pq,Qq | vpmulhw Vx,Hx,Wx (66),(v1)
|
|
e6: vcvttpd2dq Vx,Wpd (66) | vcvtdq2pd Vx,Wdq (F3) | vcvtpd2dq Vx,Wpd (F2)
|
|
e7: movntq Mq,Pq | vmovntdq Mx,Vx (66)
|
|
e8: psubsb Pq,Qq | vpsubsb Vx,Hx,Wx (66),(v1)
|
|
e9: psubsw Pq,Qq | vpsubsw Vx,Hx,Wx (66),(v1)
|
|
ea: pminsw Pq,Qq | vpminsw Vx,Hx,Wx (66),(v1)
|
|
eb: por Pq,Qq | vpor Vx,Hx,Wx (66),(v1)
|
|
ec: paddsb Pq,Qq | vpaddsb Vx,Hx,Wx (66),(v1)
|
|
ed: paddsw Pq,Qq | vpaddsw Vx,Hx,Wx (66),(v1)
|
|
ee: pmaxsw Pq,Qq | vpmaxsw Vx,Hx,Wx (66),(v1)
|
|
ef: pxor Pq,Qq | vpxor Vx,Hx,Wx (66),(v1)
|
|
# 0x0f 0xf0-0xff
|
|
f0: vlddqu Vx,Mx (F2)
|
|
f1: psllw Pq,Qq | vpsllw Vx,Hx,Wx (66),(v1)
|
|
f2: pslld Pq,Qq | vpslld Vx,Hx,Wx (66),(v1)
|
|
f3: psllq Pq,Qq | vpsllq Vx,Hx,Wx (66),(v1)
|
|
f4: pmuludq Pq,Qq | vpmuludq Vx,Hx,Wx (66),(v1)
|
|
f5: pmaddwd Pq,Qq | vpmaddwd Vx,Hx,Wx (66),(v1)
|
|
f6: psadbw Pq,Qq | vpsadbw Vx,Hx,Wx (66),(v1)
|
|
f7: maskmovq Pq,Nq | vmaskmovdqu Vx,Ux (66),(v1)
|
|
f8: psubb Pq,Qq | vpsubb Vx,Hx,Wx (66),(v1)
|
|
f9: psubw Pq,Qq | vpsubw Vx,Hx,Wx (66),(v1)
|
|
fa: psubd Pq,Qq | vpsubd Vx,Hx,Wx (66),(v1)
|
|
fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),(v1)
|
|
fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1)
|
|
fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1)
|
|
fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1)
|
|
ff:
|
|
EndTable
|
|
|
|
Table: 3-byte opcode 1 (0x0f 0x38)
|
|
Referrer: 3-byte escape 1
|
|
AVXcode: 2
|
|
# 0x0f 0x38 0x00-0x0f
|
|
00: pshufb Pq,Qq | vpshufb Vx,Hx,Wx (66),(v1)
|
|
01: phaddw Pq,Qq | vphaddw Vx,Hx,Wx (66),(v1)
|
|
02: phaddd Pq,Qq | vphaddd Vx,Hx,Wx (66),(v1)
|
|
03: phaddsw Pq,Qq | vphaddsw Vx,Hx,Wx (66),(v1)
|
|
04: pmaddubsw Pq,Qq | vpmaddubsw Vx,Hx,Wx (66),(v1)
|
|
05: phsubw Pq,Qq | vphsubw Vx,Hx,Wx (66),(v1)
|
|
06: phsubd Pq,Qq | vphsubd Vx,Hx,Wx (66),(v1)
|
|
07: phsubsw Pq,Qq | vphsubsw Vx,Hx,Wx (66),(v1)
|
|
08: psignb Pq,Qq | vpsignb Vx,Hx,Wx (66),(v1)
|
|
09: psignw Pq,Qq | vpsignw Vx,Hx,Wx (66),(v1)
|
|
0a: psignd Pq,Qq | vpsignd Vx,Hx,Wx (66),(v1)
|
|
0b: pmulhrsw Pq,Qq | vpmulhrsw Vx,Hx,Wx (66),(v1)
|
|
0c: vpermilps Vx,Hx,Wx (66),(v)
|
|
0d: vpermilpd Vx,Hx,Wx (66),(v)
|
|
0e: vtestps Vx,Wx (66),(v)
|
|
0f: vtestpd Vx,Wx (66),(v)
|
|
# 0x0f 0x38 0x10-0x1f
|
|
10: pblendvb Vdq,Wdq (66)
|
|
11:
|
|
12:
|
|
13: vcvtph2ps Vx,Wx,Ib (66),(v)
|
|
14: blendvps Vdq,Wdq (66)
|
|
15: blendvpd Vdq,Wdq (66)
|
|
16: vpermps Vqq,Hqq,Wqq (66),(v)
|
|
17: vptest Vx,Wx (66)
|
|
18: vbroadcastss Vx,Wd (66),(v)
|
|
19: vbroadcastsd Vqq,Wq (66),(v)
|
|
1a: vbroadcastf128 Vqq,Mdq (66),(v)
|
|
1b:
|
|
1c: pabsb Pq,Qq | vpabsb Vx,Wx (66),(v1)
|
|
1d: pabsw Pq,Qq | vpabsw Vx,Wx (66),(v1)
|
|
1e: pabsd Pq,Qq | vpabsd Vx,Wx (66),(v1)
|
|
1f:
|
|
# 0x0f 0x38 0x20-0x2f
|
|
20: vpmovsxbw Vx,Ux/Mq (66),(v1)
|
|
21: vpmovsxbd Vx,Ux/Md (66),(v1)
|
|
22: vpmovsxbq Vx,Ux/Mw (66),(v1)
|
|
23: vpmovsxwd Vx,Ux/Mq (66),(v1)
|
|
24: vpmovsxwq Vx,Ux/Md (66),(v1)
|
|
25: vpmovsxdq Vx,Ux/Mq (66),(v1)
|
|
26:
|
|
27:
|
|
28: vpmuldq Vx,Hx,Wx (66),(v1)
|
|
29: vpcmpeqq Vx,Hx,Wx (66),(v1)
|
|
2a: vmovntdqa Vx,Mx (66),(v1)
|
|
2b: vpackusdw Vx,Hx,Wx (66),(v1)
|
|
2c: vmaskmovps Vx,Hx,Mx (66),(v)
|
|
2d: vmaskmovpd Vx,Hx,Mx (66),(v)
|
|
2e: vmaskmovps Mx,Hx,Vx (66),(v)
|
|
2f: vmaskmovpd Mx,Hx,Vx (66),(v)
|
|
# 0x0f 0x38 0x30-0x3f
|
|
30: vpmovzxbw Vx,Ux/Mq (66),(v1)
|
|
31: vpmovzxbd Vx,Ux/Md (66),(v1)
|
|
32: vpmovzxbq Vx,Ux/Mw (66),(v1)
|
|
33: vpmovzxwd Vx,Ux/Mq (66),(v1)
|
|
34: vpmovzxwq Vx,Ux/Md (66),(v1)
|
|
35: vpmovzxdq Vx,Ux/Mq (66),(v1)
|
|
36: vpermd Vqq,Hqq,Wqq (66),(v)
|
|
37: vpcmpgtq Vx,Hx,Wx (66),(v1)
|
|
38: vpminsb Vx,Hx,Wx (66),(v1)
|
|
39: vpminsd Vx,Hx,Wx (66),(v1)
|
|
3a: vpminuw Vx,Hx,Wx (66),(v1)
|
|
3b: vpminud Vx,Hx,Wx (66),(v1)
|
|
3c: vpmaxsb Vx,Hx,Wx (66),(v1)
|
|
3d: vpmaxsd Vx,Hx,Wx (66),(v1)
|
|
3e: vpmaxuw Vx,Hx,Wx (66),(v1)
|
|
3f: vpmaxud Vx,Hx,Wx (66),(v1)
|
|
# 0x0f 0x38 0x40-0x8f
|
|
40: vpmulld Vx,Hx,Wx (66),(v1)
|
|
41: vphminposuw Vdq,Wdq (66),(v1)
|
|
42:
|
|
43:
|
|
44:
|
|
45: vpsrlvd/q Vx,Hx,Wx (66),(v)
|
|
46: vpsravd Vx,Hx,Wx (66),(v)
|
|
47: vpsllvd/q Vx,Hx,Wx (66),(v)
|
|
# Skip 0x48-0x57
|
|
58: vpbroadcastd Vx,Wx (66),(v)
|
|
59: vpbroadcastq Vx,Wx (66),(v)
|
|
5a: vbroadcasti128 Vqq,Mdq (66),(v)
|
|
# Skip 0x5b-0x77
|
|
78: vpbroadcastb Vx,Wx (66),(v)
|
|
79: vpbroadcastw Vx,Wx (66),(v)
|
|
# Skip 0x7a-0x7f
|
|
80: INVEPT Gy,Mdq (66)
|
|
81: INVPID Gy,Mdq (66)
|
|
82: INVPCID Gy,Mdq (66)
|
|
8c: vpmaskmovd/q Vx,Hx,Mx (66),(v)
|
|
8e: vpmaskmovd/q Mx,Vx,Hx (66),(v)
|
|
# 0x0f 0x38 0x90-0xbf (FMA)
|
|
90: vgatherdd/q Vx,Hx,Wx (66),(v)
|
|
91: vgatherqd/q Vx,Hx,Wx (66),(v)
|
|
92: vgatherdps/d Vx,Hx,Wx (66),(v)
|
|
93: vgatherqps/d Vx,Hx,Wx (66),(v)
|
|
94:
|
|
95:
|
|
96: vfmaddsub132ps/d Vx,Hx,Wx (66),(v)
|
|
97: vfmsubadd132ps/d Vx,Hx,Wx (66),(v)
|
|
98: vfmadd132ps/d Vx,Hx,Wx (66),(v)
|
|
99: vfmadd132ss/d Vx,Hx,Wx (66),(v),(v1)
|
|
9a: vfmsub132ps/d Vx,Hx,Wx (66),(v)
|
|
9b: vfmsub132ss/d Vx,Hx,Wx (66),(v),(v1)
|
|
9c: vfnmadd132ps/d Vx,Hx,Wx (66),(v)
|
|
9d: vfnmadd132ss/d Vx,Hx,Wx (66),(v),(v1)
|
|
9e: vfnmsub132ps/d Vx,Hx,Wx (66),(v)
|
|
9f: vfnmsub132ss/d Vx,Hx,Wx (66),(v),(v1)
|
|
a6: vfmaddsub213ps/d Vx,Hx,Wx (66),(v)
|
|
a7: vfmsubadd213ps/d Vx,Hx,Wx (66),(v)
|
|
a8: vfmadd213ps/d Vx,Hx,Wx (66),(v)
|
|
a9: vfmadd213ss/d Vx,Hx,Wx (66),(v),(v1)
|
|
aa: vfmsub213ps/d Vx,Hx,Wx (66),(v)
|
|
ab: vfmsub213ss/d Vx,Hx,Wx (66),(v),(v1)
|
|
ac: vfnmadd213ps/d Vx,Hx,Wx (66),(v)
|
|
ad: vfnmadd213ss/d Vx,Hx,Wx (66),(v),(v1)
|
|
ae: vfnmsub213ps/d Vx,Hx,Wx (66),(v)
|
|
af: vfnmsub213ss/d Vx,Hx,Wx (66),(v),(v1)
|
|
b6: vfmaddsub231ps/d Vx,Hx,Wx (66),(v)
|
|
b7: vfmsubadd231ps/d Vx,Hx,Wx (66),(v)
|
|
b8: vfmadd231ps/d Vx,Hx,Wx (66),(v)
|
|
b9: vfmadd231ss/d Vx,Hx,Wx (66),(v),(v1)
|
|
ba: vfmsub231ps/d Vx,Hx,Wx (66),(v)
|
|
bb: vfmsub231ss/d Vx,Hx,Wx (66),(v),(v1)
|
|
bc: vfnmadd231ps/d Vx,Hx,Wx (66),(v)
|
|
bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1)
|
|
be: vfnmsub231ps/d Vx,Hx,Wx (66),(v)
|
|
bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1)
|
|
# 0x0f 0x38 0xc0-0xff
|
|
db: VAESIMC Vdq,Wdq (66),(v1)
|
|
dc: VAESENC Vdq,Hdq,Wdq (66),(v1)
|
|
dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1)
|
|
de: VAESDEC Vdq,Hdq,Wdq (66),(v1)
|
|
df: VAESDECLAST Vdq,Hdq,Wdq (66),(v1)
|
|
f0: MOVBE Gy,My | MOVBE Gw,Mw (66) | CRC32 Gd,Eb (F2) | CRC32 Gd,Eb (66&F2)
|
|
f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) | CRC32 Gd,Ew (66&F2)
|
|
f2: ANDN Gy,By,Ey (v)
|
|
f3: Grp17 (1A)
|
|
f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v)
|
|
f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v)
|
|
f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v)
|
|
EndTable
|
|
|
|
Table: 3-byte opcode 2 (0x0f 0x3a)
|
|
Referrer: 3-byte escape 2
|
|
AVXcode: 3
|
|
# 0x0f 0x3a 0x00-0xff
|
|
00: vpermq Vqq,Wqq,Ib (66),(v)
|
|
01: vpermpd Vqq,Wqq,Ib (66),(v)
|
|
02: vpblendd Vx,Hx,Wx,Ib (66),(v)
|
|
03:
|
|
04: vpermilps Vx,Wx,Ib (66),(v)
|
|
05: vpermilpd Vx,Wx,Ib (66),(v)
|
|
06: vperm2f128 Vqq,Hqq,Wqq,Ib (66),(v)
|
|
07:
|
|
08: vroundps Vx,Wx,Ib (66)
|
|
09: vroundpd Vx,Wx,Ib (66)
|
|
0a: vroundss Vss,Wss,Ib (66),(v1)
|
|
0b: vroundsd Vsd,Wsd,Ib (66),(v1)
|
|
0c: vblendps Vx,Hx,Wx,Ib (66)
|
|
0d: vblendpd Vx,Hx,Wx,Ib (66)
|
|
0e: vpblendw Vx,Hx,Wx,Ib (66),(v1)
|
|
0f: palignr Pq,Qq,Ib | vpalignr Vx,Hx,Wx,Ib (66),(v1)
|
|
14: vpextrb Rd/Mb,Vdq,Ib (66),(v1)
|
|
15: vpextrw Rd/Mw,Vdq,Ib (66),(v1)
|
|
16: vpextrd/q Ey,Vdq,Ib (66),(v1)
|
|
17: vextractps Ed,Vdq,Ib (66),(v1)
|
|
18: vinsertf128 Vqq,Hqq,Wqq,Ib (66),(v)
|
|
19: vextractf128 Wdq,Vqq,Ib (66),(v)
|
|
1d: vcvtps2ph Wx,Vx,Ib (66),(v)
|
|
20: vpinsrb Vdq,Hdq,Ry/Mb,Ib (66),(v1)
|
|
21: vinsertps Vdq,Hdq,Udq/Md,Ib (66),(v1)
|
|
22: vpinsrd/q Vdq,Hdq,Ey,Ib (66),(v1)
|
|
38: vinserti128 Vqq,Hqq,Wqq,Ib (66),(v)
|
|
39: vextracti128 Wdq,Vqq,Ib (66),(v)
|
|
40: vdpps Vx,Hx,Wx,Ib (66)
|
|
41: vdppd Vdq,Hdq,Wdq,Ib (66),(v1)
|
|
42: vmpsadbw Vx,Hx,Wx,Ib (66),(v1)
|
|
44: vpclmulqdq Vdq,Hdq,Wdq,Ib (66),(v1)
|
|
46: vperm2i128 Vqq,Hqq,Wqq,Ib (66),(v)
|
|
4a: vblendvps Vx,Hx,Wx,Lx (66),(v)
|
|
4b: vblendvpd Vx,Hx,Wx,Lx (66),(v)
|
|
4c: vpblendvb Vx,Hx,Wx,Lx (66),(v1)
|
|
60: vpcmpestrm Vdq,Wdq,Ib (66),(v1)
|
|
61: vpcmpestri Vdq,Wdq,Ib (66),(v1)
|
|
62: vpcmpistrm Vdq,Wdq,Ib (66),(v1)
|
|
63: vpcmpistri Vdq,Wdq,Ib (66),(v1)
|
|
df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1)
|
|
f0: RORX Gy,Ey,Ib (F2),(v)
|
|
EndTable
|
|
|
|
GrpTable: Grp1
|
|
0: ADD
|
|
1: OR
|
|
2: ADC
|
|
3: SBB
|
|
4: AND
|
|
5: SUB
|
|
6: XOR
|
|
7: CMP
|
|
EndTable
|
|
|
|
GrpTable: Grp1A
|
|
0: POP
|
|
EndTable
|
|
|
|
GrpTable: Grp2
|
|
0: ROL
|
|
1: ROR
|
|
2: RCL
|
|
3: RCR
|
|
4: SHL/SAL
|
|
5: SHR
|
|
6:
|
|
7: SAR
|
|
EndTable
|
|
|
|
GrpTable: Grp3_1
|
|
0: TEST Eb,Ib
|
|
1:
|
|
2: NOT Eb
|
|
3: NEG Eb
|
|
4: MUL AL,Eb
|
|
5: IMUL AL,Eb
|
|
6: DIV AL,Eb
|
|
7: IDIV AL,Eb
|
|
EndTable
|
|
|
|
GrpTable: Grp3_2
|
|
0: TEST Ev,Iz
|
|
1:
|
|
2: NOT Ev
|
|
3: NEG Ev
|
|
4: MUL rAX,Ev
|
|
5: IMUL rAX,Ev
|
|
6: DIV rAX,Ev
|
|
7: IDIV rAX,Ev
|
|
EndTable
|
|
|
|
GrpTable: Grp4
|
|
0: INC Eb
|
|
1: DEC Eb
|
|
EndTable
|
|
|
|
GrpTable: Grp5
|
|
0: INC Ev
|
|
1: DEC Ev
|
|
# Note: "forced64" is Intel CPU behavior (see comment about CALL insn).
|
|
2: CALLN Ev (f64)
|
|
3: CALLF Ep
|
|
4: JMPN Ev (f64)
|
|
5: JMPF Mp
|
|
6: PUSH Ev (d64)
|
|
7:
|
|
EndTable
|
|
|
|
GrpTable: Grp6
|
|
0: SLDT Rv/Mw
|
|
1: STR Rv/Mw
|
|
2: LLDT Ew
|
|
3: LTR Ew
|
|
4: VERR Ew
|
|
5: VERW Ew
|
|
EndTable
|
|
|
|
GrpTable: Grp7
|
|
0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B)
|
|
1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B)
|
|
2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B)
|
|
3: LIDT Ms
|
|
4: SMSW Mw/Rv
|
|
5:
|
|
6: LMSW Ew
|
|
7: INVLPG Mb | SWAPGS (o64),(000),(11B) | RDTSCP (001),(11B)
|
|
EndTable
|
|
|
|
GrpTable: Grp8
|
|
4: BT
|
|
5: BTS
|
|
6: BTR
|
|
7: BTC
|
|
EndTable
|
|
|
|
GrpTable: Grp9
|
|
1: CMPXCHG8B/16B Mq/Mdq
|
|
6: VMPTRLD Mq | VMCLEAR Mq (66) | VMXON Mq (F3) | RDRAND Rv (11B)
|
|
7: VMPTRST Mq | VMPTRST Mq (F3) | RDSEED Rv (11B)
|
|
EndTable
|
|
|
|
GrpTable: Grp10
|
|
EndTable
|
|
|
|
# Grp11A and Grp11B are expressed as Grp11 in Intel SDM
|
|
GrpTable: Grp11A
|
|
0: MOV Eb,Ib
|
|
7: XABORT Ib (000),(11B)
|
|
EndTable
|
|
|
|
GrpTable: Grp11B
|
|
0: MOV Eb,Iz
|
|
7: XBEGIN Jz (000),(11B)
|
|
EndTable
|
|
|
|
GrpTable: Grp12
|
|
2: psrlw Nq,Ib (11B) | vpsrlw Hx,Ux,Ib (66),(11B),(v1)
|
|
4: psraw Nq,Ib (11B) | vpsraw Hx,Ux,Ib (66),(11B),(v1)
|
|
6: psllw Nq,Ib (11B) | vpsllw Hx,Ux,Ib (66),(11B),(v1)
|
|
EndTable
|
|
|
|
GrpTable: Grp13
|
|
2: psrld Nq,Ib (11B) | vpsrld Hx,Ux,Ib (66),(11B),(v1)
|
|
4: psrad Nq,Ib (11B) | vpsrad Hx,Ux,Ib (66),(11B),(v1)
|
|
6: pslld Nq,Ib (11B) | vpslld Hx,Ux,Ib (66),(11B),(v1)
|
|
EndTable
|
|
|
|
GrpTable: Grp14
|
|
2: psrlq Nq,Ib (11B) | vpsrlq Hx,Ux,Ib (66),(11B),(v1)
|
|
3: vpsrldq Hx,Ux,Ib (66),(11B),(v1)
|
|
6: psllq Nq,Ib (11B) | vpsllq Hx,Ux,Ib (66),(11B),(v1)
|
|
7: vpslldq Hx,Ux,Ib (66),(11B),(v1)
|
|
EndTable
|
|
|
|
GrpTable: Grp15
|
|
0: fxsave | RDFSBASE Ry (F3),(11B)
|
|
1: fxstor | RDGSBASE Ry (F3),(11B)
|
|
2: vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B)
|
|
3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
|
|
4: XSAVE
|
|
5: XRSTOR | lfence (11B)
|
|
6: XSAVEOPT | mfence (11B)
|
|
7: clflush | sfence (11B)
|
|
EndTable
|
|
|
|
GrpTable: Grp16
|
|
0: prefetch NTA
|
|
1: prefetch T0
|
|
2: prefetch T1
|
|
3: prefetch T2
|
|
EndTable
|
|
|
|
GrpTable: Grp17
|
|
1: BLSR By,Ey (v)
|
|
2: BLSMSK By,Ey (v)
|
|
3: BLSI By,Ey (v)
|
|
EndTable
|
|
|
|
# AMD's Prefetch Group
|
|
GrpTable: GrpP
|
|
0: PREFETCH
|
|
1: PREFETCHW
|
|
EndTable
|
|
|
|
GrpTable: GrpPDLK
|
|
0: MONTMUL
|
|
1: XSHA1
|
|
2: XSHA2
|
|
EndTable
|
|
|
|
GrpTable: GrpRNG
|
|
0: xstore-rng
|
|
1: xcrypt-ecb
|
|
2: xcrypt-cbc
|
|
4: xcrypt-cfb
|
|
5: xcrypt-ofb
|
|
EndTable
|