984 строки
27 KiB
C
984 строки
27 KiB
C
/*
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* pata_it821x.c - IT821x PATA for new ATA layer
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* (C) 2005 Red Hat Inc
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* Alan Cox <alan@lxorguk.ukuu.org.uk>
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* (C) 2007 Bartlomiej Zolnierkiewicz
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*
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* based upon
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*
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* it821x.c
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*
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* linux/drivers/ide/pci/it821x.c Version 0.09 December 2004
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*
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* Copyright (C) 2004 Red Hat
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*
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* May be copied or modified under the terms of the GNU General Public License
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* Based in part on the ITE vendor provided SCSI driver.
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*
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* Documentation available from IT8212F_V04.pdf
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* http://www.ite.com.tw/EN/products_more.aspx?CategoryID=3&ID=5,91
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* Some other documents are NDA.
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*
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* The ITE8212 isn't exactly a standard IDE controller. It has two
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* modes. In pass through mode then it is an IDE controller. In its smart
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* mode its actually quite a capable hardware raid controller disguised
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* as an IDE controller. Smart mode only understands DMA read/write and
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* identify, none of the fancier commands apply. The IT8211 is identical
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* in other respects but lacks the raid mode.
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*
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* Errata:
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* o Rev 0x10 also requires master/slave hold the same DMA timings and
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* cannot do ATAPI MWDMA.
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* o The identify data for raid volumes lacks CHS info (technically ok)
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* but also fails to set the LBA28 and other bits. We fix these in
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* the IDE probe quirk code.
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* o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
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* raid then the controller firmware dies
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* o Smart mode without RAID doesn't clear all the necessary identify
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* bits to reduce the command set to the one used
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*
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* This has a few impacts on the driver
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* - In pass through mode we do all the work you would expect
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* - In smart mode the clocking set up is done by the controller generally
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* but we must watch the other limits and filter.
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* - There are a few extra vendor commands that actually talk to the
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* controller but only work PIO with no IRQ.
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*
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* Vendor areas of the identify block in smart mode are used for the
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* timing and policy set up. Each HDD in raid mode also has a serial
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* block on the disk. The hardware extra commands are get/set chip status,
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* rebuild, get rebuild status.
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*
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* In Linux the driver supports pass through mode as if the device was
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* just another IDE controller. If the smart mode is running then
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* volumes are managed by the controller firmware and each IDE "disk"
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* is a raid volume. Even more cute - the controller can do automated
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* hotplug and rebuild.
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*
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* The pass through controller itself is a little demented. It has a
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* flaw that it has a single set of PIO/MWDMA timings per channel so
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* non UDMA devices restrict each others performance. It also has a
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* single clock source per channel so mixed UDMA100/133 performance
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* isn't perfect and we have to pick a clock. Thankfully none of this
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* matters in smart mode. ATAPI DMA is not currently supported.
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*
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* It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
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*
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* TODO
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* - ATAPI and other speed filtering
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* - RAID configuration ioctls
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_it821x"
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#define DRV_VERSION "0.4.2"
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struct it821x_dev
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{
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unsigned int smart:1, /* Are we in smart raid mode */
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timing10:1; /* Rev 0x10 */
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u8 clock_mode; /* 0, ATA_50 or ATA_66 */
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u8 want[2][2]; /* Mode/Pri log for master slave */
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/* We need these for switching the clock when DMA goes on/off
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The high byte is the 66Mhz timing */
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u16 pio[2]; /* Cached PIO values */
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u16 mwdma[2]; /* Cached MWDMA values */
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u16 udma[2]; /* Cached UDMA values (per drive) */
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u16 last_device; /* Master or slave loaded ? */
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};
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#define ATA_66 0
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#define ATA_50 1
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#define ATA_ANY 2
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#define UDMA_OFF 0
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#define MWDMA_OFF 0
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/*
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* We allow users to force the card into non raid mode without
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* flashing the alternative BIOS. This is also necessary right now
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* for embedded platforms that cannot run a PC BIOS but are using this
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* device.
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*/
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static int it8212_noraid;
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/**
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* it821x_program - program the PIO/MWDMA registers
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* @ap: ATA port
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* @adev: Device to program
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* @timing: Timing value (66Mhz in top 8bits, 50 in the low 8)
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*
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* Program the PIO/MWDMA timing for this channel according to the
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* current clock. These share the same register so are managed by
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* the DMA start/stop sequence as with the old driver.
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*/
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static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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struct it821x_dev *itdev = ap->private_data;
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int channel = ap->port_no;
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u8 conf;
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/* Program PIO/MWDMA timing bits */
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if (itdev->clock_mode == ATA_66)
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conf = timing >> 8;
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else
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conf = timing & 0xFF;
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pci_write_config_byte(pdev, 0x54 + 4 * channel, conf);
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}
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/**
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* it821x_program_udma - program the UDMA registers
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* @ap: ATA port
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* @adev: ATA device to update
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* @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz
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*
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* Program the UDMA timing for this drive according to the
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* current clock. Handles the dual clocks and also knows about
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* the errata on the 0x10 revision. The UDMA errata is partly handled
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* here and partly in start_dma.
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*/
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static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing)
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{
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struct it821x_dev *itdev = ap->private_data;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int channel = ap->port_no;
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int unit = adev->devno;
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u8 conf;
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/* Program UDMA timing bits */
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if (itdev->clock_mode == ATA_66)
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conf = timing >> 8;
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else
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conf = timing & 0xFF;
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if (itdev->timing10 == 0)
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pci_write_config_byte(pdev, 0x56 + 4 * channel + unit, conf);
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else {
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/* Early revision must be programmed for both together */
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pci_write_config_byte(pdev, 0x56 + 4 * channel, conf);
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pci_write_config_byte(pdev, 0x56 + 4 * channel + 1, conf);
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}
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}
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/**
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* it821x_clock_strategy
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* @ap: ATA interface
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* @adev: ATA device being updated
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*
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* Select between the 50 and 66Mhz base clocks to get the best
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* results for this interface.
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*/
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static void it821x_clock_strategy(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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struct it821x_dev *itdev = ap->private_data;
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u8 unit = adev->devno;
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struct ata_device *pair = ata_dev_pair(adev);
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int clock, altclock;
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u8 v;
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int sel = 0;
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/* Look for the most wanted clocking */
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if (itdev->want[0][0] > itdev->want[1][0]) {
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clock = itdev->want[0][1];
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altclock = itdev->want[1][1];
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} else {
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clock = itdev->want[1][1];
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altclock = itdev->want[0][1];
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}
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/* Master doesn't care does the slave ? */
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if (clock == ATA_ANY)
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clock = altclock;
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/* Nobody cares - keep the same clock */
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if (clock == ATA_ANY)
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return;
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/* No change */
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if (clock == itdev->clock_mode)
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return;
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/* Load this into the controller */
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if (clock == ATA_66)
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itdev->clock_mode = ATA_66;
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else {
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itdev->clock_mode = ATA_50;
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sel = 1;
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}
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pci_read_config_byte(pdev, 0x50, &v);
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v &= ~(1 << (1 + ap->port_no));
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v |= sel << (1 + ap->port_no);
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pci_write_config_byte(pdev, 0x50, v);
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/*
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* Reprogram the UDMA/PIO of the pair drive for the switch
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* MWDMA will be dealt with by the dma switcher
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*/
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if (pair && itdev->udma[1-unit] != UDMA_OFF) {
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it821x_program_udma(ap, pair, itdev->udma[1-unit]);
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it821x_program(ap, pair, itdev->pio[1-unit]);
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}
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/*
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* Reprogram the UDMA/PIO of our drive for the switch.
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* MWDMA will be dealt with by the dma switcher
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*/
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if (itdev->udma[unit] != UDMA_OFF) {
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it821x_program_udma(ap, adev, itdev->udma[unit]);
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it821x_program(ap, adev, itdev->pio[unit]);
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}
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}
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/**
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* it821x_passthru_set_piomode - set PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Configure for PIO mode. This is complicated as the register is
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* shared by PIO and MWDMA and for both channels.
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*/
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static void it821x_passthru_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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/* Spec says 89 ref driver uses 88 */
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static const u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
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static const u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
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struct it821x_dev *itdev = ap->private_data;
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int unit = adev->devno;
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int mode_wanted = adev->pio_mode - XFER_PIO_0;
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/* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
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itdev->want[unit][1] = pio_want[mode_wanted];
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itdev->want[unit][0] = 1; /* PIO is lowest priority */
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itdev->pio[unit] = pio[mode_wanted];
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it821x_clock_strategy(ap, adev);
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it821x_program(ap, adev, itdev->pio[unit]);
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}
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/**
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* it821x_passthru_set_dmamode - set initial DMA mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Set up the DMA modes. The actions taken depend heavily on the mode
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* to use. If UDMA is used as is hopefully the usual case then the
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* timing register is private and we need only consider the clock. If
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* we are using MWDMA then we have to manage the setting ourself as
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* we switch devices and mode.
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*/
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static void it821x_passthru_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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static const u16 dma[] = { 0x8866, 0x3222, 0x3121 };
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static const u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
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static const u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
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static const u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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struct it821x_dev *itdev = ap->private_data;
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int channel = ap->port_no;
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int unit = adev->devno;
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u8 conf;
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if (adev->dma_mode >= XFER_UDMA_0) {
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int mode_wanted = adev->dma_mode - XFER_UDMA_0;
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itdev->want[unit][1] = udma_want[mode_wanted];
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itdev->want[unit][0] = 3; /* UDMA is high priority */
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itdev->mwdma[unit] = MWDMA_OFF;
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itdev->udma[unit] = udma[mode_wanted];
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if (mode_wanted >= 5)
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itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
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/* UDMA on. Again revision 0x10 must do the pair */
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pci_read_config_byte(pdev, 0x50, &conf);
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if (itdev->timing10)
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conf &= channel ? 0x9F: 0xE7;
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else
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conf &= ~ (1 << (3 + 2 * channel + unit));
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pci_write_config_byte(pdev, 0x50, conf);
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it821x_clock_strategy(ap, adev);
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it821x_program_udma(ap, adev, itdev->udma[unit]);
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} else {
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int mode_wanted = adev->dma_mode - XFER_MW_DMA_0;
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itdev->want[unit][1] = mwdma_want[mode_wanted];
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itdev->want[unit][0] = 2; /* MWDMA is low priority */
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itdev->mwdma[unit] = dma[mode_wanted];
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itdev->udma[unit] = UDMA_OFF;
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/* UDMA bits off - Revision 0x10 do them in pairs */
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pci_read_config_byte(pdev, 0x50, &conf);
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if (itdev->timing10)
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conf |= channel ? 0x60: 0x18;
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else
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conf |= 1 << (3 + 2 * channel + unit);
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pci_write_config_byte(pdev, 0x50, conf);
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it821x_clock_strategy(ap, adev);
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}
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}
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/**
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* it821x_passthru_dma_start - DMA start callback
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* @qc: Command in progress
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*
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* Usually drivers set the DMA timing at the point the set_dmamode call
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* is made. IT821x however requires we load new timings on the
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* transitions in some cases.
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*/
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static void it821x_passthru_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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struct it821x_dev *itdev = ap->private_data;
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int unit = adev->devno;
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if (itdev->mwdma[unit] != MWDMA_OFF)
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it821x_program(ap, adev, itdev->mwdma[unit]);
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else if (itdev->udma[unit] != UDMA_OFF && itdev->timing10)
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it821x_program_udma(ap, adev, itdev->udma[unit]);
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ata_bmdma_start(qc);
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}
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/**
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* it821x_passthru_dma_stop - DMA stop callback
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* @qc: ATA command
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*
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* We loaded new timings in dma_start, as a result we need to restore
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* the PIO timings in dma_stop so that the next command issue gets the
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* right clock values.
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*/
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static void it821x_passthru_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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struct it821x_dev *itdev = ap->private_data;
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int unit = adev->devno;
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ata_bmdma_stop(qc);
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if (itdev->mwdma[unit] != MWDMA_OFF)
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it821x_program(ap, adev, itdev->pio[unit]);
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}
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/**
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* it821x_passthru_dev_select - Select master/slave
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* @ap: ATA port
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* @device: Device number (not pointer)
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*
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* Device selection hook. If necessary perform clock switching
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*/
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static void it821x_passthru_dev_select(struct ata_port *ap,
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unsigned int device)
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{
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struct it821x_dev *itdev = ap->private_data;
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if (itdev && device != itdev->last_device) {
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struct ata_device *adev = &ap->link.device[device];
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it821x_program(ap, adev, itdev->pio[adev->devno]);
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itdev->last_device = device;
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}
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ata_sff_dev_select(ap, device);
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}
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/**
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* it821x_smart_qc_issue - wrap qc issue prot
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* @qc: command
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*
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* Wrap the command issue sequence for the IT821x. We need to
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* perform out own device selection timing loads before the
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* usual happenings kick off
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*/
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static unsigned int it821x_smart_qc_issue(struct ata_queued_cmd *qc)
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{
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switch(qc->tf.command)
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{
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/* Commands the firmware supports */
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case ATA_CMD_READ:
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case ATA_CMD_READ_EXT:
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case ATA_CMD_WRITE:
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case ATA_CMD_WRITE_EXT:
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case ATA_CMD_PIO_READ:
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case ATA_CMD_PIO_READ_EXT:
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case ATA_CMD_PIO_WRITE:
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case ATA_CMD_PIO_WRITE_EXT:
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case ATA_CMD_READ_MULTI:
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case ATA_CMD_READ_MULTI_EXT:
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case ATA_CMD_WRITE_MULTI:
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case ATA_CMD_WRITE_MULTI_EXT:
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case ATA_CMD_ID_ATA:
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case ATA_CMD_INIT_DEV_PARAMS:
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case 0xFC: /* Internal 'report rebuild state' */
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/* Arguably should just no-op this one */
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case ATA_CMD_SET_FEATURES:
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return ata_bmdma_qc_issue(qc);
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}
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printk(KERN_DEBUG "it821x: can't process command 0x%02X\n", qc->tf.command);
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return AC_ERR_DEV;
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}
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/**
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* it821x_passthru_qc_issue - wrap qc issue prot
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* @qc: command
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*
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* Wrap the command issue sequence for the IT821x. We need to
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* perform out own device selection timing loads before the
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* usual happenings kick off
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*/
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static unsigned int it821x_passthru_qc_issue(struct ata_queued_cmd *qc)
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{
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it821x_passthru_dev_select(qc->ap, qc->dev->devno);
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return ata_bmdma_qc_issue(qc);
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}
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/**
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* it821x_smart_set_mode - mode setting
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* @link: interface to set up
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* @unused: device that failed (error only)
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*
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* Use a non standard set_mode function. We don't want to be tuned.
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* The BIOS configured everything. Our job is not to fiddle. We
|
|
* read the dma enabled bits from the PCI configuration of the device
|
|
* and respect them.
|
|
*/
|
|
|
|
static int it821x_smart_set_mode(struct ata_link *link, struct ata_device **unused)
|
|
{
|
|
struct ata_device *dev;
|
|
|
|
ata_for_each_dev(dev, link, ENABLED) {
|
|
/* We don't really care */
|
|
dev->pio_mode = XFER_PIO_0;
|
|
dev->dma_mode = XFER_MW_DMA_0;
|
|
/* We do need the right mode information for DMA or PIO
|
|
and this comes from the current configuration flags */
|
|
if (ata_id_has_dma(dev->id)) {
|
|
ata_dev_info(dev, "configured for DMA\n");
|
|
dev->xfer_mode = XFER_MW_DMA_0;
|
|
dev->xfer_shift = ATA_SHIFT_MWDMA;
|
|
dev->flags &= ~ATA_DFLAG_PIO;
|
|
} else {
|
|
ata_dev_info(dev, "configured for PIO\n");
|
|
dev->xfer_mode = XFER_PIO_0;
|
|
dev->xfer_shift = ATA_SHIFT_PIO;
|
|
dev->flags |= ATA_DFLAG_PIO;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* it821x_dev_config - Called each device identify
|
|
* @adev: Device that has just been identified
|
|
*
|
|
* Perform the initial setup needed for each device that is chip
|
|
* special. In our case we need to lock the sector count to avoid
|
|
* blowing the brains out of the firmware with large LBA48 requests
|
|
*
|
|
*/
|
|
|
|
static void it821x_dev_config(struct ata_device *adev)
|
|
{
|
|
unsigned char model_num[ATA_ID_PROD_LEN + 1];
|
|
|
|
ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
|
|
|
|
if (adev->max_sectors > 255)
|
|
adev->max_sectors = 255;
|
|
|
|
if (strstr(model_num, "Integrated Technology Express")) {
|
|
/* RAID mode */
|
|
ata_dev_info(adev, "%sRAID%d volume",
|
|
adev->id[147] ? "Bootable " : "",
|
|
adev->id[129]);
|
|
if (adev->id[129] != 1)
|
|
pr_cont("(%dK stripe)", adev->id[146]);
|
|
pr_cont("\n");
|
|
}
|
|
/* This is a controller firmware triggered funny, don't
|
|
report the drive faulty! */
|
|
adev->horkage &= ~ATA_HORKAGE_DIAGNOSTIC;
|
|
/* No HPA in 'smart' mode */
|
|
adev->horkage |= ATA_HORKAGE_BROKEN_HPA;
|
|
}
|
|
|
|
/**
|
|
* it821x_read_id - Hack identify data up
|
|
* @adev: device to read
|
|
* @tf: proposed taskfile
|
|
* @id: buffer for returned ident data
|
|
*
|
|
* Query the devices on this firmware driven port and slightly
|
|
* mash the identify data to stop us and common tools trying to
|
|
* use features not firmware supported. The firmware itself does
|
|
* some masking (eg SMART) but not enough.
|
|
*/
|
|
|
|
static unsigned int it821x_read_id(struct ata_device *adev,
|
|
struct ata_taskfile *tf, u16 *id)
|
|
{
|
|
unsigned int err_mask;
|
|
unsigned char model_num[ATA_ID_PROD_LEN + 1];
|
|
|
|
err_mask = ata_do_dev_read_id(adev, tf, id);
|
|
if (err_mask)
|
|
return err_mask;
|
|
ata_id_c_string(id, model_num, ATA_ID_PROD, sizeof(model_num));
|
|
|
|
id[83] &= ~(1 << 12); /* Cache flush is firmware handled */
|
|
id[83] &= ~(1 << 13); /* Ditto for LBA48 flushes */
|
|
id[84] &= ~(1 << 6); /* No FUA */
|
|
id[85] &= ~(1 << 10); /* No HPA */
|
|
id[76] = 0; /* No NCQ/AN etc */
|
|
|
|
if (strstr(model_num, "Integrated Technology Express")) {
|
|
/* Set feature bits the firmware neglects */
|
|
id[49] |= 0x0300; /* LBA, DMA */
|
|
id[83] &= 0x7FFF;
|
|
id[83] |= 0x4400; /* Word 83 is valid and LBA48 */
|
|
id[86] |= 0x0400; /* LBA48 on */
|
|
id[ATA_ID_MAJOR_VER] |= 0x1F;
|
|
/* Clear the serial number because it's different each boot
|
|
which breaks validation on resume */
|
|
memset(&id[ATA_ID_SERNO], 0x20, ATA_ID_SERNO_LEN);
|
|
}
|
|
return err_mask;
|
|
}
|
|
|
|
/**
|
|
* it821x_check_atapi_dma - ATAPI DMA handler
|
|
* @qc: Command we are about to issue
|
|
*
|
|
* Decide if this ATAPI command can be issued by DMA on this
|
|
* controller. Return 0 if it can be.
|
|
*/
|
|
|
|
static int it821x_check_atapi_dma(struct ata_queued_cmd *qc)
|
|
{
|
|
struct ata_port *ap = qc->ap;
|
|
struct it821x_dev *itdev = ap->private_data;
|
|
|
|
/* Only use dma for transfers to/from the media. */
|
|
if (ata_qc_raw_nbytes(qc) < 2048)
|
|
return -EOPNOTSUPP;
|
|
|
|
/* No ATAPI DMA in smart mode */
|
|
if (itdev->smart)
|
|
return -EOPNOTSUPP;
|
|
/* No ATAPI DMA on rev 10 */
|
|
if (itdev->timing10)
|
|
return -EOPNOTSUPP;
|
|
/* Cool */
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* it821x_display_disk - display disk setup
|
|
* @n: Device number
|
|
* @buf: Buffer block from firmware
|
|
*
|
|
* Produce a nice informative display of the device setup as provided
|
|
* by the firmware.
|
|
*/
|
|
|
|
static void it821x_display_disk(int n, u8 *buf)
|
|
{
|
|
unsigned char id[41];
|
|
int mode = 0;
|
|
char *mtype = "";
|
|
char mbuf[8];
|
|
char *cbl = "(40 wire cable)";
|
|
|
|
static const char *types[5] = {
|
|
"RAID0", "RAID1", "RAID 0+1", "JBOD", "DISK"
|
|
};
|
|
|
|
if (buf[52] > 4) /* No Disk */
|
|
return;
|
|
|
|
ata_id_c_string((u16 *)buf, id, 0, 41);
|
|
|
|
if (buf[51]) {
|
|
mode = ffs(buf[51]);
|
|
mtype = "UDMA";
|
|
} else if (buf[49]) {
|
|
mode = ffs(buf[49]);
|
|
mtype = "MWDMA";
|
|
}
|
|
|
|
if (buf[76])
|
|
cbl = "";
|
|
|
|
if (mode)
|
|
snprintf(mbuf, 8, "%5s%d", mtype, mode - 1);
|
|
else
|
|
strcpy(mbuf, "PIO");
|
|
if (buf[52] == 4)
|
|
printk(KERN_INFO "%d: %-6s %-8s %s %s\n",
|
|
n, mbuf, types[buf[52]], id, cbl);
|
|
else
|
|
printk(KERN_INFO "%d: %-6s %-8s Volume: %1d %s %s\n",
|
|
n, mbuf, types[buf[52]], buf[53], id, cbl);
|
|
if (buf[125] < 100)
|
|
printk(KERN_INFO "%d: Rebuilding: %d%%\n", n, buf[125]);
|
|
}
|
|
|
|
/**
|
|
* it821x_firmware_command - issue firmware command
|
|
* @ap: IT821x port to interrogate
|
|
* @cmd: command
|
|
* @len: length
|
|
*
|
|
* Issue firmware commands expecting data back from the controller. We
|
|
* use this to issue commands that do not go via the normal paths. Other
|
|
* commands such as 0xFC can be issued normally.
|
|
*/
|
|
|
|
static u8 *it821x_firmware_command(struct ata_port *ap, u8 cmd, int len)
|
|
{
|
|
u8 status;
|
|
int n = 0;
|
|
u16 *buf = kmalloc(len, GFP_KERNEL);
|
|
if (buf == NULL) {
|
|
printk(KERN_ERR "it821x_firmware_command: Out of memory\n");
|
|
return NULL;
|
|
}
|
|
/* This isn't quite a normal ATA command as we are talking to the
|
|
firmware not the drives */
|
|
ap->ctl |= ATA_NIEN;
|
|
iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
|
|
ata_wait_idle(ap);
|
|
iowrite8(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
|
|
iowrite8(cmd, ap->ioaddr.command_addr);
|
|
udelay(1);
|
|
/* This should be almost immediate but a little paranoia goes a long
|
|
way. */
|
|
while(n++ < 10) {
|
|
status = ioread8(ap->ioaddr.status_addr);
|
|
if (status & ATA_ERR) {
|
|
kfree(buf);
|
|
printk(KERN_ERR "it821x_firmware_command: rejected\n");
|
|
return NULL;
|
|
}
|
|
if (status & ATA_DRQ) {
|
|
ioread16_rep(ap->ioaddr.data_addr, buf, len/2);
|
|
return (u8 *)buf;
|
|
}
|
|
mdelay(1);
|
|
}
|
|
kfree(buf);
|
|
printk(KERN_ERR "it821x_firmware_command: timeout\n");
|
|
return NULL;
|
|
}
|
|
|
|
/**
|
|
* it821x_probe_firmware - firmware reporting/setup
|
|
* @ap: IT821x port being probed
|
|
*
|
|
* Probe the firmware of the controller by issuing firmware command
|
|
* 0xFA and analysing the returned data.
|
|
*/
|
|
|
|
static void it821x_probe_firmware(struct ata_port *ap)
|
|
{
|
|
u8 *buf;
|
|
int i;
|
|
|
|
/* This is a bit ugly as we can't just issue a task file to a device
|
|
as this is controller magic */
|
|
|
|
buf = it821x_firmware_command(ap, 0xFA, 512);
|
|
|
|
if (buf != NULL) {
|
|
printk(KERN_INFO "pata_it821x: Firmware %02X/%02X/%02X%02X\n",
|
|
buf[505],
|
|
buf[506],
|
|
buf[507],
|
|
buf[508]);
|
|
for (i = 0; i < 4; i++)
|
|
it821x_display_disk(i, buf + 128 * i);
|
|
kfree(buf);
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
* it821x_port_start - port setup
|
|
* @ap: ATA port being set up
|
|
*
|
|
* The it821x needs to maintain private data structures and also to
|
|
* use the standard PCI interface which lacks support for this
|
|
* functionality. We instead set up the private data on the port
|
|
* start hook, and tear it down on port stop
|
|
*/
|
|
|
|
static int it821x_port_start(struct ata_port *ap)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
|
struct it821x_dev *itdev;
|
|
u8 conf;
|
|
|
|
int ret = ata_bmdma_port_start(ap);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
itdev = devm_kzalloc(&pdev->dev, sizeof(struct it821x_dev), GFP_KERNEL);
|
|
if (itdev == NULL)
|
|
return -ENOMEM;
|
|
ap->private_data = itdev;
|
|
|
|
pci_read_config_byte(pdev, 0x50, &conf);
|
|
|
|
if (conf & 1) {
|
|
itdev->smart = 1;
|
|
/* Long I/O's although allowed in LBA48 space cause the
|
|
onboard firmware to enter the twighlight zone */
|
|
/* No ATAPI DMA in this mode either */
|
|
if (ap->port_no == 0)
|
|
it821x_probe_firmware(ap);
|
|
}
|
|
/* Pull the current clocks from 0x50 */
|
|
if (conf & (1 << (1 + ap->port_no)))
|
|
itdev->clock_mode = ATA_50;
|
|
else
|
|
itdev->clock_mode = ATA_66;
|
|
|
|
itdev->want[0][1] = ATA_ANY;
|
|
itdev->want[1][1] = ATA_ANY;
|
|
itdev->last_device = -1;
|
|
|
|
if (pdev->revision == 0x10) {
|
|
itdev->timing10 = 1;
|
|
/* Need to disable ATAPI DMA for this case */
|
|
if (!itdev->smart)
|
|
printk(KERN_WARNING DRV_NAME": Revision 0x10, workarounds activated.\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* it821x_rdc_cable - Cable detect for RDC1010
|
|
* @ap: port we are checking
|
|
*
|
|
* Return the RDC1010 cable type. Unlike the IT821x we know how to do
|
|
* this and can do host side cable detect
|
|
*/
|
|
|
|
static int it821x_rdc_cable(struct ata_port *ap)
|
|
{
|
|
u16 r40;
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
|
|
|
pci_read_config_word(pdev, 0x40, &r40);
|
|
if (r40 & (1 << (2 + ap->port_no)))
|
|
return ATA_CBL_PATA40;
|
|
return ATA_CBL_PATA80;
|
|
}
|
|
|
|
static struct scsi_host_template it821x_sht = {
|
|
ATA_BMDMA_SHT(DRV_NAME),
|
|
};
|
|
|
|
static struct ata_port_operations it821x_smart_port_ops = {
|
|
.inherits = &ata_bmdma_port_ops,
|
|
|
|
.check_atapi_dma= it821x_check_atapi_dma,
|
|
.qc_issue = it821x_smart_qc_issue,
|
|
|
|
.cable_detect = ata_cable_80wire,
|
|
.set_mode = it821x_smart_set_mode,
|
|
.dev_config = it821x_dev_config,
|
|
.read_id = it821x_read_id,
|
|
|
|
.port_start = it821x_port_start,
|
|
};
|
|
|
|
static struct ata_port_operations it821x_passthru_port_ops = {
|
|
.inherits = &ata_bmdma_port_ops,
|
|
|
|
.check_atapi_dma= it821x_check_atapi_dma,
|
|
.sff_dev_select = it821x_passthru_dev_select,
|
|
.bmdma_start = it821x_passthru_bmdma_start,
|
|
.bmdma_stop = it821x_passthru_bmdma_stop,
|
|
.qc_issue = it821x_passthru_qc_issue,
|
|
|
|
.cable_detect = ata_cable_unknown,
|
|
.set_piomode = it821x_passthru_set_piomode,
|
|
.set_dmamode = it821x_passthru_set_dmamode,
|
|
|
|
.port_start = it821x_port_start,
|
|
};
|
|
|
|
static struct ata_port_operations it821x_rdc_port_ops = {
|
|
.inherits = &ata_bmdma_port_ops,
|
|
|
|
.check_atapi_dma= it821x_check_atapi_dma,
|
|
.sff_dev_select = it821x_passthru_dev_select,
|
|
.bmdma_start = it821x_passthru_bmdma_start,
|
|
.bmdma_stop = it821x_passthru_bmdma_stop,
|
|
.qc_issue = it821x_passthru_qc_issue,
|
|
|
|
.cable_detect = it821x_rdc_cable,
|
|
.set_piomode = it821x_passthru_set_piomode,
|
|
.set_dmamode = it821x_passthru_set_dmamode,
|
|
|
|
.port_start = it821x_port_start,
|
|
};
|
|
|
|
static void it821x_disable_raid(struct pci_dev *pdev)
|
|
{
|
|
/* Neither the RDC nor the IT8211 */
|
|
if (pdev->vendor != PCI_VENDOR_ID_ITE ||
|
|
pdev->device != PCI_DEVICE_ID_ITE_8212)
|
|
return;
|
|
|
|
/* Reset local CPU, and set BIOS not ready */
|
|
pci_write_config_byte(pdev, 0x5E, 0x01);
|
|
|
|
/* Set to bypass mode, and reset PCI bus */
|
|
pci_write_config_byte(pdev, 0x50, 0x00);
|
|
pci_write_config_word(pdev, PCI_COMMAND,
|
|
PCI_COMMAND_PARITY | PCI_COMMAND_IO |
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
pci_write_config_word(pdev, 0x40, 0xA0F3);
|
|
|
|
pci_write_config_dword(pdev,0x4C, 0x02040204);
|
|
pci_write_config_byte(pdev, 0x42, 0x36);
|
|
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
|
|
}
|
|
|
|
|
|
static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|
{
|
|
u8 conf;
|
|
|
|
static const struct ata_port_info info_smart = {
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA6,
|
|
.port_ops = &it821x_smart_port_ops
|
|
};
|
|
static const struct ata_port_info info_passthru = {
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA6,
|
|
.port_ops = &it821x_passthru_port_ops
|
|
};
|
|
static const struct ata_port_info info_rdc = {
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA6,
|
|
.port_ops = &it821x_rdc_port_ops
|
|
};
|
|
static const struct ata_port_info info_rdc_11 = {
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
/* No UDMA */
|
|
.port_ops = &it821x_rdc_port_ops
|
|
};
|
|
|
|
const struct ata_port_info *ppi[] = { NULL, NULL };
|
|
static char *mode[2] = { "pass through", "smart" };
|
|
int rc;
|
|
|
|
rc = pcim_enable_device(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_RDC) {
|
|
/* Deal with Vortex86SX */
|
|
if (pdev->revision == 0x11)
|
|
ppi[0] = &info_rdc_11;
|
|
else
|
|
ppi[0] = &info_rdc;
|
|
} else {
|
|
/* Force the card into bypass mode if so requested */
|
|
if (it8212_noraid) {
|
|
printk(KERN_INFO DRV_NAME ": forcing bypass mode.\n");
|
|
it821x_disable_raid(pdev);
|
|
}
|
|
pci_read_config_byte(pdev, 0x50, &conf);
|
|
conf &= 1;
|
|
|
|
printk(KERN_INFO DRV_NAME": controller in %s mode.\n",
|
|
mode[conf]);
|
|
if (conf == 0)
|
|
ppi[0] = &info_passthru;
|
|
else
|
|
ppi[0] = &info_smart;
|
|
}
|
|
return ata_pci_bmdma_init_one(pdev, ppi, &it821x_sht, NULL, 0);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int it821x_reinit_one(struct pci_dev *pdev)
|
|
{
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|
struct ata_host *host = pci_get_drvdata(pdev);
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|
int rc;
|
|
|
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rc = ata_pci_device_do_resume(pdev);
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|
if (rc)
|
|
return rc;
|
|
/* Resume - turn raid back off if need be */
|
|
if (it8212_noraid)
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|
it821x_disable_raid(pdev);
|
|
ata_host_resume(host);
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|
return rc;
|
|
}
|
|
#endif
|
|
|
|
static const struct pci_device_id it821x[] = {
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|
{ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), },
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|
{ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), },
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|
{ PCI_VDEVICE(RDC, PCI_DEVICE_ID_RDC_D1010), },
|
|
|
|
{ },
|
|
};
|
|
|
|
static struct pci_driver it821x_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = it821x,
|
|
.probe = it821x_init_one,
|
|
.remove = ata_pci_remove_one,
|
|
#ifdef CONFIG_PM
|
|
.suspend = ata_pci_device_suspend,
|
|
.resume = it821x_reinit_one,
|
|
#endif
|
|
};
|
|
|
|
module_pci_driver(it821x_pci_driver);
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
MODULE_DESCRIPTION("low-level driver for the IT8211/IT8212 IDE RAID controller");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, it821x);
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
module_param_named(noraid, it8212_noraid, int, S_IRUGO);
|
|
MODULE_PARM_DESC(noraid, "Force card into bypass mode");
|