303 строки
8.3 KiB
C
303 строки
8.3 KiB
C
#include <linux/init.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/atmel_tc.h>
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/*
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* We're configured to use a specific TC block, one that's not hooked
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* up to external hardware, to provide a time solution:
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*
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* - Two channels combine to create a free-running 32 bit counter
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* with a base rate of 5+ MHz, packaged as a clocksource (with
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* resolution better than 200 nsec).
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*
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* - The third channel may be used to provide a 16-bit clockevent
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* source, used in either periodic or oneshot mode. This runs
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* at 32 KiHZ, and can handle delays of up to two seconds.
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*
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* A boot clocksource and clockevent source are also currently needed,
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* unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
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* this code can be used when init_timers() is called, well before most
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* devices are set up. (Some low end AT91 parts, which can run uClinux,
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* have only the timers in one TC block... they currently don't support
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* the tclib code, because of that initialization issue.)
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*
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* REVISIT behavior during system suspend states... we should disable
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* all clocks and save the power. Easily done for clockevent devices,
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* but clocksources won't necessarily get the needed notifications.
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* For deeper system sleep states, this will be mandatory...
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*/
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static void __iomem *tcaddr;
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static cycle_t tc_get_cycles(void)
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{
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unsigned long flags;
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u32 lower, upper;
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raw_local_irq_save(flags);
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do {
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upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
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lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
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} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
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raw_local_irq_restore(flags);
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return (upper << 16) | lower;
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}
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static struct clocksource clksrc = {
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.name = "tcb_clksrc",
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.rating = 200,
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.read = tc_get_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 18,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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#ifdef CONFIG_GENERIC_CLOCKEVENTS
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struct tc_clkevt_device {
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struct clock_event_device clkevt;
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struct clk *clk;
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void __iomem *regs;
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};
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static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
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{
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return container_of(clkevt, struct tc_clkevt_device, clkevt);
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}
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/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
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* because using one of the divided clocks would usually mean the
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* tick rate can never be less than several dozen Hz (vs 0.5 Hz).
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*
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* A divided clock could be good for high resolution timers, since
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* 30.5 usec resolution can seem "low".
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*/
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static u32 timer_clock;
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static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
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{
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struct tc_clkevt_device *tcd = to_tc_clkevt(d);
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void __iomem *regs = tcd->regs;
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if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
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|| tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
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__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
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__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
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clk_disable(tcd->clk);
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}
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switch (m) {
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/* By not making the gentime core emulate periodic mode on top
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* of oneshot, we get lower overhead and improved accuracy.
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*/
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case CLOCK_EVT_MODE_PERIODIC:
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clk_enable(tcd->clk);
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/* slow clock, count up to RC, then irq and restart */
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__raw_writel(timer_clock
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| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
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regs + ATMEL_TC_REG(2, CMR));
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__raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
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/* Enable clock and interrupts on RC compare */
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__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
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/* go go gadget! */
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__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
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regs + ATMEL_TC_REG(2, CCR));
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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clk_enable(tcd->clk);
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/* slow clock, count up to RC, then irq and stop */
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__raw_writel(timer_clock | ATMEL_TC_CPCSTOP
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| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
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regs + ATMEL_TC_REG(2, CMR));
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__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
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/* set_next_event() configures and starts the timer */
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break;
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default:
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break;
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}
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}
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static int tc_next_event(unsigned long delta, struct clock_event_device *d)
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{
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__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
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/* go go gadget! */
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__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
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tcaddr + ATMEL_TC_REG(2, CCR));
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return 0;
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}
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static struct tc_clkevt_device clkevt = {
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.clkevt = {
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.name = "tc_clkevt",
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.features = CLOCK_EVT_FEAT_PERIODIC
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| CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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/* Should be lower than at91rm9200's system timer */
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.rating = 125,
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.cpumask = CPU_MASK_CPU0,
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.set_next_event = tc_next_event,
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.set_mode = tc_mode,
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},
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};
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static irqreturn_t ch2_irq(int irq, void *handle)
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{
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struct tc_clkevt_device *dev = handle;
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unsigned int sr;
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sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
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if (sr & ATMEL_TC_CPCS) {
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dev->clkevt.event_handler(&dev->clkevt);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static struct irqaction tc_irqaction = {
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.name = "tc_clkevt",
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.flags = IRQF_TIMER | IRQF_DISABLED,
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.handler = ch2_irq,
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};
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static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
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{
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struct clk *t2_clk = tc->clk[2];
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int irq = tc->irq[2];
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clkevt.regs = tc->regs;
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clkevt.clk = t2_clk;
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tc_irqaction.dev_id = &clkevt;
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timer_clock = clk32k_divisor_idx;
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clkevt.clkevt.mult = div_sc(32768, NSEC_PER_SEC, clkevt.clkevt.shift);
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clkevt.clkevt.max_delta_ns
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= clockevent_delta2ns(0xffff, &clkevt.clkevt);
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clkevt.clkevt.min_delta_ns = clockevent_delta2ns(1, &clkevt.clkevt) + 1;
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setup_irq(irq, &tc_irqaction);
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clockevents_register_device(&clkevt.clkevt);
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}
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#else /* !CONFIG_GENERIC_CLOCKEVENTS */
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static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
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{
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/* NOTHING */
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}
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#endif
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static int __init tcb_clksrc_init(void)
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{
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static char bootinfo[] __initdata
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= KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
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struct platform_device *pdev;
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struct atmel_tc *tc;
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struct clk *t0_clk;
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u32 rate, divided_rate = 0;
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int best_divisor_idx = -1;
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int clk32k_divisor_idx = -1;
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int i;
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tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK, clksrc.name);
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if (!tc) {
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pr_debug("can't alloc TC for clocksource\n");
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return -ENODEV;
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}
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tcaddr = tc->regs;
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pdev = tc->pdev;
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t0_clk = tc->clk[0];
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clk_enable(t0_clk);
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/* How fast will we be counting? Pick something over 5 MHz. */
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rate = (u32) clk_get_rate(t0_clk);
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for (i = 0; i < 5; i++) {
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unsigned divisor = atmel_tc_divisors[i];
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unsigned tmp;
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/* remember 32 KiHz clock for later */
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if (!divisor) {
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clk32k_divisor_idx = i;
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continue;
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}
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tmp = rate / divisor;
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pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
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if (best_divisor_idx > 0) {
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if (tmp < 5 * 1000 * 1000)
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continue;
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}
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divided_rate = tmp;
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best_divisor_idx = i;
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}
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clksrc.mult = clocksource_hz2mult(divided_rate, clksrc.shift);
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printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
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divided_rate / 1000000,
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((divided_rate + 500000) % 1000000) / 1000);
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/* tclib will give us three clocks no matter what the
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* underlying platform supports.
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*/
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clk_enable(tc->clk[1]);
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/* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
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__raw_writel(best_divisor_idx /* likely divide-by-8 */
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| ATMEL_TC_WAVE
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| ATMEL_TC_WAVESEL_UP /* free-run */
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| ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
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| ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
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tcaddr + ATMEL_TC_REG(0, CMR));
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__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
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__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
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__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
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__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
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/* channel 1: waveform mode, input TIOA0 */
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__raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */
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| ATMEL_TC_WAVE
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| ATMEL_TC_WAVESEL_UP, /* free-run */
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tcaddr + ATMEL_TC_REG(1, CMR));
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__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
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__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
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/* chain channel 0 to channel 1, then reset all the timers */
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__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
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__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
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/* and away we go! */
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clocksource_register(&clksrc);
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/* channel 2: periodic and oneshot timer support */
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setup_clkevents(tc, clk32k_divisor_idx);
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return 0;
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}
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arch_initcall(tcb_clksrc_init);
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