410 строки
10 KiB
C
410 строки
10 KiB
C
/*
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* AVR32 SMC/CFC PATA Driver
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*
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* Copyright (C) 2007 Atmel Norway
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*/
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#define DEBUG
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <scsi/scsi_host.h>
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#include <linux/ata.h>
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#include <linux/libata.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <mach/board.h>
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#include <mach/smc.h>
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#define DRV_NAME "pata_at32"
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#define DRV_VERSION "0.0.3"
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/*
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* CompactFlash controller memory layout relative to the base address:
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*
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* Attribute memory: 0000 0000 -> 003f ffff
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* Common memory: 0040 0000 -> 007f ffff
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* I/O memory: 0080 0000 -> 00bf ffff
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* True IDE Mode: 00c0 0000 -> 00df ffff
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* Alt IDE Mode: 00e0 0000 -> 00ff ffff
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*
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* Only True IDE and Alt True IDE mode are needed for this driver.
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*
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* True IDE mode => CS0 = 0, CS1 = 1 (cmd, error, stat, etc)
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* Alt True IDE mode => CS0 = 1, CS1 = 0 (ctl, alt_stat)
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*/
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#define CF_IDE_OFFSET 0x00c00000
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#define CF_ALT_IDE_OFFSET 0x00e00000
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#define CF_RES_SIZE 2048
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/*
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* Define DEBUG_BUS if you are doing debugging of your own EBI -> PATA
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* adaptor with a logic analyzer or similar.
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*/
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#undef DEBUG_BUS
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/*
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* ATA PIO modes
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*
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* Name | Mb/s | Min cycle time | Mask
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* --------+-------+----------------+--------
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* Mode 0 | 3.3 | 600 ns | 0x01
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* Mode 1 | 5.2 | 383 ns | 0x03
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* Mode 2 | 8.3 | 240 ns | 0x07
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* Mode 3 | 11.1 | 180 ns | 0x0f
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* Mode 4 | 16.7 | 120 ns | 0x1f
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*
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* Alter PIO_MASK below according to table to set maximal PIO mode.
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*/
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#define PIO_MASK (0x1f)
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/*
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* Struct containing private information about device.
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*/
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struct at32_ide_info {
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unsigned int irq;
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struct resource res_ide;
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struct resource res_alt;
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void __iomem *ide_addr;
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void __iomem *alt_addr;
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unsigned int cs;
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struct smc_config smc;
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};
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/*
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* Setup SMC for the given ATA timing.
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*/
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static int pata_at32_setup_timing(struct device *dev,
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struct at32_ide_info *info,
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const struct ata_timing *ata)
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{
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struct smc_config *smc = &info->smc;
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struct smc_timing timing;
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int active;
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int recover;
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memset(&timing, 0, sizeof(struct smc_timing));
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/* Total cycle time */
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timing.read_cycle = ata->cyc8b;
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/* DIOR <= CFIOR timings */
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timing.nrd_setup = ata->setup;
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timing.nrd_pulse = ata->act8b;
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timing.nrd_recover = ata->rec8b;
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/* Convert nanosecond timing to clock cycles */
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smc_set_timing(smc, &timing);
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/* Add one extra cycle setup due to signal ring */
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smc->nrd_setup = smc->nrd_setup + 1;
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active = smc->nrd_setup + smc->nrd_pulse;
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recover = smc->read_cycle - active;
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/* Need at least two cycles recovery */
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if (recover < 2)
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smc->read_cycle = active + 2;
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/* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */
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smc->ncs_read_setup = 1;
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smc->ncs_read_pulse = smc->read_cycle - 2;
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/* Write timings same as read timings */
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smc->write_cycle = smc->read_cycle;
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smc->nwe_setup = smc->nrd_setup;
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smc->nwe_pulse = smc->nrd_pulse;
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smc->ncs_write_setup = smc->ncs_read_setup;
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smc->ncs_write_pulse = smc->ncs_read_pulse;
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/* Do some debugging output of ATA and SMC timings */
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dev_dbg(dev, "ATA: C=%d S=%d P=%d R=%d\n",
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ata->cyc8b, ata->setup, ata->act8b, ata->rec8b);
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dev_dbg(dev, "SMC: C=%d S=%d P=%d NS=%d NP=%d\n",
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smc->read_cycle, smc->nrd_setup, smc->nrd_pulse,
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smc->ncs_read_setup, smc->ncs_read_pulse);
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/* Finally, configure the SMC */
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return smc_set_configuration(info->cs, smc);
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}
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/*
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* Procedures for libATA.
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*/
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static void pata_at32_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct ata_timing timing;
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struct at32_ide_info *info = ap->host->private_data;
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int ret;
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/* Compute ATA timing */
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ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
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if (ret) {
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dev_warn(ap->dev, "Failed to compute ATA timing %d\n", ret);
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return;
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}
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/* Setup SMC to ATA timing */
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ret = pata_at32_setup_timing(ap->dev, info, &timing);
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if (ret) {
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dev_warn(ap->dev, "Failed to setup ATA timing %d\n", ret);
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return;
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}
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}
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static struct scsi_host_template at32_sht = {
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ATA_PIO_SHT(DRV_NAME),
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};
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static struct ata_port_operations at32_port_ops = {
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.inherits = &ata_sff_port_ops,
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.cable_detect = ata_cable_40wire,
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.set_piomode = pata_at32_set_piomode,
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};
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static int __init pata_at32_init_one(struct device *dev,
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struct at32_ide_info *info)
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{
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struct ata_host *host;
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struct ata_port *ap;
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host = ata_host_alloc(dev, 1);
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if (!host)
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return -ENOMEM;
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ap = host->ports[0];
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/* Setup ATA bindings */
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ap->ops = &at32_port_ops;
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ap->pio_mask = PIO_MASK;
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ap->flags |= ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS;
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/*
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* Since all 8-bit taskfile transfers has to go on the lower
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* byte of the data bus and there is a bug in the SMC that
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* makes it impossible to alter the bus width during runtime,
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* we need to hardwire the address signals as follows:
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*
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* A_IDE(2:0) <= A_EBI(3:1)
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*
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* This makes all addresses on the EBI even, thus all data
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* will be on the lower byte of the data bus. All addresses
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* used by libATA need to be altered according to this.
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*/
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ap->ioaddr.altstatus_addr = info->alt_addr + (0x06 << 1);
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ap->ioaddr.ctl_addr = info->alt_addr + (0x06 << 1);
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ap->ioaddr.data_addr = info->ide_addr + (ATA_REG_DATA << 1);
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ap->ioaddr.error_addr = info->ide_addr + (ATA_REG_ERR << 1);
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ap->ioaddr.feature_addr = info->ide_addr + (ATA_REG_FEATURE << 1);
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ap->ioaddr.nsect_addr = info->ide_addr + (ATA_REG_NSECT << 1);
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ap->ioaddr.lbal_addr = info->ide_addr + (ATA_REG_LBAL << 1);
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ap->ioaddr.lbam_addr = info->ide_addr + (ATA_REG_LBAM << 1);
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ap->ioaddr.lbah_addr = info->ide_addr + (ATA_REG_LBAH << 1);
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ap->ioaddr.device_addr = info->ide_addr + (ATA_REG_DEVICE << 1);
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ap->ioaddr.status_addr = info->ide_addr + (ATA_REG_STATUS << 1);
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ap->ioaddr.command_addr = info->ide_addr + (ATA_REG_CMD << 1);
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/* Set info as private data of ATA host */
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host->private_data = info;
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/* Register ATA device and return */
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return ata_host_activate(host, info->irq, ata_sff_interrupt,
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IRQF_SHARED | IRQF_TRIGGER_RISING,
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&at32_sht);
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}
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/*
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* This function may come in handy for people analyzing their own
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* EBI -> PATA adaptors.
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*/
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#ifdef DEBUG_BUS
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static void __init pata_at32_debug_bus(struct device *dev,
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struct at32_ide_info *info)
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{
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const int d1 = 0xff;
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const int d2 = 0x00;
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int i;
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/* Write 8-bit values (registers) */
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iowrite8(d1, info->alt_addr + (0x06 << 1));
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iowrite8(d2, info->alt_addr + (0x06 << 1));
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for (i = 0; i < 8; i++) {
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iowrite8(d1, info->ide_addr + (i << 1));
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iowrite8(d2, info->ide_addr + (i << 1));
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}
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/* Write 16 bit values (data) */
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iowrite16(d1, info->ide_addr);
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iowrite16(d1 << 8, info->ide_addr);
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iowrite16(d1, info->ide_addr);
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iowrite16(d1 << 8, info->ide_addr);
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}
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#endif
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static int __init pata_at32_probe(struct platform_device *pdev)
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{
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const struct ata_timing initial_timing =
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{XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0};
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struct device *dev = &pdev->dev;
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struct at32_ide_info *info;
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struct ide_platform_data *board = pdev->dev.platform_data;
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struct resource *res;
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int irq;
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int ret;
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if (!board)
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return -ENXIO;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENXIO;
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/* Retrive IRQ */
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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/* Setup struct containing private information */
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info = kzalloc(sizeof(struct at32_ide_info), GFP_KERNEL);
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if (!info)
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return -ENOMEM;
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info->irq = irq;
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info->cs = board->cs;
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/* Request memory resources */
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info->res_ide.start = res->start + CF_IDE_OFFSET;
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info->res_ide.end = info->res_ide.start + CF_RES_SIZE - 1;
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info->res_ide.name = "ide";
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info->res_ide.flags = IORESOURCE_MEM;
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ret = request_resource(res, &info->res_ide);
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if (ret)
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goto err_req_res_ide;
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info->res_alt.start = res->start + CF_ALT_IDE_OFFSET;
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info->res_alt.end = info->res_alt.start + CF_RES_SIZE - 1;
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info->res_alt.name = "alt";
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info->res_alt.flags = IORESOURCE_MEM;
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ret = request_resource(res, &info->res_alt);
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if (ret)
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goto err_req_res_alt;
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/* Setup non-timing elements of SMC */
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info->smc.bus_width = 2; /* 16 bit data bus */
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info->smc.nrd_controlled = 1; /* Sample data on rising edge of NRD */
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info->smc.nwe_controlled = 0; /* Drive data on falling edge of NCS */
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info->smc.nwait_mode = 3; /* NWAIT is in READY mode */
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info->smc.byte_write = 0; /* Byte select access type */
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info->smc.tdf_mode = 0; /* TDF optimization disabled */
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info->smc.tdf_cycles = 0; /* No TDF wait cycles */
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/* Setup SMC to ATA timing */
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ret = pata_at32_setup_timing(dev, info, &initial_timing);
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if (ret)
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goto err_setup_timing;
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/* Map ATA address space */
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ret = -ENOMEM;
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info->ide_addr = devm_ioremap(dev, info->res_ide.start, 16);
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info->alt_addr = devm_ioremap(dev, info->res_alt.start, 16);
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if (!info->ide_addr || !info->alt_addr)
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goto err_ioremap;
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#ifdef DEBUG_BUS
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pata_at32_debug_bus(dev, info);
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#endif
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/* Setup and register ATA device */
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ret = pata_at32_init_one(dev, info);
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if (ret)
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goto err_ata_device;
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return 0;
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err_ata_device:
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err_ioremap:
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err_setup_timing:
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release_resource(&info->res_alt);
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err_req_res_alt:
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release_resource(&info->res_ide);
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err_req_res_ide:
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kfree(info);
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return ret;
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}
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static int __exit pata_at32_remove(struct platform_device *pdev)
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{
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struct ata_host *host = platform_get_drvdata(pdev);
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struct at32_ide_info *info;
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if (!host)
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return 0;
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info = host->private_data;
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ata_host_detach(host);
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if (!info)
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return 0;
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release_resource(&info->res_ide);
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release_resource(&info->res_alt);
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kfree(info);
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return 0;
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}
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/* work with hotplug and coldplug */
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MODULE_ALIAS("platform:at32_ide");
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static struct platform_driver pata_at32_driver = {
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.remove = __exit_p(pata_at32_remove),
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.driver = {
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.name = "at32_ide",
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.owner = THIS_MODULE,
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},
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};
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static int __init pata_at32_init(void)
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{
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return platform_driver_probe(&pata_at32_driver, pata_at32_probe);
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}
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static void __exit pata_at32_exit(void)
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{
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platform_driver_unregister(&pata_at32_driver);
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}
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module_init(pata_at32_init);
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module_exit(pata_at32_exit);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("AVR32 SMC/CFC PATA Driver");
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MODULE_AUTHOR("Kristoffer Nyborg Gregertsen <kngregertsen@norway.atmel.com>");
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MODULE_VERSION(DRV_VERSION);
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