656 строки
15 KiB
Plaintext
656 строки
15 KiB
Plaintext
/*
|
|
* SAMSUNG EXYNOS5420 SoC device tree source
|
|
*
|
|
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
|
* http://www.samsung.com
|
|
*
|
|
* SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
|
|
* EXYNOS5420 based board files can include this file and provide
|
|
* values for board specfic bindings.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include "exynos5.dtsi"
|
|
#include "exynos5420-pinctrl.dtsi"
|
|
|
|
#include <dt-bindings/clk/exynos-audss-clk.h>
|
|
|
|
/ {
|
|
compatible = "samsung,exynos5420";
|
|
|
|
aliases {
|
|
mshc0 = &mmc_0;
|
|
mshc1 = &mmc_1;
|
|
mshc2 = &mmc_2;
|
|
pinctrl0 = &pinctrl_0;
|
|
pinctrl1 = &pinctrl_1;
|
|
pinctrl2 = &pinctrl_2;
|
|
pinctrl3 = &pinctrl_3;
|
|
pinctrl4 = &pinctrl_4;
|
|
i2c0 = &i2c_0;
|
|
i2c1 = &i2c_1;
|
|
i2c2 = &i2c_2;
|
|
i2c3 = &i2c_3;
|
|
i2c4 = &hsi2c_4;
|
|
i2c5 = &hsi2c_5;
|
|
i2c6 = &hsi2c_6;
|
|
i2c7 = &hsi2c_7;
|
|
i2c8 = &hsi2c_8;
|
|
i2c9 = &hsi2c_9;
|
|
i2c10 = &hsi2c_10;
|
|
gsc0 = &gsc_0;
|
|
gsc1 = &gsc_1;
|
|
spi0 = &spi_0;
|
|
spi1 = &spi_1;
|
|
spi2 = &spi_2;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0x0>;
|
|
clock-frequency = <1800000000>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0x1>;
|
|
clock-frequency = <1800000000>;
|
|
};
|
|
|
|
cpu2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0x2>;
|
|
clock-frequency = <1800000000>;
|
|
};
|
|
|
|
cpu3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0x3>;
|
|
clock-frequency = <1800000000>;
|
|
};
|
|
|
|
cpu4: cpu@100 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x100>;
|
|
clock-frequency = <1000000000>;
|
|
};
|
|
|
|
cpu5: cpu@101 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x101>;
|
|
clock-frequency = <1000000000>;
|
|
};
|
|
|
|
cpu6: cpu@102 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x102>;
|
|
clock-frequency = <1000000000>;
|
|
};
|
|
|
|
cpu7: cpu@103 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x103>;
|
|
clock-frequency = <1000000000>;
|
|
};
|
|
};
|
|
|
|
clock: clock-controller@10010000 {
|
|
compatible = "samsung,exynos5420-clock";
|
|
reg = <0x10010000 0x30000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audss: audss-clock-controller@3810000 {
|
|
compatible = "samsung,exynos5420-audss-clock";
|
|
reg = <0x03810000 0x0C>;
|
|
#clock-cells = <1>;
|
|
clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
|
|
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
|
|
};
|
|
|
|
codec@11000000 {
|
|
compatible = "samsung,mfc-v7";
|
|
reg = <0x11000000 0x10000>;
|
|
interrupts = <0 96 0>;
|
|
clocks = <&clock 401>;
|
|
clock-names = "mfc";
|
|
};
|
|
|
|
mmc_0: mmc@12200000 {
|
|
compatible = "samsung,exynos5420-dw-mshc-smu";
|
|
interrupts = <0 75 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x12200000 0x2000>;
|
|
clocks = <&clock 351>, <&clock 132>;
|
|
clock-names = "biu", "ciu";
|
|
fifo-depth = <0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc_1: mmc@12210000 {
|
|
compatible = "samsung,exynos5420-dw-mshc-smu";
|
|
interrupts = <0 76 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x12210000 0x2000>;
|
|
clocks = <&clock 352>, <&clock 133>;
|
|
clock-names = "biu", "ciu";
|
|
fifo-depth = <0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc_2: mmc@12220000 {
|
|
compatible = "samsung,exynos5420-dw-mshc";
|
|
interrupts = <0 77 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x12220000 0x1000>;
|
|
clocks = <&clock 353>, <&clock 134>;
|
|
clock-names = "biu", "ciu";
|
|
fifo-depth = <0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mct@101C0000 {
|
|
compatible = "samsung,exynos4210-mct";
|
|
reg = <0x101C0000 0x800>;
|
|
interrupt-controller;
|
|
#interrups-cells = <1>;
|
|
interrupt-parent = <&mct_map>;
|
|
interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
|
|
<8>, <9>, <10>, <11>;
|
|
clocks = <&clock 1>, <&clock 315>;
|
|
clock-names = "fin_pll", "mct";
|
|
|
|
mct_map: mct-map {
|
|
#interrupt-cells = <1>;
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
interrupt-map = <0 &combiner 23 3>,
|
|
<1 &combiner 23 4>,
|
|
<2 &combiner 25 2>,
|
|
<3 &combiner 25 3>,
|
|
<4 &gic 0 120 0>,
|
|
<5 &gic 0 121 0>,
|
|
<6 &gic 0 122 0>,
|
|
<7 &gic 0 123 0>,
|
|
<8 &gic 0 128 0>,
|
|
<9 &gic 0 129 0>,
|
|
<10 &gic 0 130 0>,
|
|
<11 &gic 0 131 0>;
|
|
};
|
|
};
|
|
|
|
gsc_pd: power-domain@10044000 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10044000 0x20>;
|
|
};
|
|
|
|
isp_pd: power-domain@10044020 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10044020 0x20>;
|
|
};
|
|
|
|
mfc_pd: power-domain@10044060 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10044060 0x20>;
|
|
};
|
|
|
|
disp_pd: power-domain@100440C0 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x100440C0 0x20>;
|
|
};
|
|
|
|
mau_pd: power-domain@100440E0 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x100440E0 0x20>;
|
|
};
|
|
|
|
g2d_pd: power-domain@10044100 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10044100 0x20>;
|
|
};
|
|
|
|
msc_pd: power-domain@10044120 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10044120 0x20>;
|
|
};
|
|
|
|
pinctrl_0: pinctrl@13400000 {
|
|
compatible = "samsung,exynos5420-pinctrl";
|
|
reg = <0x13400000 0x1000>;
|
|
interrupts = <0 45 0>;
|
|
|
|
wakeup-interrupt-controller {
|
|
compatible = "samsung,exynos4210-wakeup-eint";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 32 0>;
|
|
};
|
|
};
|
|
|
|
pinctrl_1: pinctrl@13410000 {
|
|
compatible = "samsung,exynos5420-pinctrl";
|
|
reg = <0x13410000 0x1000>;
|
|
interrupts = <0 78 0>;
|
|
};
|
|
|
|
pinctrl_2: pinctrl@14000000 {
|
|
compatible = "samsung,exynos5420-pinctrl";
|
|
reg = <0x14000000 0x1000>;
|
|
interrupts = <0 46 0>;
|
|
};
|
|
|
|
pinctrl_3: pinctrl@14010000 {
|
|
compatible = "samsung,exynos5420-pinctrl";
|
|
reg = <0x14010000 0x1000>;
|
|
interrupts = <0 50 0>;
|
|
};
|
|
|
|
pinctrl_4: pinctrl@03860000 {
|
|
compatible = "samsung,exynos5420-pinctrl";
|
|
reg = <0x03860000 0x1000>;
|
|
interrupts = <0 47 0>;
|
|
};
|
|
|
|
rtc@101E0000 {
|
|
clocks = <&clock 317>;
|
|
clock-names = "rtc";
|
|
status = "okay";
|
|
};
|
|
|
|
amba {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "arm,amba-bus";
|
|
interrupt-parent = <&gic>;
|
|
ranges;
|
|
|
|
pdma0: pdma@121A0000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x121A0000 0x1000>;
|
|
interrupts = <0 34 0>;
|
|
clocks = <&clock 362>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
#dma-channels = <8>;
|
|
#dma-requests = <32>;
|
|
};
|
|
|
|
pdma1: pdma@121B0000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x121B0000 0x1000>;
|
|
interrupts = <0 35 0>;
|
|
clocks = <&clock 363>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
#dma-channels = <8>;
|
|
#dma-requests = <32>;
|
|
};
|
|
|
|
mdma0: mdma@10800000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x10800000 0x1000>;
|
|
interrupts = <0 33 0>;
|
|
clocks = <&clock 473>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
#dma-channels = <8>;
|
|
#dma-requests = <1>;
|
|
};
|
|
|
|
mdma1: mdma@11C10000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x11C10000 0x1000>;
|
|
interrupts = <0 124 0>;
|
|
clocks = <&clock 442>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
#dma-channels = <8>;
|
|
#dma-requests = <1>;
|
|
};
|
|
};
|
|
|
|
spi_0: spi@12d20000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x12d20000 0x100>;
|
|
interrupts = <0 66 0>;
|
|
dmas = <&pdma0 5
|
|
&pdma0 4>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_bus>;
|
|
clocks = <&clock 271>, <&clock 135>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_1: spi@12d30000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x12d30000 0x100>;
|
|
interrupts = <0 67 0>;
|
|
dmas = <&pdma1 5
|
|
&pdma1 4>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_bus>;
|
|
clocks = <&clock 272>, <&clock 136>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_2: spi@12d40000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x12d40000 0x100>;
|
|
interrupts = <0 68 0>;
|
|
dmas = <&pdma0 7
|
|
&pdma0 6>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi2_bus>;
|
|
clocks = <&clock 273>, <&clock 137>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
status = "disabled";
|
|
};
|
|
|
|
serial@12C00000 {
|
|
clocks = <&clock 257>, <&clock 128>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|
|
|
|
serial@12C10000 {
|
|
clocks = <&clock 258>, <&clock 129>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|
|
|
|
serial@12C20000 {
|
|
clocks = <&clock 259>, <&clock 130>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|
|
|
|
serial@12C30000 {
|
|
clocks = <&clock 260>, <&clock 131>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|
|
|
|
pwm: pwm@12dd0000 {
|
|
compatible = "samsung,exynos4210-pwm";
|
|
reg = <0x12dd0000 0x100>;
|
|
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&clock 279>;
|
|
clock-names = "timers";
|
|
};
|
|
|
|
dp_phy: video-phy@10040728 {
|
|
compatible = "samsung,exynos5250-dp-video-phy";
|
|
reg = <0x10040728 4>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
dp-controller@145B0000 {
|
|
clocks = <&clock 412>;
|
|
clock-names = "dp";
|
|
phys = <&dp_phy>;
|
|
phy-names = "dp";
|
|
};
|
|
|
|
fimd@14400000 {
|
|
samsung,power-domain = <&disp_pd>;
|
|
clocks = <&clock 147>, <&clock 421>;
|
|
clock-names = "sclk_fimd", "fimd";
|
|
};
|
|
|
|
adc: adc@12D10000 {
|
|
compatible = "samsung,exynos-adc-v2";
|
|
reg = <0x12D10000 0x100>, <0x10040720 0x4>;
|
|
interrupts = <0 106 0>;
|
|
clocks = <&clock 270>;
|
|
clock-names = "adc";
|
|
#io-channel-cells = <1>;
|
|
io-channel-ranges;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_0: i2c@12C60000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C60000 0x100>;
|
|
interrupts = <0 56 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 261>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_1: i2c@12C70000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C70000 0x100>;
|
|
interrupts = <0 57 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 262>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_2: i2c@12C80000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C80000 0x100>;
|
|
interrupts = <0 58 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 263>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_3: i2c@12C90000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C90000 0x100>;
|
|
interrupts = <0 59 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 264>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_4: i2c@12CA0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CA0000 0x1000>;
|
|
interrupts = <0 60 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_hs_bus>;
|
|
clocks = <&clock 265>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_5: i2c@12CB0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CB0000 0x1000>;
|
|
interrupts = <0 61 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5_hs_bus>;
|
|
clocks = <&clock 266>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_6: i2c@12CC0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CC0000 0x1000>;
|
|
interrupts = <0 62 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6_hs_bus>;
|
|
clocks = <&clock 267>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_7: i2c@12CD0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CD0000 0x1000>;
|
|
interrupts = <0 63 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c7_hs_bus>;
|
|
clocks = <&clock 268>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_8: i2c@12E00000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12E00000 0x1000>;
|
|
interrupts = <0 87 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c8_hs_bus>;
|
|
clocks = <&clock 281>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_9: i2c@12E10000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12E10000 0x1000>;
|
|
interrupts = <0 88 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c9_hs_bus>;
|
|
clocks = <&clock 282>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_10: i2c@12E20000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12E20000 0x1000>;
|
|
interrupts = <0 203 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c10_hs_bus>;
|
|
clocks = <&clock 283>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hdmi@14530000 {
|
|
compatible = "samsung,exynos4212-hdmi";
|
|
reg = <0x14530000 0x70000>;
|
|
interrupts = <0 95 0>;
|
|
clocks = <&clock 413>, <&clock 143>, <&clock 768>,
|
|
<&clock 158>, <&clock 640>;
|
|
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
|
|
"sclk_hdmiphy", "mout_hdmi";
|
|
status = "disabled";
|
|
};
|
|
|
|
mixer@14450000 {
|
|
compatible = "samsung,exynos5420-mixer";
|
|
reg = <0x14450000 0x10000>;
|
|
interrupts = <0 94 0>;
|
|
clocks = <&clock 431>, <&clock 143>;
|
|
clock-names = "mixer", "sclk_hdmi";
|
|
};
|
|
|
|
gsc_0: video-scaler@13e00000 {
|
|
compatible = "samsung,exynos5-gsc";
|
|
reg = <0x13e00000 0x1000>;
|
|
interrupts = <0 85 0>;
|
|
clocks = <&clock 465>;
|
|
clock-names = "gscl";
|
|
samsung,power-domain = <&gsc_pd>;
|
|
};
|
|
|
|
gsc_1: video-scaler@13e10000 {
|
|
compatible = "samsung,exynos5-gsc";
|
|
reg = <0x13e10000 0x1000>;
|
|
interrupts = <0 86 0>;
|
|
clocks = <&clock 466>;
|
|
clock-names = "gscl";
|
|
samsung,power-domain = <&gsc_pd>;
|
|
};
|
|
|
|
tmu_cpu0: tmu@10060000 {
|
|
compatible = "samsung,exynos5420-tmu";
|
|
reg = <0x10060000 0x100>;
|
|
interrupts = <0 65 0>;
|
|
clocks = <&clock 318>;
|
|
clock-names = "tmu_apbif";
|
|
};
|
|
|
|
tmu_cpu1: tmu@10064000 {
|
|
compatible = "samsung,exynos5420-tmu";
|
|
reg = <0x10064000 0x100>;
|
|
interrupts = <0 183 0>;
|
|
clocks = <&clock 318>;
|
|
clock-names = "tmu_apbif";
|
|
};
|
|
|
|
tmu_cpu2: tmu@10068000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
|
|
interrupts = <0 184 0>;
|
|
clocks = <&clock 318>, <&clock 318>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
};
|
|
|
|
tmu_cpu3: tmu@1006c000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
|
|
interrupts = <0 185 0>;
|
|
clocks = <&clock 318>, <&clock 319>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
};
|
|
|
|
tmu_gpu: tmu@100a0000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x100a0000 0x100>, <0x10068000 0x4>;
|
|
interrupts = <0 215 0>;
|
|
clocks = <&clock 319>, <&clock 318>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
};
|
|
};
|