зеркало из https://github.com/microsoft/clang-1.git
Remove the cellspu port.
Approved by Chris Lattner. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@167983 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Родитель
5a95d46029
Коммит
825d386c1d
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@ -384,13 +384,13 @@ public:
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case llvm::Triple::x86:
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case llvm::Triple::x86_64:
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case llvm::Triple::arm:
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case llvm::Triple::sparc:
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case llvm::Triple::sparc:
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this->MCountName = "__mcount";
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break;
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case llvm::Triple::mips64:
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case llvm::Triple::mips64el:
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case llvm::Triple::ppc:
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case llvm::Triple::sparcv9:
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case llvm::Triple::sparcv9:
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this->MCountName = "_mcount";
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break;
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}
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@ -1647,7 +1647,7 @@ public:
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NumAliases = 0;
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}
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virtual void getGCCAddlRegNames(const AddlRegName *&Names,
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unsigned &NumNames) const {
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unsigned &NumNames) const {
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Names = AddlRegNames;
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NumNames = llvm::array_lengthof(AddlRegNames);
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}
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@ -3325,11 +3325,11 @@ public:
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case 'v': // ...VFP load/store (reg+constant offset)
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case 'y': // ...iWMMXt load/store
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case 't': // address valid for load/store opaque types wider
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// than 128-bits
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// than 128-bits
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case 'n': // valid address for Neon doubleword vector load/store
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case 'm': // valid address for Neon element and structure load/store
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case 's': // valid address for non-offset loads/stores of quad-word
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// values in four ARM registers
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// values in four ARM registers
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Info.setAllowsMemory();
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Name++;
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return true;
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@ -4580,10 +4580,6 @@ static TargetInfo *AllocateTarget(const std::string &T) {
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return new SparcV8TargetInfo(T);
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}
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// FIXME: Need a real SPU target.
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case llvm::Triple::cellspu:
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return new PS3SPUTargetInfo<PPC64TargetInfo>(T);
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case llvm::Triple::tce:
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return new TCETargetInfo(T);
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@ -1,7 +1,6 @@
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// RUN: %clang_cc1 -triple i686 %s -emit-llvm -o - | FileCheck %s
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// RUN: %clang_cc1 -triple x86_64 %s -emit-llvm -o - | FileCheck %s
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// RUN: %clang_cc1 -triple arm %s -emit-llvm -o - | FileCheck %s
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// RUN: %clang_cc1 -triple cellspu %s -emit-llvm -o - | FileCheck %s
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// RUN: %clang_cc1 -triple mblaze %s -emit-llvm -o - | FileCheck %s
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// RUN: %clang_cc1 -triple mips %s -emit-llvm -o - | FileCheck %s
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// RUN: %clang_cc1 -triple mipsel %s -emit-llvm -o - | FileCheck %s
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@ -17,7 +17,6 @@ cxxflags = ['-D__STDC_LIMIT_MACROS',
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'-I%s/include' % root.llvm_src_root,
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'-I%s/include' % root.llvm_obj_root,
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'-I%s/lib/Target/ARM' % root.llvm_src_root,
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'-I%s/lib/Target/CellSPU' % root.llvm_src_root,
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'-I%s/lib/Target/CppBackend' % root.llvm_src_root,
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'-I%s/lib/Target/Mips' % root.llvm_src_root,
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'-I%s/lib/Target/MSIL' % root.llvm_src_root,
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@ -28,7 +27,6 @@ cxxflags = ['-D__STDC_LIMIT_MACROS',
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'-I%s/lib/Target/X86' % root.llvm_src_root,
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'-I%s/lib/Target/XCore' % root.llvm_src_root,
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'-I%s/lib/Target/ARM' % target_obj_root,
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'-I%s/lib/Target/CellSPU' % target_obj_root,
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'-I%s/lib/Target/CppBackend' % target_obj_root,
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'-I%s/lib/Target/Mips' % target_obj_root,
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'-I%s/lib/Target/MSIL' % target_obj_root,
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@ -17,7 +17,6 @@ cxxflags = ['-D__STDC_LIMIT_MACROS',
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'-I%s/include' % root.llvm_src_root,
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'-I%s/include' % root.llvm_obj_root,
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'-I%s/lib/Target/ARM' % root.llvm_src_root,
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'-I%s/lib/Target/CellSPU' % root.llvm_src_root,
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'-I%s/lib/Target/CppBackend' % root.llvm_src_root,
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'-I%s/lib/Target/Mips' % root.llvm_src_root,
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'-I%s/lib/Target/MSIL' % root.llvm_src_root,
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@ -28,7 +27,6 @@ cxxflags = ['-D__STDC_LIMIT_MACROS',
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'-I%s/lib/Target/X86' % root.llvm_src_root,
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'-I%s/lib/Target/XCore' % root.llvm_src_root,
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'-I%s/lib/Target/ARM' % target_obj_root,
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'-I%s/lib/Target/CellSPU' % target_obj_root,
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'-I%s/lib/Target/CppBackend' % target_obj_root,
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'-I%s/lib/Target/Mips' % target_obj_root,
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'-I%s/lib/Target/MSIL' % target_obj_root,
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@ -16,7 +16,6 @@ cxxflags = ['-D__STDC_LIMIT_MACROS',
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'-I%s/include' % root.llvm_src_root,
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'-I%s/include' % root.llvm_obj_root,
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'-I%s/lib/Target/ARM' % root.llvm_src_root,
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'-I%s/lib/Target/CellSPU' % root.llvm_src_root,
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'-I%s/lib/Target/CppBackend' % root.llvm_src_root,
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'-I%s/lib/Target/Mips' % root.llvm_src_root,
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'-I%s/lib/Target/MSIL' % root.llvm_src_root,
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@ -27,7 +26,6 @@ cxxflags = ['-D__STDC_LIMIT_MACROS',
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'-I%s/lib/Target/X86' % root.llvm_src_root,
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'-I%s/lib/Target/XCore' % root.llvm_src_root,
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'-I%s/lib/Target/ARM' % target_obj_root,
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'-I%s/lib/Target/CellSPU' % target_obj_root,
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'-I%s/lib/Target/CppBackend' % target_obj_root,
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'-I%s/lib/Target/Mips' % target_obj_root,
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'-I%s/lib/Target/MSIL' % target_obj_root,
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