зеркало из https://github.com/microsoft/git.git
186 строки
3.6 KiB
ArmAsm
186 строки
3.6 KiB
ArmAsm
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/*
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* SHA-1 implementation for PowerPC.
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*
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* Copyright (C) 2005 Paul Mackerras <paulus@samba.org>
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*/
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#define FS 80
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/*
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* We roll the registers for T, A, B, C, D, E around on each
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* iteration; T on iteration t is A on iteration t+1, and so on.
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* We use registers 7 - 12 for this.
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*/
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#define RT(t) ((((t)+5)%6)+7)
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#define RA(t) ((((t)+4)%6)+7)
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#define RB(t) ((((t)+3)%6)+7)
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#define RC(t) ((((t)+2)%6)+7)
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#define RD(t) ((((t)+1)%6)+7)
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#define RE(t) ((((t)+0)%6)+7)
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/* We use registers 16 - 31 for the W values */
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#define W(t) (((t)%16)+16)
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#define STEPD0(t) \
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and %r6,RB(t),RC(t); \
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andc %r0,RD(t),RB(t); \
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rotlwi RT(t),RA(t),5; \
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rotlwi RB(t),RB(t),30; \
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or %r6,%r6,%r0; \
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add %r0,RE(t),%r15; \
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add RT(t),RT(t),%r6; \
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add %r0,%r0,W(t); \
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add RT(t),RT(t),%r0
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#define STEPD1(t) \
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xor %r6,RB(t),RC(t); \
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rotlwi RT(t),RA(t),5; \
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rotlwi RB(t),RB(t),30; \
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xor %r6,%r6,RD(t); \
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add %r0,RE(t),%r15; \
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add RT(t),RT(t),%r6; \
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add %r0,%r0,W(t); \
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add RT(t),RT(t),%r0
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#define STEPD2(t) \
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and %r6,RB(t),RC(t); \
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and %r0,RB(t),RD(t); \
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rotlwi RT(t),RA(t),5; \
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rotlwi RB(t),RB(t),30; \
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or %r6,%r6,%r0; \
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and %r0,RC(t),RD(t); \
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or %r6,%r6,%r0; \
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add %r0,RE(t),%r15; \
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add RT(t),RT(t),%r6; \
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add %r0,%r0,W(t); \
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add RT(t),RT(t),%r0
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#define LOADW(t) \
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lwz W(t),(t)*4(%r4)
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#define UPDATEW(t) \
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xor %r0,W((t)-3),W((t)-8); \
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xor W(t),W((t)-16),W((t)-14); \
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xor W(t),W(t),%r0; \
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rotlwi W(t),W(t),1
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#define STEP0LD4(t) \
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STEPD0(t); LOADW((t)+4); \
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STEPD0((t)+1); LOADW((t)+5); \
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STEPD0((t)+2); LOADW((t)+6); \
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STEPD0((t)+3); LOADW((t)+7)
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#define STEPUP4(t, fn) \
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STEP##fn(t); UPDATEW((t)+4); \
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STEP##fn((t)+1); UPDATEW((t)+5); \
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STEP##fn((t)+2); UPDATEW((t)+6); \
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STEP##fn((t)+3); UPDATEW((t)+7)
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#define STEPUP20(t, fn) \
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STEPUP4(t, fn); \
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STEPUP4((t)+4, fn); \
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STEPUP4((t)+8, fn); \
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STEPUP4((t)+12, fn); \
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STEPUP4((t)+16, fn)
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.globl sha1_core
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sha1_core:
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stwu %r1,-FS(%r1)
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stw %r15,FS-68(%r1)
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stw %r16,FS-64(%r1)
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stw %r17,FS-60(%r1)
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stw %r18,FS-56(%r1)
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stw %r19,FS-52(%r1)
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stw %r20,FS-48(%r1)
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stw %r21,FS-44(%r1)
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stw %r22,FS-40(%r1)
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stw %r23,FS-36(%r1)
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stw %r24,FS-32(%r1)
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stw %r25,FS-28(%r1)
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stw %r26,FS-24(%r1)
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stw %r27,FS-20(%r1)
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stw %r28,FS-16(%r1)
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stw %r29,FS-12(%r1)
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stw %r30,FS-8(%r1)
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stw %r31,FS-4(%r1)
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/* Load up A - E */
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lwz RA(0),0(%r3) /* A */
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lwz RB(0),4(%r3) /* B */
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lwz RC(0),8(%r3) /* C */
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lwz RD(0),12(%r3) /* D */
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lwz RE(0),16(%r3) /* E */
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mtctr %r5
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1: LOADW(0)
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LOADW(1)
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LOADW(2)
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LOADW(3)
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lis %r15,0x5a82 /* K0-19 */
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ori %r15,%r15,0x7999
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STEP0LD4(0)
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STEP0LD4(4)
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STEP0LD4(8)
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STEPUP4(12, D0)
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STEPUP4(16, D0)
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lis %r15,0x6ed9 /* K20-39 */
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ori %r15,%r15,0xeba1
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STEPUP20(20, D1)
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lis %r15,0x8f1b /* K40-59 */
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ori %r15,%r15,0xbcdc
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STEPUP20(40, D2)
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lis %r15,0xca62 /* K60-79 */
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ori %r15,%r15,0xc1d6
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STEPUP4(60, D1)
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STEPUP4(64, D1)
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STEPUP4(68, D1)
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STEPUP4(72, D1)
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STEPD1(76)
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STEPD1(77)
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STEPD1(78)
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STEPD1(79)
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lwz %r20,16(%r3)
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lwz %r19,12(%r3)
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lwz %r18,8(%r3)
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lwz %r17,4(%r3)
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lwz %r16,0(%r3)
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add %r20,RE(80),%r20
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add RD(0),RD(80),%r19
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add RC(0),RC(80),%r18
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add RB(0),RB(80),%r17
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add RA(0),RA(80),%r16
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mr RE(0),%r20
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stw RA(0),0(%r3)
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stw RB(0),4(%r3)
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stw RC(0),8(%r3)
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stw RD(0),12(%r3)
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stw RE(0),16(%r3)
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addi %r4,%r4,64
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bdnz 1b
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lwz %r15,FS-68(%r1)
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lwz %r16,FS-64(%r1)
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lwz %r17,FS-60(%r1)
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lwz %r18,FS-56(%r1)
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lwz %r19,FS-52(%r1)
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lwz %r20,FS-48(%r1)
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lwz %r21,FS-44(%r1)
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lwz %r22,FS-40(%r1)
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lwz %r23,FS-36(%r1)
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lwz %r24,FS-32(%r1)
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lwz %r25,FS-28(%r1)
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lwz %r26,FS-24(%r1)
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lwz %r27,FS-20(%r1)
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lwz %r28,FS-16(%r1)
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lwz %r29,FS-12(%r1)
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lwz %r30,FS-8(%r1)
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lwz %r31,FS-4(%r1)
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addi %r1,%r1,FS
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blr
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