2018-01-12 04:41:10 +03:00
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#lang ivy1.7
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type word_t
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type reg_t
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type tag_t
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type eu_t
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type opcode = {op_alu,op_rd,op_wr,op_nop}
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module st_opr = {
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var valid : bool
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var tag : tag_t
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var val : word_t
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}
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# an uninterpreted function to model the ALU
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function f(X:word_t,Y:word_t) : word_t
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object ref = {
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action step(opin : opcode, # opcode input
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srca:reg_t, srcb:reg_t, dst:reg_t, # source and dest indices input
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2018-01-13 05:37:34 +03:00
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din: word_t, # data input
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st_choice : tag_t,
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issue_choice : tag_t,
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issue_eu : eu_t,
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exe_valid : bool
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)
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2018-01-12 04:41:10 +03:00
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2018-01-13 05:37:34 +03:00
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returns (
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dout : word_t
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)
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2018-01-12 04:41:10 +03:00
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var r(R:reg_t) : word_t # the register file
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implement step {
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2018-01-13 05:37:34 +03:00
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var opra : word_t;
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var oprb : word_t;
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var res : word_t;
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2018-01-12 04:41:10 +03:00
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if opin = op_alu {
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opra := r(srca);
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oprb := r(srcb);
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res := f(opra,oprb);
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r(dst) := res;
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}
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else if opin = op_rd {
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dout := r(srca);
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}
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else if opin = op_wr {
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r(dst) := din;
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2018-01-13 05:37:34 +03:00
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};
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# following doesn't belong here...
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# update the aux state (this is ghost, should not be here)
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if(opin = op_alu){
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toma.aux(st_choice).opra := opra;
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toma.aux(st_choice).oprb := oprb;
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toma.aux(st_choice).res := res;
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toma.aux(st_choice).srca := srca;
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toma.aux(st_choice).srcb := srcb;
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};
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2018-01-12 04:41:10 +03:00
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}
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}
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object toma = {
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object ir(self:reg_t) = {
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var resvd : bool
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var tag : tag_t
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var val : word_t
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}
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object st(self:tag_t) = {
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var valid : bool
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instance opra : st_opr
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instance oprb : st_opr
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var dst : reg_t
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var issued : bool
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}
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object eu(self:eu_t) = {
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var valid : bool
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var ready : bool
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var res : word_t
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var tag : tag_t
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}
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# the auxiliary state
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object aux(self:tag_t) = {
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var opra : word_t
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var oprb : word_t
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var res : word_t
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var srca : reg_t
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var srcb : reg_t
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var eu : eu_t
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}
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instance pout : st_opr
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after init {
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st(T).valid := false;
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ir(R).resvd := false;
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eu(E).valid := false;
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2018-01-13 05:37:34 +03:00
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# initialize abstract model to match the implementation
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ref.r(R) := ir(R).val;
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2018-01-12 04:41:10 +03:00
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}
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action step (
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2018-01-13 05:37:34 +03:00
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opin : opcode, # opcode input
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srca:reg_t, srcb:reg_t, dst:reg_t, # source and dest indices input
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din: word_t,
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2018-01-12 04:41:10 +03:00
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st_choice : tag_t,
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issue_choice : tag_t,
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issue_eu : eu_t,
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complete_eu : eu_t
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2018-01-13 05:37:34 +03:00
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)
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returns (
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stallout : bool,
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dout : word_t
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)
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=
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{
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2018-01-12 04:41:10 +03:00
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var exe_rdy : bool;
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var exe_valid : bool;
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var exe_tag : tag_t;
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var exe_opra : word_t;
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var exe_oprb : word_t;
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# completion of operation in execution unit, result on pout
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pout.valid := eu(complete_eu).valid & eu(complete_eu).ready;
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pout.val := eu(complete_eu).res;
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pout.tag := eu(complete_eu).tag;
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if pout.valid {
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eu(complete_eu).valid := false
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};
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2018-02-06 01:05:15 +03:00
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assert pout.valid -> complete_eu = aux(pout.tag).eu
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proof let E=complete_eu, I = pout.tag;
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2018-01-12 04:41:10 +03:00
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2018-02-06 01:05:15 +03:00
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assert pout.tag = I & pout.valid -> pout.val = aux(I).res
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proof let E = complete_eu, A = aux(I).opra, B = aux(I).oprb, C = f(A,B);
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2018-01-12 04:41:10 +03:00
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2018-01-16 02:25:07 +03:00
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# stall if station is busy or read of reserved register
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stallout := opin = op_alu & st(st_choice).valid
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| opin = op_rd & ir(srca).resvd;
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2018-01-12 04:41:10 +03:00
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# use pout to retire an instruction
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if(pout.valid){
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2018-01-13 05:37:34 +03:00
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ir(R).val := (pout.val) if (ir(R).resvd & ir(R).tag = pout.tag) else (ir(R).val);
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2018-01-16 02:25:07 +03:00
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ir(R).resvd := ir(R).tag ~= pout.tag & ir(R).resvd;
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2018-01-12 04:41:10 +03:00
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2018-01-13 05:37:34 +03:00
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st(T).opra.val := (pout.val) if ~st(T).opra.valid & st(T).opra.tag = pout.tag else st(T).opra.val;
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2018-01-16 02:25:07 +03:00
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st(T).opra.valid := st(T).opra.tag = pout.tag | st(T).opra.valid;
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2018-01-12 04:41:10 +03:00
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2018-01-13 05:37:34 +03:00
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st(T).oprb.val := (pout.val) if ~st(T).oprb.valid & st(T).oprb.tag = pout.tag else st(T).oprb.val;
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2018-01-16 02:25:07 +03:00
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st(T).oprb.valid := st(T).oprb.tag = pout.tag | st(T).oprb.valid;
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2018-01-12 04:41:10 +03:00
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2018-01-16 02:25:07 +03:00
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st(T).valid := ~(st(T).issued & pout.tag = T) & st(T).valid;
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2018-01-13 05:37:34 +03:00
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};
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2018-01-12 04:41:10 +03:00
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# perform the incoming op
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if(~stallout) {
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if opin = op_alu {
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# store the instruction in an RS
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st(st_choice).valid := true;
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st(st_choice).issued := false;
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# fetch the a operand (with bypass)
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if(pout.valid & ir(srca).resvd & pout.tag = ir(srca).tag) {
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st(st_choice).opra.valid := true;
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st(st_choice).opra.tag := ir(srca).tag;
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st(st_choice).opra.val := pout.val;
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} else {
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st(st_choice).opra.valid := ~ir(srca).resvd;
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st(st_choice).opra.tag := ir(srca).tag;
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st(st_choice).opra.val := ir(srca).val;
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2018-01-13 05:37:34 +03:00
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};
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2018-01-12 04:41:10 +03:00
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# fetch the b operand (with bypass) */
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if(pout.valid & ir(srcb).resvd & pout.tag = ir(srcb).tag){
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2018-01-13 05:37:34 +03:00
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st(st_choice).oprb.valid := true;
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2018-01-12 04:41:10 +03:00
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st(st_choice).oprb.tag := ir(srcb).tag;
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st(st_choice).oprb.val := pout.val;
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} else {
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st(st_choice).oprb.valid := ~ir(srcb).resvd;
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st(st_choice).oprb.tag := ir(srcb).tag;
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st(st_choice).oprb.val := ir(srcb).val;
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2018-01-16 02:25:07 +03:00
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};
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# mark the dst register as reserved
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ir(dst).resvd := true;
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ir(dst).tag := st_choice;
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2018-01-12 04:41:10 +03:00
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}
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else if opin = op_rd {
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dout := ir(srca).val;
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}
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else if opin = op_wr {
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ir(dst).val := din;
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ir(dst).resvd := false;
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}
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2018-01-13 05:37:34 +03:00
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};
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2018-01-12 04:41:10 +03:00
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# instruction issue from station to eu
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2018-01-13 05:37:34 +03:00
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exe_rdy := ~eu(issue_eu).valid;
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2018-01-12 04:41:10 +03:00
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if(st(issue_choice).valid
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& st(issue_choice).opra.valid
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& st(issue_choice).oprb.valid
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& ~st(issue_choice).issued
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& exe_rdy)
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{
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exe_valid := true;
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st(issue_choice).issued := true;
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}
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else exe_valid := false;
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exe_tag := issue_choice;
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exe_opra := st(issue_choice).opra.val;
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exe_oprb := st(issue_choice).oprb.val;
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# perform op in execution unit, store result
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if(~eu(issue_eu).valid){
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eu(issue_eu).valid := exe_valid;
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eu(issue_eu).res := f(exe_opra)(exe_oprb);
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eu(issue_eu).tag := exe_tag;
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2018-01-13 05:37:34 +03:00
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};
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2018-01-12 04:41:10 +03:00
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2018-01-13 05:37:34 +03:00
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# commit the abstract operation here
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2018-01-12 04:41:10 +03:00
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2018-01-13 05:37:34 +03:00
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if ~stallout {
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var dout := ref.step(opin,srca,srcb,dst,din,st_choice,issue_choice,issue_eu,exe_valid) # ghost
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2018-02-20 05:31:10 +03:00
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};
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2018-01-12 04:41:10 +03:00
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2018-02-20 05:31:10 +03:00
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if (exe_valid) {
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toma.aux(issue_choice).eu := issue_eu;
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};
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2018-01-12 04:41:10 +03:00
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}
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2018-01-13 05:37:34 +03:00
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2018-01-12 04:41:10 +03:00
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# the refinement maps
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invariant st(K).valid & st(K).opra.valid -> st(K).opra.val = aux(K).opra
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2018-01-13 05:37:34 +03:00
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proof let I = st(K).opra.tag, J = aux(K).srca, C = aux(K).opra
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2018-01-12 04:41:10 +03:00
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2018-01-13 05:37:34 +03:00
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invariant st(K).valid & st(K).oprb.valid -> st(K).oprb.val = aux(K).oprb
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proof let I = st(K).oprb.tag, J = aux(K).srcb, C = aux(K).oprb
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2018-01-12 04:41:10 +03:00
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# invariant pout.tag = I & pout.valid -> pout.val = aux(I).res;
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# proof let A = aux(i).opra, B = aux(i).oprb, C = f(a,b), J = complete_eu
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# # noninterference lemma
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# invariant pout.valid -> complete_eu = aux(pout.tag).eu;
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# proof I = pout.tag, J = complete_eu
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}
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2018-01-13 05:37:34 +03:00
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export toma.step
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2018-02-24 00:26:06 +03:00
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include mc_schemata
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2018-01-16 02:25:07 +03:00
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2018-02-24 02:14:24 +03:00
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attribute method = mc
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