2021-02-17 16:26:58 +03:00
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# Jacdac PADAUK
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2020-10-14 15:09:50 +03:00
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2021-04-27 03:51:50 +03:00
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This repository contains an implementation of Jacdac protocol and various services for the PADAUK family of microcontrollers,
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in particular the PADAUK PMS150C, PMS171B, and PMS131.
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2020-10-14 15:09:50 +03:00
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2021-04-27 03:51:50 +03:00
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* Read more about Jacdac at https://aka.ms/jacdac
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2021-02-17 16:26:58 +03:00
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2021-04-27 03:51:50 +03:00
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## Folders
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* `jd` contains implementation of Jacdac protocol
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* `services` contains implementation of various Jacdac services
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* `genid` contains a Win32 console application used to generate random Jacdac device identifiers (this is called by PADAUK writer software)
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* `scripts` contains various utility scripts (they are not currently used in build process)
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* `jm-*` contains project files and `main.asm` files for several Jacdac modules; they each include the base Jacdac implementation and a single service
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2021-05-25 18:51:51 +03:00
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If you create a new device folder, run `./check.sh` script to check for duplicate firmware IDs.
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2021-04-27 03:51:50 +03:00
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## Requirements
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To run (software) UART at 1mbaud (as required by Jacdac), the MCU has to run at 8MHz (or more, but PADAUK chips only do up to 8MHz).
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2022-04-21 15:21:59 +03:00
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Most PADAUK chips require LVD setting of 3.5V to operate at 8MHz, which implies supply of ~3.7V, which is not possible to get reliably
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from the Jacdac bus. Additionally, all Jacdac signalling uses 3.3V.
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2021-04-27 03:51:50 +03:00
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2021-04-27 21:45:59 +03:00
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We thus recommend chips that can run at 8MHz and 3.3V with low voltage detector set to 3.0V.
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2021-04-27 03:51:50 +03:00
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Additionally, we require the 16-bit timer, an 8-bit timer, 64 bytes of memory, and 1kW of program memory.
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This limits the chips to:
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2022-09-16 21:05:04 +03:00
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* PMS150C - $0.03; 64 bytes / 1kW - too small for many services!
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* PMS171B - $0.06; x8-bit timer, 8-bit ADC; 96 bytes / 1.5kW
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* PMS130 - 2x8-bit timer, 12-bit ADC; 88 bytes / 1.5kW
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* PMS131 - $0.08; 2x8-bit timer, 12-bit ADC; 96 bytes / 1.5kW
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* PFS172 - $0.08; 2x8-bit timer, 8-bit ADC; 128 bytes / 2kW; re-flashable
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* PFS122 - $0.06; 2x8-bit timer, 12-bit ADC; 128 bytes / 2kW; re-flashable
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We've had most success with PFS122.
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## Basic architecture
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The main loop of the program:
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* captures current time (based on T16 timer, which is set to increment every 4us)
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* sets "pending announce" bit every ~500ms (really 512*1024us)
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2022-03-31 20:27:20 +03:00
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* triggers transmission, when transmission timer expires (if there are pending TX bits)
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* does any service-specific processing (like probing the button)
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For reception,
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there is TM2 (8-bit timer) interrupt triggering every 8us (64T (instructions)) which checks if the Jacdac line was pulled low.
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(A pin interrupt could be possibly used instead, but the pin with interrupt is typically missing
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on smallest packages.)
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TM2 is the only source of interrupts ever enabled.
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Once the packet is received, it is processed by service-specific code (while still in interrupt context).
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There is typically a single pending TX bit allocated to each possible response to be sent from PADAUK,
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and the packet processing code sets that bit upon request received.
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The transmission code prepares data for outgoing packets based on pending TX bits
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after the initial low-pulse has been generated.
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This way, a single buffer is used for transmission and reception.
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Flags for different responses are independent, meaning there can be multiple pending responses
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(which may happen often when a client asks quickly for contest of several registers).
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### Stack
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There are 3 words of stack allocated.
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The main loop never uses any stack (never calls anything) while the interrupts are enabled.
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The RX process is triggered from interrupt and pushes current A/F registers, so it uses two words
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of stack.
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Then it sets up a nested interrupt which will eat one more word
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(which is immediately popped in timeout-handling code so it can do one level of calls).
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The TX code runs with interrupts disabled, so it can do 3 levels of calls (but only does 1 at the moment).
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### Reception
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Once the interrupt is triggered the reception process proceeds as follows:
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* set flag that we're in RX
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* setup TM2 to expire in ~136us
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* wait for line to come high
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* setup variables for reception
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* wait for first start bit (*)
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* setup TM2 to expire in 16T
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* get 8 bits of data
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* go to (*)
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The reception buffer will often overflow - the additional data is discarded in that case.
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When the interrupt is triggered when the RX flag is already set (timeout condition), the incoming packet is processed:
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* first, we check if the packet is an announce from a client, and if so we blink the status LED for 50us
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(this is before checking size or CRC, as these packets typically exceed our buffer size, but we are only interested
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in their headers anyways)
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* check if packet is addressed to current device
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* check if the packet didn't overflow the reception buffer
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* check CRC
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* check if this is a command
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* check if this is for current version of Jacdac (VNEXT flag not set)
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* if some of these conditions are not met, skip the packet
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* if ACK was requested, record that we need to send ACK
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* process packet according to control or custom service logic, setting various pending TX flags
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* reset TM2 back to the 8us period
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* return from interrupt
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### Transmission
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The transmission code performs the following steps:
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* disables interrupts
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* if the line is already low (TX/RX race detected) it jumps to the interrupt handler
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* pulls the line low
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* fills the device id field of outgoing packet
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* pull the line high
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* set TM2 for ~50us
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* prepare outgoing packet based on pending TX bits
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* compute CRC (CRC of packet size and device id is pre-computed by genid)
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* wait for TM2 to expire
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* transmit bytes
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* send final break
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* reset TM2 back for the 8us
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* enable interrupts
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* go back to main loop
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2020-10-14 15:09:50 +03:00
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2020-10-14 15:25:30 +03:00
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## Programming
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2021-04-27 03:51:50 +03:00
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To build programs you'll need to obtain the [PADAUK IDE](http://www.padauk.com.tw/en/technical/index.aspx?kind=26).
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To flash the microcontroller you'll need to also download the program writer and obtain a physical hardware programmer.
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2020-10-14 15:09:50 +03:00
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2021-04-30 02:16:41 +03:00
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The following warnings are expected:
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```
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...\jdheader.asm(...): The calculation of Stack maybe error !
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...\jdheader.asm(...): The code is overlapped. [FPPA 0, Interrupt] : ... to ...
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```
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2020-10-14 15:09:50 +03:00
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## Contributing
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This project welcomes contributions and suggestions. Most contributions require you to agree to a
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Contributor License Agreement (CLA) declaring that you have the right to, and actually do, grant us
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the rights to use your contribution. For details, visit https://cla.opensource.microsoft.com.
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When you submit a pull request, a CLA bot will automatically determine whether you need to provide
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a CLA and decorate the PR appropriately (e.g., status check, comment). Simply follow the instructions
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provided by the bot. You will only need to do this once across all repos using our CLA.
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This project has adopted the [Microsoft Open Source Code of Conduct](https://opensource.microsoft.com/codeofconduct/).
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For more information see the [Code of Conduct FAQ](https://opensource.microsoft.com/codeofconduct/faq/) or
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contact [opencode@microsoft.com](mailto:opencode@microsoft.com) with any additional questions or comments.
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## Trademarks
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This project may contain trademarks or logos for projects, products, or services. Authorized use of Microsoft
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trademarks or logos is subject to and must follow
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[Microsoft's Trademark & Brand Guidelines](https://www.microsoft.com/en-us/legal/intellectualproperty/trademarks/usage/general).
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Use of Microsoft trademarks or logos in modified versions of this project must not cause confusion or imply Microsoft sponsorship.
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Any use of third-party trademarks or logos are subject to those third-party's policies.
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