stm32l4-specific code
This commit is contained in:
Michal Moskal
Родитель
4cb4b7fdd8
Коммит
0470ecfeba
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@ -4,7 +4,14 @@
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#include "pinnames.h"
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uint64_t hw_device_id(void) {
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#ifdef STM32WL
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#ifdef STM32L4
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static uint64_t b;
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if (b)
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return b;
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const uint8_t *hp = (const uint8_t *)0x1FFF7590;
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b = ((uint64_t)jd_hash_fnv1a(hp, 12) << 32) | ((uint64_t)jd_hash_fnv1a(hp + 1, 11));
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return b;
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#elif defined(STM32WL)
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static uint64_t b;
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if (b)
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return b;
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@ -11,6 +11,8 @@
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#include "stm32g0.h"
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#elif defined(STM32WL)
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#include "stm32wl.h"
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#elif defined(STM32L4)
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#include "stm32l4.h"
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#else
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#error "invalid CPU"
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#endif
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@ -59,7 +61,7 @@ void rtc_cancel_cb(void);
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#define DMA_FLAG_HT DMA_ISR_HTIF1
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#define DMA_FLAG_TE DMA_ISR_TEIF1
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#if defined(STM32G0) || defined(STM32WL)
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#if defined(STM32G0) || defined(STM32L)
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static inline void dma_clear_flag(int ch, int flag) {
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WRITE_REG(DMA1->IFCR, flag << (ch*4));
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}
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@ -26,7 +26,7 @@ static const struct TimDesc tims[] = {
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{TIM3, 1, RCC_APB1ENR_TIM3EN}, //
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{TIM14, 1, RCC_APB1ENR_TIM14EN}, //
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{TIM16, 2, RCC_APB2ENR_TIM16EN}, //
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#elif defined(STM32WL)
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#elif defined(STM32L)
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#define APB1ENR APB1ENR1
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// TODO LPTIM...
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{TIM1, 2, RCC_APB2ENR_TIM1EN}, //
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@ -87,6 +87,11 @@ static const struct PinPWM pins[] = {
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{PA_3, 4, LL_GPIO_AF_1, TIM2},
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{PB_10, 3, LL_GPIO_AF_1, TIM2},
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// ...
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#elif defined(STM32L4)
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{PA_0, 1, LL_GPIO_AF_1, TIM2},
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{PA_3, 4, LL_GPIO_AF_1, TIM2},
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{PB_10, 3, LL_GPIO_AF_1, TIM2},
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// ...
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#else
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#error "missing"
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#endif
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106
stm32/uart.c
106
stm32/uart.c
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@ -16,6 +16,14 @@
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#define IRQHandler USART2_IRQHandler
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#define LL_DMAMUX_REQ_USARTx_RX LL_DMAMUX_REQ_USART2_RX
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#define LL_DMAMUX_REQ_USARTx_TX LL_DMAMUX_REQ_USART2_TX
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#elif USART_IDX == 4
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#define USARTx UART4
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#define IRQn UART4_IRQn
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#define IRQHandler UART4_IRQHandler
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#define LL_DMAMUX_REQ_USARTx_RX LL_DMAMUX_REQ_UART4_RX
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#define LL_DMAMUX_REQ_USARTx_TX LL_DMAMUX_REQ_UART4_TX
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//#define LL_DMAMUX_REQ_USARTx_RX 2
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//#define LL_DMAMUX_REQ_USARTx_TX 2
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#else
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#error "bad usart"
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#endif
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@ -24,6 +32,17 @@
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#define DMA_IRQn DMA1_Ch4_5_DMAMUX1_OVR_IRQn
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#define DMA_Handler DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler
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#define NEW_UART 1
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#elif defined(STM32L4)
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#define DMA_IRQn DMA2_Channel3_IRQn
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#define DMA_IRQn_2 DMA2_Channel5_IRQn
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#define DMA_CH_TX LL_DMA_CHANNEL_3
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#define DMA_CH_RX LL_DMA_CHANNEL_5
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#define DMA_ISR_TC_TX DMA_ISR_TCIF3
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#define DMA_ISR_TE_TX DMA_ISR_TEIF3
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#define DMA_ISR_TC_RX DMA_ISR_TCIF5
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#define DMA_ISR_TE_RX DMA_ISR_TEIF5
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#define DMAx DMA2
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#define NEW_UART 1
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#elif defined(STM32WL)
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#define DMA_IRQn DMA1_Channel4_IRQn
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#define DMA_IRQn_2 DMA1_Channel5_IRQn
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@ -34,6 +53,22 @@
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#define NEW_UART 0
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#endif
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#ifndef DMA_CH_TX
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#define DMA_CH_TX LL_DMA_CHANNEL_4
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#define DMA_ISR_TC_TX DMA_ISR_TCIF4
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#define DMA_ISR_TE_TX DMA_ISR_TEIF4
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#endif
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#ifndef DMA_CH_RX
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#define DMA_CH_RX LL_DMA_CHANNEL_5
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#define DMA_ISR_TC_RX DMA_ISR_TCIF5
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#define DMA_ISR_TE_RX DMA_ISR_TEIF5
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#endif
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#ifndef DMAx
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#define DMAx DMA1
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#endif
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// DMA Channel 4 - TX
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// DMA Channel 5 - RX
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@ -60,11 +95,11 @@ static void uartOwnsPin(int doesIt) {
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}
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void uart_disable() {
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LL_DMA_ClearFlag_GI5(DMA1);
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LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_5);
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LL_DMA_ClearFlag_GI5(DMAx);
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LL_DMA_DisableChannel(DMAx, DMA_CH_RX);
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LL_DMA_ClearFlag_GI4(DMA1);
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LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_4);
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LL_DMA_ClearFlag_GI3(DMAx);
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LL_DMA_DisableChannel(DMAx, DMA_CH_TX);
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LL_USART_Disable(USARTx);
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@ -73,13 +108,13 @@ void uart_disable() {
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}
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void DMA_Handler(void) {
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uint32_t isr = DMA1->ISR;
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uint32_t isr = DMAx->ISR;
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// DMESG("DMA irq %x", isr);
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// DMESG("DMA irq %x", (unsigned) isr);
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if (isr & (DMA_ISR_TCIF5 | DMA_ISR_TEIF5)) {
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if (isr & (DMA_ISR_TC_RX | DMA_ISR_TE_RX)) {
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uart_disable();
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if (isr & DMA_ISR_TCIF5) {
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if (isr & DMA_ISR_TC_RX) {
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// overrun?
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// DMESG("USARTx RX OK, but how?!");
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jd_rx_completed(-1);
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@ -89,12 +124,12 @@ void DMA_Handler(void) {
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}
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}
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if (isr & (DMA_ISR_TCIF4 | DMA_ISR_TEIF4)) {
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LL_DMA_ClearFlag_GI4(DMA1);
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LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_4);
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if (isr & (DMA_ISR_TC_TX | DMA_ISR_TE_TX)) {
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LL_DMA_ClearFlag_GI3(DMAx);
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LL_DMA_DisableChannel(DMAx, DMA_CH_TX);
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int errCode = 0;
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if (isr & DMA_ISR_TCIF4) {
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if (isr & DMA_ISR_TC_TX) {
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while (!LL_USART_IsActiveFlag_TC(USARTx))
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;
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// the standard BRK signal is too short - it's 10uS - to be detected as break at least on NRF52
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@ -130,8 +165,20 @@ void DMA1_Channel5_IRQHandler(void) {
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}
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#endif
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#ifdef STM32L4
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void DMA2_Channel3_IRQHandler(void) {
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DMA_Handler();
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}
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void DMA2_Channel5_IRQHandler(void) {
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DMA_Handler();
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}
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#endif
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static void DMA_Init(void) {
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DMA_CLK_ENABLE();
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#ifdef __HAL_RCC_DMA2_CLK_ENABLE
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__HAL_RCC_DMA2_CLK_ENABLE();
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#endif
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NVIC_SetPriority(DMA_IRQn, IRQ_PRIORITY_UART);
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NVIC_EnableIRQ(DMA_IRQn);
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@ -152,6 +199,9 @@ static void USART_UART_Init(void) {
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#elif USART_IDX == 1
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LL_RCC_SetUSARTClockSource(LL_RCC_USART1_CLKSOURCE_HSI);
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__HAL_RCC_USART1_CLK_ENABLE();
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#elif USART_IDX == 4
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LL_RCC_SetUSARTClockSource(LL_RCC_UART4_CLKSOURCE_HSI);
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__HAL_RCC_UART4_CLK_ENABLE();
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#else
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#error "bad usart"
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#endif
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@ -167,9 +217,9 @@ static void USART_UART_Init(void) {
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/* USART_RX Init */
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#if NEW_UART
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LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_5, LL_DMAMUX_REQ_USARTx_RX);
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LL_DMA_SetPeriphRequest(DMAx, DMA_CH_RX, LL_DMAMUX_REQ_USARTx_RX);
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#endif
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LL_DMA_ConfigTransfer(DMA1, LL_DMA_CHANNEL_5,
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LL_DMA_ConfigTransfer(DMAx, DMA_CH_RX,
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LL_DMA_DIRECTION_PERIPH_TO_MEMORY | //
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LL_DMA_PRIORITY_HIGH | //
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LL_DMA_MODE_NORMAL | //
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@ -179,9 +229,9 @@ static void USART_UART_Init(void) {
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LL_DMA_MDATAALIGN_BYTE);
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/* USART_TX Init */
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#if NEW_UART
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LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_4, LL_DMAMUX_REQ_USARTx_TX);
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LL_DMA_SetPeriphRequest(DMAx, DMA_CH_TX, LL_DMAMUX_REQ_USARTx_TX);
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#endif
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LL_DMA_ConfigTransfer(DMA1, LL_DMA_CHANNEL_4,
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LL_DMA_ConfigTransfer(DMAx, DMA_CH_TX,
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LL_DMA_DIRECTION_MEMORY_TO_PERIPH | //
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LL_DMA_PRIORITY_HIGH | //
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LL_DMA_MODE_NORMAL | //
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@ -195,10 +245,10 @@ static void USART_UART_Init(void) {
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NVIC_EnableIRQ(IRQn);
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/* Enable DMA transfer complete/error interrupts */
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LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_4);
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LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_4);
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LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_5);
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LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_5);
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LL_DMA_EnableIT_TC(DMAx, DMA_CH_TX);
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LL_DMA_EnableIT_TE(DMAx, DMA_CH_TX);
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LL_DMA_EnableIT_TC(DMAx, DMA_CH_RX);
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LL_DMA_EnableIT_TE(DMAx, DMA_CH_RX);
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#if NEW_UART
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USARTx->CR1 = LL_USART_DATAWIDTH_8B | LL_USART_PARITY_NONE | LL_USART_OVERSAMPLING_16 |
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@ -247,7 +297,7 @@ int uart_wait_high() {
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}
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int uart_start_tx(const void *data, uint32_t numbytes) {
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// DMESG("tx %d", numbytes);
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// DMESG("tx %d", (int)numbytes);
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exti_disable(PIN_MASK(UART_PIN));
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exti_clear_falling(PIN_MASK(UART_PIN));
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// We assume EXTI runs at higher priority than us
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@ -284,9 +334,9 @@ int uart_start_tx(const void *data, uint32_t numbytes) {
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while (!(LL_USART_IsActiveFlag_TEACK(USARTx)))
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;
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LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_4, (uint32_t)data, (uint32_t) & (USARTx->TDR),
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LL_DMA_ConfigAddresses(DMAx, DMA_CH_TX, (uint32_t)data, (uint32_t) & (USARTx->TDR),
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LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
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LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_4, numbytes);
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LL_DMA_SetDataLength(DMAx, DMA_CH_TX, numbytes);
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LL_USART_EnableDMAReq_TX(USARTx);
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// to here, it's about 1.3us
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@ -294,7 +344,7 @@ int uart_start_tx(const void *data, uint32_t numbytes) {
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target_wait_us(45);
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// The spec requires min of 50us and max of 189us.
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LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_4);
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LL_DMA_EnableChannel(DMAx, DMA_CH_TX);
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return 0;
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}
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@ -311,11 +361,11 @@ void uart_start_rx(void *data, uint32_t maxbytes) {
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while (!(LL_USART_IsActiveFlag_REACK(USARTx)))
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;
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LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_5, (uint32_t) & (USARTx->RDR), (uint32_t)data,
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LL_DMA_ConfigAddresses(DMAx, DMA_CH_RX, (uint32_t) & (USARTx->RDR), (uint32_t)data,
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LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
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LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_5, maxbytes);
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LL_DMA_SetDataLength(DMAx, DMA_CH_RX, maxbytes);
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LL_USART_EnableDMAReq_RX(USARTx);
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LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_5);
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LL_DMA_EnableChannel(DMAx, DMA_CH_RX);
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exti_disable(PIN_MASK(UART_PIN));
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exti_clear_falling(PIN_MASK(UART_PIN));
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@ -325,7 +375,7 @@ void uart_start_rx(void *data, uint32_t maxbytes) {
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void IRQHandler(void) {
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// DMESG("irq handler");
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// pulse_log_pin();
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uint32_t dataLeft = LL_DMA_GetDataLength(DMA1, LL_DMA_CHANNEL_5);
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uint32_t dataLeft = LL_DMA_GetDataLength(DMAx, DMA_CH_RX);
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uart_disable();
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jd_rx_completed(dataLeft);
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}
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