diff --git a/bl/blutils.c b/bl/blutils.c
index 19db71b..98455a0 100644
--- a/bl/blutils.c
+++ b/bl/blutils.c
@@ -5,7 +5,7 @@ void target_wait_cycles(int n) {
     __asm__ __volatile__(".syntax unified\n"
                          "1:              \n"
                          "   subs %0, #1   \n" // subtract 1 from %0 (n)
-#if defined(STM32G0) || defined(STM32WL)
+#if defined(STM32G0) || defined(STM32L)
                          "  nop  \n"
 #endif
                          "   bne 1b       \n" // if result is not 0 jump to 1
@@ -16,7 +16,7 @@ void target_wait_cycles(int n) {
 }
 
 void target_wait_us(uint32_t n) {
-#if defined(STM32G0) || defined(STM32F0) || defined(STM32WL)
+#if defined(STM32G0) || defined(STM32F0) || defined(STM32L)
     n = n * CPU_MHZ >> 2;
 #else
 #error "define clock rate"
diff --git a/src/blhw.h b/src/blhw.h
index b475b47..e09bef0 100644
--- a/src/blhw.h
+++ b/src/blhw.h
@@ -77,7 +77,7 @@ struct app_top_handlers {
 #if defined(STM32G0)
 #define OTP_DEVICE_ID_ADDR (0x1FFF7000 + 1024 - 8)
 #define APP_DEVICE_ID *(uint64_t *)OTP_DEVICE_ID_ADDR
-#elif defined(STM32WL)
+#elif defined(STM32L)
 #define APP_DEVICE_ID use hw_device_id
 #else
 #define APP_DEVICE_ID app_dev_info.device_id
diff --git a/src/namestore.c b/src/namestore.c
index b9136db..7b7d1cd 100644
--- a/src/namestore.c
+++ b/src/namestore.c
@@ -3,7 +3,7 @@
 // (not used)
 
 // STM32G0/WL require 8-byte aligned flash writes
-#if !defined(STM32G0) && !defined(STM32WL)
+#if !defined(STM32G0) && !defined(STM32L)
 
 #define MAGIC 0xe233b285
 #define SETTINGS_SIZE 1024
diff --git a/stm32/adc.c b/stm32/adc.c
index 388e996..671116e 100644
--- a/stm32/adc.c
+++ b/stm32/adc.c
@@ -3,11 +3,11 @@
 
 static bool adc_calibrated;
 
-#ifdef STM32WL
+#ifdef STM32L
 #define ADC1 ADC
 #endif
 
-#if defined(STM32G0) || defined(STM32WL)
+#if defined(STM32G0) || defined(STM32L)
 #define NEW_ADC 1
 #else
 #define NEW_ADC 0
@@ -32,7 +32,7 @@ uint16_t adc_convert(void) {
     } else
         JD_PANIC();
 
-#if STM32WL
+#if STM32L
     while (LL_ADC_IsActiveFlag_EOS(ADC1) == 0)
         ;
     LL_ADC_ClearFlag_EOS(ADC1);
@@ -165,7 +165,7 @@ void adc_init_random(void) {
 
     set_temp_ref(1);
     ADC1->CFGR1 = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
-#ifdef STM32WL
+#ifdef STM32L
     ADC1->CFGR2 = LL_ADC_CLOCK_SYNC_PCLK_DIV4;
 #endif
 
@@ -251,7 +251,7 @@ uint16_t adc_read_temp(void) {
     // 310 = 2.5mV/C * 100C * (1<<12) / 3300mV
     // 30/33 is because the TS_CAL1 is taken at 3.0V VCC and we run at 3.3V
     return ((130 - 30) * (r - (TS_CAL1 * 30 / 33))) / 310 + 30;
-#elif defined(STM32WL)
+#elif defined(STM32L)
     return __LL_ADC_CALC_TEMPERATURE(3300, r, LL_ADC_RESOLUTION_12B);
 #else
 #error "no temp"
diff --git a/stm32/dspi.c b/stm32/dspi.c
index 06ae518..28d9fab 100644
--- a/stm32/dspi.c
+++ b/stm32/dspi.c
@@ -284,7 +284,7 @@ void px_init(int light_type) {
     if (light_type & LIGHT_TYPE_APA_MASK)
         pin_setup_output_af(PIN_ASCK, PIN_AF);
 
-#if defined(STM32G0) || defined(STM32WL)
+#if defined(STM32G0) || defined(STM32L)
     LL_DMA_SetPeriphRequest(DMA1, DMA_CH_TX, LL_DMAMUX_REQ_SPIx_TX);
 #endif
 
diff --git a/stm32/duart.c b/stm32/duart.c
index 76eb709..ab960ab 100644
--- a/stm32/duart.c
+++ b/stm32/duart.c
@@ -4,7 +4,7 @@
 
 #define RX_BUFFER_SIZE 512
 
-#if defined(STM32G0) || defined(STM32WL)
+#if defined(STM32G0) || defined(STM32L)
 #define NEW_UART 1
 #else
 #error "F0 not (yet?) supported for duplex UART"
@@ -22,7 +22,7 @@
 #error "bad usart"
 #endif
 
-#if defined(STM32WL)
+#if defined(STM32L)
 #define TX_AF LL_GPIO_AF_7
 #define RX_AF LL_GPIO_AF_7
 #elif defined(STM32G0)
@@ -47,7 +47,7 @@
 #define DMA_IRQn DMA1_Channel2_3_IRQn
 #define DUART_DMA_Handler DMA1_Channel2_3_IRQHandler
 #define NEW_UART 1
-#elif defined(STM32WL)
+#elif defined(STM32L)
 #define DMA_IRQn DMA1_Channel2_IRQn
 #define DMA_IRQn_2 DMA1_Channel3_IRQn
 #define NEW_UART 1
@@ -105,7 +105,7 @@ void DUART_DMA_Handler(void) {
     }
 }
 
-#ifdef STM32WL
+#ifdef STM32L
 void DMA1_Channel2_IRQHandler(void) {
     DUART_DMA_Handler();
 }
@@ -128,7 +128,7 @@ void duart_init(data_cb_t cb) {
 
 #if DUPLEX_UART == 2
     __HAL_RCC_USART2_CLK_ENABLE();
-#ifdef STM32WL
+#ifdef STM32L
     LL_RCC_SetUSARTClockSource(LL_RCC_USART2_CLKSOURCE_HSI);
 #elif !defined(DISABLE_PLL)
 #error "PLL not supported"
diff --git a/stm32/exti.c b/stm32/exti.c
index 79eba6b..8be284a 100644
--- a/stm32/exti.c
+++ b/stm32/exti.c
@@ -3,7 +3,7 @@
 static cb_t callbacks[16];
 
 static void _check_line(int ln) {
-#if defined(STM32F0) || defined(STM32WL)
+#if defined(STM32F0) || defined(STM32L)
     LL_EXTI_ClearFlag_0_31(1 << ln);
 #else
     LL_EXTI_ClearRisingFlag_0_31(1 << ln);
@@ -14,7 +14,7 @@ static void _check_line(int ln) {
 
 #if defined(STM32G0)
 #define EXTI_LINES() (EXTI->FPR1 | EXTI->RPR1)
-#elif defined(STM32WL)
+#elif defined(STM32L)
 #define EXTI_LINES() (EXTI->PR1)
 #else
 #define EXTI_LINES() (EXTI->PR)
@@ -24,7 +24,7 @@ static void _check_line(int ln) {
     if (lines & (1 << (ln)))                                                                       \
     _check_line(ln)
 
-#ifdef STM32WL
+#ifdef STM32L
 #define SINGLE(name, ln)                                                                           \
     void name(void) {                                                                              \
         rtc_sync_time();                                                                           \
@@ -94,7 +94,7 @@ void exti_set_callback(uint8_t pin, cb_t callback, uint32_t flags) {
 
     if (pin >> 4 > 2)
         JD_PANIC();
-#if defined(STM32F0) || defined(STM32WL)
+#if defined(STM32F0) || defined(STM32L)
     extiport = pin >> 4;
 #elif defined(STM32G0)
     extiport = cfgs[pin >> 4];
@@ -107,7 +107,7 @@ void exti_set_callback(uint8_t pin, cb_t callback, uint32_t flags) {
 #ifdef STM32F0
     uint32_t line = (pos >> 2) | ((pos & 3) << 18);
     LL_SYSCFG_SetEXTISource(extiport, line);
-#elif defined(STM32WL)
+#elif defined(STM32L)
     uint32_t line = (pos >> 2) | (0xF << (16 + (4 * (pos & 3))));
     LL_SYSCFG_SetEXTISource(extiport, line);
 #else
@@ -126,7 +126,7 @@ void exti_set_callback(uint8_t pin, cb_t callback, uint32_t flags) {
     NVIC_SetPriority(irq, IRQ_PRIORITY_EXTI);                                                      \
     NVIC_EnableIRQ(irq)
 
-#ifdef STM32WL
+#ifdef STM32L
     if (!NVIC_GetEnableIRQ(EXTI0_IRQn)) {
         SETUP(EXTI0_IRQn);
         SETUP(EXTI1_IRQn);
diff --git a/stm32/flash.c b/stm32/flash.c
index 10e70d5..ad2d67c 100644
--- a/stm32/flash.c
+++ b/stm32/flash.c
@@ -1,6 +1,6 @@
 #include "jdstm.h"
 
-#if defined(STM32G0) || defined(STM32WL)
+#if defined(STM32G0) || defined(STM32L)
 #define NEW_FLASH 1
 #else
 #define NEW_FLASH 0
diff --git a/stm32/i2c.c b/stm32/i2c.c
index 19494b5..07becd4 100644
--- a/stm32/i2c.c
+++ b/stm32/i2c.c
@@ -43,7 +43,7 @@
 #endif
 #endif
 
-#if defined(STM32G0) || defined(STM32WL)
+#if defined(STM32G0) || defined(STM32L)
 // 25.4.11 I2C_TIMINGR register configuration examples (G0 docs)
 // 32.4.10 in WL docs
 #if I2C_FAST_MODE
@@ -75,7 +75,7 @@ int i2c_init(void) {
 #define CYCLES_PER_MS (77 * cpu_mhz)
 #elif defined(STM32G0)
 #define CYCLES_PER_MS (100 * cpu_mhz) // TODO measure this!
-#elif defined(STM32WL)
+#elif defined(STM32L)
 #define CYCLES_PER_MS (100 * cpu_mhz) // TODO measure this!
 #else
 #error "measure CYCLES_PER_MS"
diff --git a/stm32/init.c b/stm32/init.c
index 977d010..175dc50 100644
--- a/stm32/init.c
+++ b/stm32/init.c
@@ -103,7 +103,8 @@ void clk_setup_pll(void) {
 #else
     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, LL_RCC_PLL_MUL_12);
 #endif
-#elif defined(STM32WL)
+#elif defined(STM32L)
+    // run at 48MHz
     LL_FLASH_SetLatency(LL_FLASH_LATENCY_2);
     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_1, 6, LL_RCC_PLLR_DIV_2);
 #else
@@ -138,7 +139,7 @@ uint32_t SystemCoreClock = HSI_MHZ * 1000000;
 #endif
 
 void clk_set_pll(int on) {
-#if defined(STM32WL) || !defined(DISABLE_PLL)
+#if defined(STM32L) || !defined(DISABLE_PLL)
     if (!on) {
         LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
         while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
@@ -169,7 +170,7 @@ void SystemInit(void) {
     LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA | LL_IOP_GRP1_PERIPH_GPIOB |
                             LL_IOP_GRP1_PERIPH_GPIOC);
     LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-#elif defined(STM32WL)
+#elif defined(STM32L)
     SCB->VTOR = FLASH_BASE; // needed?
     // LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG); - doesn't have?
     LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA | LL_AHB2_GRP1_PERIPH_GPIOB |
diff --git a/stm32/rtc.c b/stm32/rtc.c
index fdad46b..aacbae6 100644
--- a/stm32/rtc.c
+++ b/stm32/rtc.c
@@ -31,7 +31,7 @@ static ctx_t ctx_;
 #define RTC_IRQn RTC_TAMP_IRQn
 #define RTC_IRQHandler RTC_TAMP_IRQHandler
 #define EXTI_LINE LL_EXTI_LINE_19
-#elif defined(STM32WL)
+#elif defined(STM32L)
 #define RTC_IRQn RTC_Alarm_IRQn
 #define RTC_IRQHandler RTC_Alarm_IRQHandler
 #define EXTI_LINE LL_EXTI_LINE_17
@@ -118,7 +118,7 @@ static void rtc_set(ctx_t *ctx, uint32_t delta_us, cb_t f) {
     ctx->cb = f;
 
     LL_RTC_ALMA_Disable(RTC);
-#ifndef STM32WL
+#ifndef STM32L
     while (!LL_RTC_IsActiveFlag_ALRAW(RTC))
         ;
 #endif
@@ -163,7 +163,7 @@ void RTC_IRQHandler(void) {
 static void rtc_config(uint8_t p0, uint16_t p1) {
 #ifdef STM32G0
     LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR | LL_APB1_GRP1_PERIPH_RTC);
-#elif defined(STM32WL)
+#elif defined(STM32L)
     LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB);
     // LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB);
 #else
@@ -283,7 +283,7 @@ void rtc_set_to_seconds_and_standby() {
     }
 
     //    pin_setup_input(PA_0, -1);
-#if defined(STM32G0) || defined(STM32WL)
+#if defined(STM32G0) || defined(STM32L)
     LL_PWR_EnableGPIOPullDown(LL_PWR_GPIO_A, LL_PWR_GPIO_BIT_0);
     LL_PWR_EnablePUPDCfg();
 #endif
@@ -297,7 +297,7 @@ void rtc_set_to_seconds_and_standby() {
 }
 
 bool rtc_check_standby(void) {
-#if defined(STM32G0) || defined(STM32WL)
+#if defined(STM32G0) || defined(STM32L)
     LL_PWR_DisablePUPDCfg();
 #endif
 
@@ -329,7 +329,7 @@ void rtc_sleep(bool forceShallow) {
     }
 
     rtc_set(&ctx_, usec, f);
-#if defined(STM32G0) || defined(STM32WL)
+#if defined(STM32G0) || defined(STM32L)
     LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1);
 #else
     LL_PWR_SetPowerMode(LL_PWR_MODE_STOP_LPREGU);
@@ -348,7 +348,7 @@ void rtc_sleep(bool forceShallow) {
 }
 
 void rtc_deepsleep(void) {
-#ifdef STM32WL
+#ifdef STM32L
     LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1);
 #endif
     LL_LPM_EnableDeepSleep();
diff --git a/stm32/spidef.h b/stm32/spidef.h
index f6949eb..6ad1df2 100644
--- a/stm32/spidef.h
+++ b/stm32/spidef.h
@@ -10,7 +10,7 @@
 #endif
 #elif defined(STM32F031x6) || defined(STM32F030x4) || !defined(SPI2)
 #define SPI_IDX 1
-#elif defined(STM32WL)
+#elif defined(STM32L)
 #if PIN_ASCK == PB_13
 #define SPI_IDX 2
 #else
@@ -58,7 +58,7 @@ STATIC_ASSERT(PIN_AMISO == PA_6);
 
 #elif SPI_IDX == 2
 #define SPI_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#if defined(STM32WL)
+#if defined(STM32L)
 #define PIN_AF LL_GPIO_AF_5
 #elif defined(STM32G031xx)
 #if PIN_ASCK == PA_0
@@ -98,7 +98,7 @@ STATIC_ASSERT(PIN_AMISO == -1);
 #define DMA_IRQn DMA1_Channel1_IRQn
 #define DMA_Handler DMA1_Channel1_IRQHandler
 #endif
-#elif defined(STM32WL)
+#elif defined(STM32L)
 #define DMA_CH_TX LL_DMA_CHANNEL_1
 #define DMA_CH_RX LL_DMA_CHANNEL_2
 #define DMA_IRQn DMA1_Channel1_IRQn
diff --git a/stm32/stm32wl.h b/stm32/stm32wl.h
index d360618..4a5db6a 100644
--- a/stm32/stm32wl.h
+++ b/stm32/stm32wl.h
@@ -4,6 +4,7 @@
 #include "board.h"
 
 #define STM32WL 1
+#define STM32L 1
 
 #include "stm32wlxx_hal_rcc.h"
 
diff --git a/stm32/target_utils.c b/stm32/target_utils.c
index 3bae88d..f5ba5b2 100644
--- a/stm32/target_utils.c
+++ b/stm32/target_utils.c
@@ -7,7 +7,7 @@ void target_wait_cycles(int n) {
                          "   subs %0, #1   \n" // subtract 1 from %0 (n)
 #if defined(STM32G0)
                          "  nop  \n"
-#elif defined(STM32WL)
+#elif defined(STM32L)
                          "  nop  \n"
                          "  nop  \n"
                          "  nop  \n"
@@ -22,7 +22,7 @@ void target_wait_cycles(int n) {
 void target_wait_us(uint32_t n) {
 #if defined(STM32G0) || defined(STM32F0)
     n = n * (cpu_mhz >> 2);
-#elif defined(STM32WL)
+#elif defined(STM32L)
     n = n * (cpu_mhz >> 3);
 #else
 #error "define clock rate"
diff --git a/stm32/tim.c b/stm32/tim.c
index b51c57c..d24aa8b 100644
--- a/stm32/tim.c
+++ b/stm32/tim.c
@@ -85,7 +85,7 @@ void tim_init(void) {
     LL_TIM_DisableARRPreload(TIMx);
     LL_TIM_SetClockSource(TIMx, LL_TIM_CLOCKSOURCE_INTERNAL);
     LL_TIM_SetTriggerOutput(TIMx, LL_TIM_TRGO_RESET);
-#if defined(STM32G0) || defined(STM32WL)
+#if defined(STM32G0) || defined(STM32L)
     LL_TIM_SetTriggerOutput2(TIMx, LL_TIM_TRGO2_RESET);
 #endif
     LL_TIM_DisableMasterSlaveMode(TIMx);