microsoft
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llvm-mctoll
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[NFC] Finish clang-tidy cleanup 

- Follow up on previous clang-tidy changes. Finish up clang-tidy changes
  of remaining project sources.
- Add support to enable clang-tidy checks on project source files
  by adding a new cmake variable viz., MCTOLL_CLANG_TIDY, that can be
  specified while configuring cmake.
- Update README.md
This commit is contained in:
Bharadwaj Yadavalli 2022-09-22 11:30:27 -04:00
Родитель 59290c9353
Коммит 5c34f03bb0
Не найден ключ, соответствующий данной подписи
Идентификатор ключа GPG: 69398DE47D4148B1
30 изменённых файлов: 1279 добавлений и 1257 удалений
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4
.clang-format
Просмотреть файл

@ -68,7 +68,7 @@ ForEachMacros:
- BOOST_FOREACH
IncludeBlocks: Preserve
IncludeCategories:
- Regex: '^"(llvm|llvm-c|clang|clang-c)/'
- Regex: '^"(llvm-|llvm|clang-c|clang)/'
Priority: 2
SortPriority: 0
- Regex: '^(<|"(gtest|gmock|isl|json)/)'
@ -105,7 +105,7 @@ PenaltyExcessCharacter: 1000000
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Right
ReflowComments: true
SortIncludes: CaseInsensitive
SortIncludes: CaseSensitive
SortUsingDeclarations: true
SpaceAfterCStyleCast: false
SpaceAfterLogicalNot: false

2
ARM/ARMArgumentRaiser.cpp
Просмотреть файл

@ -163,7 +163,7 @@ bool ARMArgumentRaiser::raiseArgs() {
ArgIter != ArgEnd; ++ArgIter)
ArgIter->setName("arg." + std::to_string(ArgIdx++));
for (unsigned i = 0, End = RF->arg_size() + 1; i < End; ++i) {
for (unsigned Idx = 0, End = RF->arg_size() + 1; Idx < End; ++Idx) {
Align ALG(32);
MFI->CreateStackObject(32, ALG, false);
}

28
ARM/ARMCreateJumpTable.cpp
Просмотреть файл

@ -85,8 +85,8 @@ MachineBasicBlock *ARMCreateJumpTable::checkJumptableBB(MachineFunction &MF) {
}
}
for (unsigned int i = 0; i < Instrs.size(); i++) {
MBB->erase(Instrs[i]);
for (unsigned int Idx = 0; Idx < Instrs.size(); Idx++) {
MBB->erase(Instrs[Idx]);
}
}
return JumpTableBB;
@ -103,16 +103,16 @@ bool ARMCreateJumpTable::updatetheBranchInst(MachineBasicBlock &MBB) {
MachineInstr &CurMI = (*MIIter);
if (CurMI.getOpcode() == ARM::Bcc) {
for (unsigned int i = 0; i < CurMI.getNumOperands(); i++) {
LLVM_DEBUG(CurMI.getOperand(i).dump());
for (unsigned int Idx = 0; Idx < CurMI.getNumOperands(); Idx++) {
LLVM_DEBUG(CurMI.getOperand(Idx).dump());
}
BuildMI(&MBB, DebugLoc(), TII->get(ARM::B)).add(CurMI.getOperand(0));
Instrs.push_back(&CurMI);
}
}
for (unsigned int i = 0; i < Instrs.size(); i++) {
MBB.erase(Instrs[i]);
for (unsigned int Idx = 0; Idx < Instrs.size(); Idx++) {
MBB.erase(Instrs[Idx]);
}
return true;
}
@ -122,8 +122,8 @@ bool ARMCreateJumpTable::raiseMaichineJumpTable(MachineFunction &MF) {
// A vector to record MBBs that need to be erased upon jump table creation.
std::vector<MachineBasicBlock *> MBBsToBeErased;
std::map<uint64_t, MCInstOrData> mcInstMapData;
MCInstRaiser::const_mcinst_iter iter_in;
std::map<uint64_t, MCInstOrData> MCInstMapData;
MCInstRaiser::const_mcinst_iter IterIn;
// Save the ADDri and Calculate the start address of data.
for (MachineBasicBlock &JmpTblBaseCalcMBB : MF) {
@ -156,10 +156,10 @@ bool ARMCreateJumpTable::raiseMaichineJumpTable(MachineFunction &MF) {
assert(
MCIR != nullptr &&
"Current function machine instruction raiser wasn't initialized!");
for (iter_in = MCIR->const_mcinstr_begin();
iter_in != MCIR->const_mcinstr_end(); iter_in++) {
MCInstOrData mcInstorData = iter_in->second;
if (mcInstorData.isData() && mcInstorData.getData() > 0) {
for (IterIn = MCIR->const_mcinstr_begin();
IterIn != MCIR->const_mcinstr_end(); IterIn++) {
MCInstOrData MCInstorData = IterIn->second;
if (MCInstorData.isData() && MCInstorData.getData() > 0) {
// The 16 is 8 + 8. The first 8 is the PC offset, the second 8 is
// the immediate of current instruction.
// If the current library is position-independent, the offset should
@ -167,9 +167,9 @@ bool ARMCreateJumpTable::raiseMaichineJumpTable(MachineFunction &MF) {
// If the current library is not position-independent, the offset
// should be CASE VALUE - text section address.
uint64_t Offset =
IsFPIC ? (mcInstorData.getData() +
IsFPIC ? (MCInstorData.getData() +
MCIR->getMCInstIndex(JmpTblOffsetCalcMI) + 16)
: (mcInstorData.getData() - MR->getTextSectionAddress());
: (MCInstorData.getData() - MR->getTextSectionAddress());
auto MBBNo = MCIR->getMBBNumberOfMCInstOffset(Offset, MF);
if (MBBNo != -1) {
MachineBasicBlock *MBB = MF.getBlockNumbered(MBBNo);

16
ARM/ARMEliminatePrologEpilog.cpp
Просмотреть файл

@ -41,8 +41,8 @@ bool ARMEliminatePrologEpilog::checkRegister(
for (; Iter < Instrs.end(); ++Iter) {
MachineInstr *MI = *Iter;
if (MI->mayStore()) {
for (unsigned i = 0; i < MI->getNumOperands(); i++) {
MachineOperand MO = MI->getOperand(i);
for (unsigned Idx = 0; Idx < MI->getNumOperands(); Idx++) {
MachineOperand MO = MI->getOperand(Idx);
// Compare the register number.
if (MO.isReg() && MO.getReg() == Reg)
@ -136,8 +136,8 @@ bool ARMEliminatePrologEpilog::eliminateProlog(MachineFunction &MF) const {
const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
std::vector<CalleeSavedInfo> CSI;
for (unsigned i = 0; CSRegs[i]; ++i) {
unsigned Reg = CSRegs[i];
for (unsigned Idx = 0; CSRegs[Idx]; ++Idx) {
unsigned Reg = CSRegs[Idx];
// Save register.
if (checkRegister(Reg, PrologInstrs)) {
@ -201,8 +201,8 @@ bool ARMEliminatePrologEpilog::eliminateProlog(MachineFunction &MF) const {
// Eliminate the instructions identified in function prologue
unsigned int DelInstSz = PrologInstrs.size();
for (unsigned int i = 0; i < DelInstSz; i++) {
FrontMBB.erase(PrologInstrs[i]);
for (unsigned int Idx = 0; Idx < DelInstSz; Idx++) {
FrontMBB.erase(PrologInstrs[Idx]);
}
return true;
@ -281,8 +281,8 @@ bool ARMEliminatePrologEpilog::eliminateEpilog(MachineFunction &MF) const {
// Eliminate the instructions identified in function epilogue
unsigned int DelInstSz = EpilogInstrs.size();
for (unsigned int i = 0; i < DelInstSz; i++) {
MBB.erase(EpilogInstrs[i]);
for (unsigned int Idx = 0; Idx < DelInstSz; Idx++) {
MBB.erase(EpilogInstrs[Idx]);
}
}

175
ARM/ARMFunctionPrototype.cpp
Просмотреть файл

@ -31,17 +31,18 @@ ARMFunctionPrototype::ARMFunctionPrototype() : MachineFunctionPass(ID) {}
ARMFunctionPrototype::~ARMFunctionPrototype() {}
/// Check the first reference of the reg is USE.
bool ARMFunctionPrototype::isUsedRegiser(unsigned reg,
const MachineBasicBlock &mbb) {
for (MachineBasicBlock::const_iterator ii = mbb.begin(), ie = mbb.end();
ii != ie; ++ii) {
const MachineInstr &mi = *ii;
for (MachineInstr::const_mop_iterator oi = mi.operands_begin(),
oe = mi.operands_end();
oi != oe; oi++) {
const MachineOperand &mo = *oi;
if (mo.isReg() && (mo.getReg() == reg))
return mo.isUse();
bool ARMFunctionPrototype::isUsedRegiser(unsigned Reg,
const MachineBasicBlock &MBB) {
for (MachineBasicBlock::const_iterator BegIter = MBB.begin(),
EndIter = MBB.end();
BegIter != EndIter; ++BegIter) {
const MachineInstr &MI = *BegIter;
for (MachineInstr::const_mop_iterator OpBegIter = MI.operands_begin(),
OpEndIter = MI.operands_end();
OpBegIter != OpEndIter; OpBegIter++) {
const MachineOperand &MO = *OpBegIter;
if (MO.isReg() && (MO.getReg() == Reg))
return MO.isUse();
}
}
@ -49,12 +50,12 @@ bool ARMFunctionPrototype::isUsedRegiser(unsigned reg,
}
/// Check the first reference of the reg is DEF.
void ARMFunctionPrototype::genParameterTypes(std::vector<Type *> &paramTypes) {
void ARMFunctionPrototype::genParameterTypes(std::vector<Type *> &ParamVec) {
assert(!MF->empty() && "The function body is empty!!!");
MF->getRegInfo().freezeReservedRegs(*MF);
LivePhysRegs liveInPhysRegs;
LivePhysRegs LiveInPhysRegs;
for (MachineBasicBlock &EMBB : *MF)
computeAndAddLiveIns(liveInPhysRegs, EMBB);
computeAndAddLiveIns(LiveInPhysRegs, EMBB);
// Walk the CFG DFS to discover first register usage
df_iterator_default_set<const MachineBasicBlock *, 16> Visited;
DenseMap<unsigned, bool> ArgObtain;
@ -62,26 +63,26 @@ void ARMFunctionPrototype::genParameterTypes(std::vector<Type *> &paramTypes) {
ArgObtain[ARM::R1] = false;
ArgObtain[ARM::R2] = false;
ArgObtain[ARM::R3] = false;
const MachineBasicBlock &fmbb = MF->front();
DenseMap<int, Type *> tarr;
int maxidx = -1; // When the maxidx is -1, means there is no argument.
const MachineBasicBlock &MBBFront = MF->front();
DenseMap<int, Type *> TyArr;
int MaxIdx = -1; // When the maxidx is -1, means there is no argument.
// Track register liveness on CFG.
for (const MachineBasicBlock *Mbb : depth_first_ext(&fmbb, Visited)) {
for (const MachineBasicBlock *Mbb : depth_first_ext(&MBBFront, Visited)) {
for (unsigned IReg = ARM::R0; IReg < ARM::R4; IReg++) {
if (!ArgObtain[IReg] && Mbb->isLiveIn(IReg)) {
for (MachineBasicBlock::const_iterator ii = Mbb->begin(),
ie = Mbb->end();
ii != ie; ++ii) {
const MachineInstr &LMI = *ii;
for (MachineBasicBlock::const_iterator BI = Mbb->begin(),
EI = Mbb->end();
BI != EI; ++BI) {
const MachineInstr &LMI = *BI;
auto RUses = LMI.uses();
auto ResIter =
const auto *ResIter =
std::find_if(RUses.begin(), RUses.end(),
[IReg](const MachineOperand &OP) -> bool {
return OP.isReg() && (OP.getReg() == IReg);
});
if (ResIter != RUses.end()) {
maxidx = IReg - ARM::R0;
tarr[maxidx] = getDefaultType();
MaxIdx = IReg - ARM::R0;
TyArr[MaxIdx] = getDefaultType();
break;
}
}
@ -90,70 +91,70 @@ void ARMFunctionPrototype::genParameterTypes(std::vector<Type *> &paramTypes) {
}
}
// The rest of function arguments are from stack.
for (MachineFunction::const_iterator mbbi = MF->begin(), mbbe = MF->end();
mbbi != mbbe; ++mbbi) {
const MachineBasicBlock &mbb = *mbbi;
for (MachineBasicBlock::const_iterator mii = mbb.begin(), mie = mbb.end();
mii != mie; ++mii) {
const MachineInstr &mi = *mii;
for (MachineFunction::const_iterator BegMBBIter = MF->begin(), EndMBBIter = MF->end();
BegMBBIter != EndMBBIter; ++BegMBBIter) {
const MachineBasicBlock &Mbb = *BegMBBIter;
for (MachineBasicBlock::const_iterator Mii = Mbb.begin(), Mie = Mbb.end();
Mii != Mie; ++Mii) {
const MachineInstr &Mi = *Mii;
// Match pattern like ldr r1, [fp, #8].
if (mi.getOpcode() == ARM::LDRi12 && mi.getNumOperands() > 2) {
const MachineOperand &mo = mi.getOperand(1);
const MachineOperand &mc = mi.getOperand(2);
if (mo.isReg() && mo.getReg() == ARM::R11 && mc.isImm()) {
if (Mi.getOpcode() == ARM::LDRi12 && Mi.getNumOperands() > 2) {
const MachineOperand &Mo = Mi.getOperand(1);
const MachineOperand &Mc = Mi.getOperand(2);
if (Mo.isReg() && Mo.getReg() == ARM::R11 && Mc.isImm()) {
// TODO: Need to check the imm is larger than 0 and it is align
// by 4(32 bit).
int imm = mc.getImm();
if (imm >= 0) {
int Imm = Mc.getImm();
if (Imm >= 0) {
// The start index of arguments on stack. If the library was
// compiled by clang, it starts from 2. If the library was compiled
// by GNU cross compiler, it starts from 1.
// FIXME: For now, we only treat that the library was complied by
// clang. We will enable the 'if condition' after we are able to
// identify the library was compiled by which compiler.
int idxoff = 2;
int Idxoff = 2;
if (true /* clang */)
idxoff = 2;
Idxoff = 2;
else /* gnu */
idxoff = 1;
Idxoff = 1;
int idx = imm / 4 - idxoff + 4; // Plus 4 is to guarantee the first
int Idx = Imm / 4 - Idxoff + 4; // Plus 4 is to guarantee the first
// stack argument index is after all
// of register arguments' indices.
if (maxidx < idx)
maxidx = idx;
tarr[idx] = getDefaultType();
if (MaxIdx < Idx)
MaxIdx = Idx;
TyArr[Idx] = getDefaultType();
}
}
}
}
}
for (int i = 0; i <= maxidx; ++i) {
if (tarr[i] == nullptr)
paramTypes.push_back(getDefaultType());
for (int Idx = 0; Idx <= MaxIdx; ++Idx) {
if (TyArr[Idx] == nullptr)
ParamVec.push_back(getDefaultType());
else
paramTypes.push_back(tarr[i]);
ParamVec.push_back(TyArr[Idx]);
}
}
/// Get all arguments types of current MachineFunction.
bool ARMFunctionPrototype::isDefinedRegiser(unsigned reg,
const MachineBasicBlock &mbb) {
for (MachineBasicBlock::const_reverse_iterator ii = mbb.rbegin(),
ie = mbb.rend();
ii != ie; ++ii) {
const MachineInstr &mi = *ii;
for (MachineInstr::const_mop_iterator oi = mi.operands_begin(),
oe = mi.operands_end();
oi != oe; oi++) {
const MachineOperand &mo = *oi;
if (mo.isReg() && (mo.getReg() == reg)) {
bool ARMFunctionPrototype::isDefinedRegiser(unsigned Reg,
const MachineBasicBlock &MBB) {
for (MachineBasicBlock::const_reverse_iterator Ii = MBB.rbegin(),
Ie = MBB.rend();
Ii != Ie; ++Ii) {
const MachineInstr &MI = *Ii;
for (MachineInstr::const_mop_iterator Oi = MI.operands_begin(),
Oe = MI.operands_end();
Oi != Oe; Oi++) {
const MachineOperand &MO = *Oi;
if (MO.isReg() && (MO.getReg() == Reg)) {
// The return register must not be tied to another register.
// If it was, it should not be return register.
if (mo.isTied())
if (MO.isTied())
return false;
return mo.isDef();
return MO.isDef();
}
}
}
@ -164,51 +165,51 @@ bool ARMFunctionPrototype::isDefinedRegiser(unsigned reg,
/// Get return type of current MachineFunction.
Type *ARMFunctionPrototype::genReturnType() {
// TODO: Need to track register liveness on CFG.
Type *retTy;
retTy = Type::getVoidTy(*CTX);
for (const MachineBasicBlock &mbb : *MF) {
if (mbb.succ_empty()) {
if (isDefinedRegiser(ARM::R0, mbb)) {
Type *RetTy;
RetTy = Type::getVoidTy(*CTX);
for (const MachineBasicBlock &MBB : *MF) {
if (MBB.succ_empty()) {
if (isDefinedRegiser(ARM::R0, MBB)) {
// TODO: Need to identify data type, int, long, float or double.
retTy = getDefaultType();
RetTy = getDefaultType();
break;
}
}
}
return retTy;
return RetTy;
}
Function *ARMFunctionPrototype::discover(MachineFunction &mf) {
Function *ARMFunctionPrototype::discover(MachineFunction &MachFunc) {
LLVM_DEBUG(dbgs() << "ARMFunctionPrototype start.\n");
MF = &mf;
Function &fn = const_cast<Function &>(mf.getFunction());
CTX = &fn.getContext();
MF = &MachFunc;
Function &Fn = const_cast<Function &>(MachFunc.getFunction());
CTX = &Fn.getContext();
std::vector<Type *> paramTys;
genParameterTypes(paramTys);
Type *retTy = genReturnType();
FunctionType *fnTy = FunctionType::get(retTy, paramTys, false);
std::vector<Type *> ParamTys;
genParameterTypes(ParamTys);
Type *RetTy = genReturnType();
FunctionType *FnTy = FunctionType::get(RetTy, ParamTys, false);
MachineModuleInfo &mmi = mf.getMMI();
Module *mdl = const_cast<Module *>(mmi.getModule());
mdl->getFunctionList().remove(&fn);
Function *pnfn =
Function::Create(fnTy, GlobalValue::ExternalLinkage, fn.getName(), mdl);
MachineModuleInfo &Mmi = MachFunc.getMMI();
Module *Mdl = const_cast<Module *>(Mmi.getModule());
Mdl->getFunctionList().remove(&Fn);
Function *Pnfn =
Function::Create(FnTy, GlobalValue::ExternalLinkage, Fn.getName(), Mdl);
// When run as FunctionPass, the Function must not be empty, so add
// EntryBlock at here.
BasicBlock::Create(pnfn->getContext(), "EntryBlock", pnfn);
BasicBlock::Create(Pnfn->getContext(), "EntryBlock", Pnfn);
LLVM_DEBUG(MF->dump());
LLVM_DEBUG(pnfn->dump());
LLVM_DEBUG(Pnfn->dump());
LLVM_DEBUG(dbgs() << "ARMFunctionPrototype end.\n");
return pnfn;
return Pnfn;
}
bool ARMFunctionPrototype::runOnMachineFunction(MachineFunction &mf) {
discover(mf);
bool ARMFunctionPrototype::runOnMachineFunction(MachineFunction &MachFunc) {
discover(MachFunc);
return true;
}
@ -218,7 +219,7 @@ bool ARMFunctionPrototype::runOnMachineFunction(MachineFunction &mf) {
extern "C" {
#endif
MachineFunctionPass *InitializeARMFunctionPrototype() {
MachineFunctionPass *initializeARMFunctionPrototype() {
return new ARMFunctionPrototype();
}

396
ARM/ARMInstructionSplitting.cpp
Просмотреть файл

@ -158,37 +158,29 @@ bool ARMInstructionSplitting::isShift_C(unsigned Opcode) {
/// Get the shift opcode in MI.
unsigned ARMInstructionSplitting::getShiftOpcode(ARM_AM::ShiftOpc SOpc,
unsigned OffSet) {
unsigned RetVal = 0;
switch (SOpc) {
case ARM_AM::asr: {
if (OffSet != 0)
return ARM::ASRi;
else
return ARM::ASRr;
}
case ARM_AM::lsl: {
if (OffSet != 0)
return ARM::LSLi;
else
return ARM::LSLr;
}
case ARM_AM::lsr: {
if (OffSet != 0)
return ARM::LSRi;
else
return ARM::LSRr;
}
case ARM_AM::ror: {
if (OffSet != 0)
return ARM::RORi;
else
return ARM::RORr;
}
case ARM_AM::asr:
RetVal = (OffSet != 0) ? ARM::ASRi : ARM::ASRr;
break;
case ARM_AM::lsl:
RetVal = (OffSet != 0) ? ARM::LSLi : ARM::LSLr;
break;
case ARM_AM::lsr:
RetVal = (OffSet != 0) ? ARM::LSRi : ARM::LSRr;
break;
case ARM_AM::ror:
RetVal = (OffSet != 0) ? ARM::RORi : ARM::RORr;
break;
case ARM_AM::rrx:
return ARM::RRX;
RetVal = ARM::RRX;
break;
case ARM_AM::no_shift:
default:
return 0;
RetVal = 0;
}
return RetVal;
}
MachineInstrBuilder &
@ -224,14 +216,14 @@ MachineInstr *ARMInstructionSplitting::splitLDRSTRPreImm(MachineBasicBlock &MBB,
// MI is splitted into 2 instructions.
// So get Metadata for the first instruction.
ConstantAsMetadata *CMD_fst = ConstantAsMetadata::get(
ConstantAsMetadata *CMDFir = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 0, false)));
MDNode *N_fst = MDNode::get(*CTX, CMD_fst);
MDNode *MDNFir = MDNode::get(*CTX, CMDFir);
// Get Metadata for the second instruction.
ConstantAsMetadata *CMD_sec = ConstantAsMetadata::get(
ConstantAsMetadata *CMDSec = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 1, false)));
MDNode *N_sec = MDNode::get(*CTX, CMD_sec);
MDNode *MDNSec = MDNode::get(*CTX, CMDSec);
unsigned NewOpc = getLoadStoreOpcode(MI.getOpcode());
// Add Rm,[Rm, #imm]!
@ -259,8 +251,8 @@ MachineInstr *ARMInstructionSplitting::splitLDRSTRPreImm(MachineBasicBlock &MBB,
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
}
Fst.addMetadata(N_fst);
Sec.addMetadata(N_sec);
Fst.addMetadata(MDNFir);
Sec.addMetadata(MDNSec);
return &MI;
}
@ -282,19 +274,19 @@ MachineInstr *ARMInstructionSplitting::splitLDRSTRPre(MachineBasicBlock &MBB,
unsigned ShiftOpc = getShiftOpcode(SOpc, SOffSet);
// Get Metadata for the first instruction.
ConstantAsMetadata *CMD_fst = ConstantAsMetadata::get(
ConstantAsMetadata *CMDFir = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 0, false)));
MDNode *N_fst = MDNode::get(*CTX, CMD_fst);
MDNode *MDNFir = MDNode::get(*CTX, CMDFir);
// Get Metadata for the second instruction.
ConstantAsMetadata *CMD_sec = ConstantAsMetadata::get(
ConstantAsMetadata *CMDSec = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 1, false)));
MDNode *N_sec = MDNode::get(*CTX, CMD_sec);
MDNode *MDNSec = MDNode::get(*CTX, CMDSec);
// Get Metadata for the third instruction.
ConstantAsMetadata *CMD_thd = ConstantAsMetadata::get(
ConstantAsMetadata *CMDThd = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 2, false)));
MDNode *N_thd = MDNode::get(*CTX, CMD_thd);
MDNode *MDNThd = MDNode::get(*CTX, CMDThd);
unsigned NewOpc = getLoadStoreOpcode(MI.getOpcode());
int Idx = MI.findRegisterUseOperandIdx(ARM::CPSR);
@ -333,9 +325,9 @@ MachineInstr *ARMInstructionSplitting::splitLDRSTRPre(MachineBasicBlock &MBB,
Thd.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Thd, MI.getOperand(Idx));
}
Fst.addMetadata(N_fst);
Sec.addMetadata(N_sec);
Thd.addMetadata(N_thd);
Fst.addMetadata(MDNFir);
Sec.addMetadata(MDNSec);
Thd.addMetadata(MDNThd);
} else if (ShiftOpc == ARM::RRX) {
// Split LDRxxx/STRxxx<c><q> <Rt>, [<Rn>, +/-<Rm>, RRX]!
MachineInstrBuilder Fst =
@ -363,9 +355,9 @@ MachineInstr *ARMInstructionSplitting::splitLDRSTRPre(MachineBasicBlock &MBB,
Thd.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Thd, MI.getOperand(Idx));
}
Fst.addMetadata(N_fst);
Sec.addMetadata(N_sec);
Thd.addMetadata(N_thd);
Fst.addMetadata(MDNFir);
Sec.addMetadata(MDNSec);
Thd.addMetadata(MDNThd);
} else {
// Split LDRxxx/STRxxx<c><q> <Rt>, [<Rn>, +/-<Rm>]!
MachineInstrBuilder Fst =
@ -389,8 +381,8 @@ MachineInstr *ARMInstructionSplitting::splitLDRSTRPre(MachineBasicBlock &MBB,
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
}
Fst.addMetadata(N_fst);
Sec.addMetadata(N_sec);
Fst.addMetadata(MDNFir);
Sec.addMetadata(MDNSec);
}
return &MI;
}
@ -407,14 +399,14 @@ MachineInstr *ARMInstructionSplitting::splitLDRSTRImm(MachineBasicBlock &MBB,
// The MI is splitted into 2 instructions.
// Get Metadata for the first instruction.
ConstantAsMetadata *CMD_fst = ConstantAsMetadata::get(
ConstantAsMetadata *CMDFir = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 0, false)));
MDNode *N_fst = MDNode::get(*CTX, CMD_fst);
MDNode *MDNFir = MDNode::get(*CTX, CMDFir);
// Get Metadata for the first instruction.
ConstantAsMetadata *CMD_sec = ConstantAsMetadata::get(
ConstantAsMetadata *CMDSec = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 1, false)));
MDNode *N_sec = MDNode::get(*CTX, CMD_sec);
MDNode *MDNSec = MDNode::get(*CTX, CMDSec);
unsigned NewOpc = getLoadStoreOpcode(MI.getOpcode());
// Add VReg, Rn, #imm
@ -440,128 +432,8 @@ MachineInstr *ARMInstructionSplitting::splitLDRSTRImm(MachineBasicBlock &MBB,
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
}
Fst.addMetadata(N_fst);
Sec.addMetadata(N_sec);
return &MI;
}
/// Split LDRxxx/STRxxx<c><q> <Rd>, [<Rn>, +/-<Rm>{, <shift>}] to:
/// Rm shift #imm, but write result to VReg.
/// Add VReg, Rn, Rm
/// LDRxxx/STRxxx Rd, [VReg]
MachineInstr *ARMInstructionSplitting::splitLDRSTR(MachineBasicBlock &MBB,
MachineInstr &MI) {
unsigned Simm = MI.getOperand(3).getImm();
unsigned SOffSet = ARM_AM::getAM2Offset(Simm);
ARM_AM::ShiftOpc SOpc = ARM_AM::getAM2ShiftOpc(Simm);
Register SVReg = MRI->createVirtualRegister(&ARM::GPRnopcRegClass);
Register AVReg = MRI->createVirtualRegister(&ARM::GPRnopcRegClass);
MachineOperand &Rd = MI.getOperand(0);
MachineOperand &Rn = MI.getOperand(1);
MachineOperand &Rm = MI.getOperand(2);
unsigned ShiftOpc = getShiftOpcode(SOpc, SOffSet);
// Get Metadata for the fisrt insturction.
ConstantAsMetadata *CMD_fst = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 0, false)));
MDNode *N_fst = MDNode::get(*CTX, CMD_fst);
// Get Metadata for the second insturction.
ConstantAsMetadata *CMD_sec = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 1, false)));
MDNode *N_sec = MDNode::get(*CTX, CMD_sec);
// Get Metadata for the third insturction.
ConstantAsMetadata *CMD_thd = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 2, false)));
MDNode *N_thd = MDNode::get(*CTX, CMD_thd);
unsigned NewOpc = getLoadStoreOpcode(MI.getOpcode());
int Idx = MI.findRegisterUseOperandIdx(ARM::CPSR);
if (SOffSet > 0) {
// Split LDRxxx/STRxxx Rd, [Rn, Rm, shift]
MachineInstrBuilder Fst =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ShiftOpc), SVReg);
addOperand(Fst, Rm);
Fst.addImm(SOffSet);
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ARM::ADDrr), AVReg);
addOperand(Sec, Rn);
Sec.addReg(SVReg);
MachineInstrBuilder Thd =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
if (MI.mayStore())
addOperand(Thd, Rd);
else
addOperand(Thd, Rd, true);
Thd.addReg(AVReg);
// Add CPSR if the MI has.
if (Idx != -1) {
Fst.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Fst, MI.getOperand(Idx));
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
Thd.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Thd, MI.getOperand(Idx));
}
Fst.addMetadata(N_fst);
Sec.addMetadata(N_sec);
Thd.addMetadata(N_thd);
} else if (ShiftOpc == ARM::RRX) {
// Split LDRxxx/STRxxx Rd, [Rn, Rm, rrx]
MachineInstrBuilder Fst =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ShiftOpc), SVReg);
addOperand(Fst, Rm);
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ARM::ADDrr), AVReg);
addOperand(Sec, Rn);
Sec.addReg(SVReg);
MachineInstrBuilder Thd =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
if (MI.mayStore())
addOperand(Thd, Rd);
else
addOperand(Thd, Rd, true);
Thd.addReg(AVReg);
// Add CPSR if the MI has.
if (Idx != -1) {
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
Thd.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Thd, MI.getOperand(Idx));
}
Fst.addMetadata(N_fst);
Sec.addMetadata(N_sec);
Thd.addMetadata(N_thd);
} else {
// Split LDRxxx/STRxxx Rd, [Rn, Rm]
MachineInstrBuilder Fst =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ARM::ADDrr), AVReg);
addOperand(Fst, Rn);
addOperand(Fst, Rm);
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
if (MI.mayStore())
addOperand(Sec, Rd);
else
addOperand(Sec, Rd, true);
Sec.addReg(AVReg);
// Add CPSR if the MI has.
if (Idx != -1) {
Fst.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Fst, MI.getOperand(Idx));
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
}
Fst.addMetadata(N_fst);
Sec.addMetadata(N_sec);
}
Fst.addMetadata(MDNFir);
Sec.addMetadata(MDNSec);
return &MI;
}
@ -570,9 +442,9 @@ MachineInstr *ARMInstructionSplitting::splitCommon(MachineBasicBlock &MBB,
MachineInstr &MI,
unsigned NewOpc) {
MachineInstr *ResMI = nullptr;
for (unsigned i = 0; i < MI.getNumOperands(); i++) {
if (MI.getOperand(i).isImm()) {
unsigned Simm = MI.getOperand(i).getImm();
for (unsigned OpIdx = 0; OpIdx < MI.getNumOperands(); OpIdx++) {
if (MI.getOperand(OpIdx).isImm()) {
unsigned Simm = MI.getOperand(OpIdx).getImm();
unsigned SOffSet = ARM_AM::getSORegOffset(Simm);
ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Simm);
unsigned ShiftOpc = getShiftOpcode(SOpc, SOffSet);
@ -580,16 +452,16 @@ MachineInstr *ARMInstructionSplitting::splitCommon(MachineBasicBlock &MBB,
Register VReg = MRI->createVirtualRegister(&ARM::GPRnopcRegClass);
if (ShiftOpc) {
MachineOperand &Rd = MI.getOperand(0);
MachineOperand &Rn = MI.getOperand(i - 2);
MachineOperand &Rm = MI.getOperand(i - 1);
MachineOperand &Rn = MI.getOperand(OpIdx - 2);
MachineOperand &Rm = MI.getOperand(OpIdx - 1);
ConstantAsMetadata *CMD_fst = ConstantAsMetadata::get(
ConstantAsMetadata *CMDFir = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 0, false)));
MDNode *N_fst = MDNode::get(*CTX, CMD_fst);
MDNode *MDNFir = MDNode::get(*CTX, CMDFir);
ConstantAsMetadata *CMD_sec = ConstantAsMetadata::get(
ConstantAsMetadata *CMDSec = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 1, false)));
MDNode *N_sec = MDNode::get(*CTX, CMD_sec);
MDNode *MDNSec = MDNode::get(*CTX, CMDSec);
if (SOffSet) {
// Split Opcode Rd, Rn, Rm, shift #imm
@ -599,34 +471,34 @@ MachineInstr *ARMInstructionSplitting::splitCommon(MachineBasicBlock &MBB,
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ShiftOpc), VReg);
addOperand(Fst, Rm);
Fst.addImm(SOffSet);
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
// Build 'opcode Rd, Rn, VReg'
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 1); N++) {
for (unsigned N = 1; N < (OpIdx - 1); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
} else {
if (ShiftOpc == ARM::RRX) {
// Split 'opcode Rd, Rn, Rm, RRX'
MachineInstrBuilder Fst =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ShiftOpc), VReg);
addOperand(Fst, Rm);
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < i - 1; N++) {
for (unsigned N = 1; N < OpIdx - 1; N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
} else {
// Split 'opcode Rd, Rn, Rm, shift Rs'
@ -635,18 +507,18 @@ MachineInstr *ARMInstructionSplitting::splitCommon(MachineBasicBlock &MBB,
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ShiftOpc), VReg);
addOperand(Fst, Rn);
addOperand(Fst, Rm);
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
// Build 'opcode Rd, Rn, VReg'
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 2); N++) {
for (unsigned N = 1; N < (OpIdx - 2); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
}
}
ResMI = &MI;
@ -663,26 +535,26 @@ MachineInstr *ARMInstructionSplitting::splitS(MachineBasicBlock &MBB,
MachineInstr &MI, unsigned NewOpc,
int Idx) {
MachineInstr *ResMI = nullptr;
for (unsigned i = 0; i < MI.getNumOperands(); i++) {
if (MI.getOperand(i).isImm()) {
unsigned Simm = MI.getOperand(i).getImm();
for (unsigned OpIdx = 0; OpIdx < MI.getNumOperands(); OpIdx++) {
if (MI.getOperand(OpIdx).isImm()) {
unsigned Simm = MI.getOperand(OpIdx).getImm();
unsigned SOffSet = ARM_AM::getSORegOffset(Simm);
ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Simm);
unsigned ShiftOpc = getShiftOpcode(SOpc, SOffSet);
Register VReg = MRI->createVirtualRegister(&ARM::GPRnopcRegClass);
if (ShiftOpc) {
ConstantAsMetadata *CMD_fst = ConstantAsMetadata::get(
ConstantAsMetadata *CMDFir = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 0, false)));
MDNode *N_fst = MDNode::get(*CTX, CMD_fst);
MDNode *MDNFir = MDNode::get(*CTX, CMDFir);
ConstantAsMetadata *CMD_sec = ConstantAsMetadata::get(
ConstantAsMetadata *CMDSec = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 1, false)));
MDNode *N_sec = MDNode::get(*CTX, CMD_sec);
MDNode *MDNSec = MDNode::get(*CTX, CMDSec);
MachineOperand &Rd = MI.getOperand(0);
MachineOperand &Rn = MI.getOperand(i - 2);
MachineOperand &Rm = MI.getOperand(i - 1);
MachineOperand &Rn = MI.getOperand(OpIdx - 2);
MachineOperand &Rm = MI.getOperand(OpIdx - 1);
// C flag is affected by Shift_c() if isShift_C is true.
if (isShift_C(MI.getOpcode())) {
@ -696,27 +568,27 @@ MachineInstr *ARMInstructionSplitting::splitS(MachineBasicBlock &MBB,
Fst.addImm(SOffSet);
Fst.addImm(ARMCC::AL);
addOperand(Fst, MI.getOperand(Idx));
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
// Build 'opcode<s> Rd, Rn, VReg'
// The new MI updates CPSR.
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 1); N++) {
for (unsigned N = 1; N < (OpIdx - 1); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(ARMCC::AL);
addOperand(Sec, MI.getOperand(Idx));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
} else {
if (ShiftOpc == ARM::RRX) {
// Split opcode<s> Rd, Rn, Rm, RRX.
MachineInstrBuilder Fst =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ShiftOpc), VReg);
addOperand(Fst, Rm);
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
// XXX: RRX implicit CPSR, how to add cpsr?
// Build base instructions
@ -724,13 +596,13 @@ MachineInstr *ARMInstructionSplitting::splitS(MachineBasicBlock &MBB,
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 1); N++) {
for (unsigned N = 1; N < (OpIdx - 1); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(ARMCC::AL);
addOperand(Sec, MI.getOperand(Idx));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
} else {
// Split opcode<s> Rd, Rn, Rm, shift Rs.
// The new MI updates CPSR.
@ -740,19 +612,19 @@ MachineInstr *ARMInstructionSplitting::splitS(MachineBasicBlock &MBB,
addOperand(Fst, Rm);
Fst.addImm(ARMCC::AL);
addOperand(Fst, MI.getOperand(Idx));
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 2); N++) {
for (unsigned N = 1; N < (OpIdx - 2); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(ARMCC::AL);
addOperand(Sec, MI.getOperand(Idx));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
}
}
} else {
@ -764,40 +636,40 @@ MachineInstr *ARMInstructionSplitting::splitS(MachineBasicBlock &MBB,
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ShiftOpc), VReg);
addOperand(Fst, Rm);
Fst.addImm(SOffSet);
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
// Build 'opcode<s> Rd, Rn, VReg'
// The new MI updates CPSR.
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 1); N++) {
for (unsigned N = 1; N < (OpIdx - 1); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(ARMCC::AL);
addOperand(Sec, MI.getOperand(Idx));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
} else {
if (ShiftOpc == ARM::RRX) {
// Split opcode<s> Rd, Rn, Rm, rrx.
MachineInstrBuilder Fst =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ShiftOpc), VReg);
addOperand(Fst, Rm);
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
// RRX implicit CPSR, how to add cpsr?
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 1); N++) {
for (unsigned N = 1; N < (OpIdx - 1); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(ARMCC::AL);
addOperand(Sec, MI.getOperand(Idx));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
} else {
// Split opcode<s> Rd, Rn, Rm, shift Rs.
@ -806,7 +678,7 @@ MachineInstr *ARMInstructionSplitting::splitS(MachineBasicBlock &MBB,
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ShiftOpc), VReg);
addOperand(Fst, Rn);
addOperand(Fst, Rm);
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
// Build 'opcode<s> Rd, Rn, VReg'
// The new MI updates CPSR.
@ -814,13 +686,13 @@ MachineInstr *ARMInstructionSplitting::splitS(MachineBasicBlock &MBB,
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 2); N++) {
for (unsigned N = 1; N < (OpIdx - 2); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(ARMCC::AL);
addOperand(Sec, MI.getOperand(Idx));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
}
}
}
@ -838,9 +710,9 @@ MachineInstr *ARMInstructionSplitting::splitC(MachineBasicBlock &MBB,
MachineInstr &MI, unsigned NewOpc,
int Idx) {
MachineInstr *ResMI = nullptr;
for (unsigned i = 0; i < MI.getNumOperands(); i++) {
if (MI.getOperand(i).isImm()) {
unsigned Simm = MI.getOperand(i).getImm();
for (unsigned OpIdx = 0; OpIdx < MI.getNumOperands(); OpIdx++) {
if (MI.getOperand(OpIdx).isImm()) {
unsigned Simm = MI.getOperand(OpIdx).getImm();
unsigned SOffSet = ARM_AM::getSORegOffset(Simm);
ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Simm);
unsigned ShiftOpc = getShiftOpcode(SOpc, SOffSet);
@ -848,16 +720,16 @@ MachineInstr *ARMInstructionSplitting::splitC(MachineBasicBlock &MBB,
if (ShiftOpc) {
MachineOperand &Rd = MI.getOperand(0);
MachineOperand &Rn = MI.getOperand(i - 2);
MachineOperand &Rm = MI.getOperand(i - 1);
MachineOperand &Rn = MI.getOperand(OpIdx - 2);
MachineOperand &Rm = MI.getOperand(OpIdx - 1);
ConstantAsMetadata *CMD_fst = ConstantAsMetadata::get(
ConstantAsMetadata *CMDFir = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 0, false)));
MDNode *N_fst = MDNode::get(*CTX, CMD_fst);
MDNode *MDNFir = MDNode::get(*CTX, CMDFir);
ConstantAsMetadata *CMD_sec = ConstantAsMetadata::get(
ConstantAsMetadata *CMDSec = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 1, false)));
MDNode *N_sec = MDNode::get(*CTX, CMD_sec);
MDNode *MDNSec = MDNode::get(*CTX, CMDSec);
if (SOffSet) {
// Split opcode<c> Rd, Rn, Rm, shift #imm
@ -869,25 +741,25 @@ MachineInstr *ARMInstructionSplitting::splitC(MachineBasicBlock &MBB,
Fst.addImm(SOffSet);
Fst.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Fst, MI.getOperand(Idx));
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 1); N++) {
for (unsigned N = 1; N < (OpIdx - 1); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
} else {
if (ShiftOpc == ARM::RRX) {
// Split opcode<c> Rd, Rn, Rm, RRX
MachineInstrBuilder Fst =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ShiftOpc), VReg);
addOperand(Fst, Rm);
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
// XXX: RRX implicit CPSR, how to add cpsr?
// Build base instructions
@ -895,13 +767,13 @@ MachineInstr *ARMInstructionSplitting::splitC(MachineBasicBlock &MBB,
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 1); N++) {
for (unsigned N = 1; N < (OpIdx - 1); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
} else {
// Split opcode<c> Rd, Rn, Rm, shift Rs
// The new MI checks CondCode.
@ -912,19 +784,19 @@ MachineInstr *ARMInstructionSplitting::splitC(MachineBasicBlock &MBB,
addOperand(Fst, Rm);
Fst.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Fst, MI.getOperand(Idx));
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 2); N++) {
for (unsigned N = 1; N < (OpIdx - 2); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
}
}
ResMI = &MI;
@ -941,9 +813,9 @@ MachineInstr *ARMInstructionSplitting::splitCS(MachineBasicBlock &MBB,
MachineInstr &MI,
unsigned NewOpc, int Idx) {
MachineInstr *ResMI = nullptr;
for (unsigned i = 0; i < MI.getNumOperands(); i++) {
if (MI.getOperand(i).isImm()) {
unsigned Simm = MI.getOperand(i).getImm();
for (unsigned OpIdx = 0; OpIdx < MI.getNumOperands(); OpIdx++) {
if (MI.getOperand(OpIdx).isImm()) {
unsigned Simm = MI.getOperand(OpIdx).getImm();
unsigned SOffSet = ARM_AM::getSORegOffset(Simm);
ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Simm);
unsigned ShiftOpc = getShiftOpcode(SOpc, SOffSet);
@ -951,16 +823,16 @@ MachineInstr *ARMInstructionSplitting::splitCS(MachineBasicBlock &MBB,
if (ShiftOpc) {
MachineOperand &Rd = MI.getOperand(0);
MachineOperand &Rn = MI.getOperand(i - 2);
MachineOperand &Rm = MI.getOperand(i - 1);
MachineOperand &Rn = MI.getOperand(OpIdx - 2);
MachineOperand &Rm = MI.getOperand(OpIdx - 1);
ConstantAsMetadata *CMD_fst = ConstantAsMetadata::get(
ConstantAsMetadata *CMDFir = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 0, false)));
MDNode *N_fst = MDNode::get(*CTX, CMD_fst);
MDNode *MDNFir = MDNode::get(*CTX, CMDFir);
ConstantAsMetadata *CMD_sec = ConstantAsMetadata::get(
ConstantAsMetadata *CMDSec = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 1, false)));
MDNode *N_sec = MDNode::get(*CTX, CMD_sec);
MDNode *MDNSec = MDNode::get(*CTX, CMDSec);
// C flag is affected by Shift_c() if isShift_C is true.
if (isShift_C(MI.getOpcode())) {
@ -975,40 +847,40 @@ MachineInstr *ARMInstructionSplitting::splitCS(MachineBasicBlock &MBB,
Fst.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Fst, MI.getOperand(Idx));
addOperand(Fst, MI.getOperand(Idx + 1));
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 1); N++) {
for (unsigned N = 1; N < (OpIdx - 1); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
addOperand(Sec, MI.getOperand(Idx + 1));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
} else {
if (ShiftOpc == ARM::RRX) {
// Split opcode<s><c> Rd, Rn, Rm, RRX
MachineInstrBuilder Fst =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ShiftOpc), VReg);
addOperand(Fst, Rm);
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
// RRX implicit CPSR, how to add cpsr?
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 1); N++) {
for (unsigned N = 1; N < (OpIdx - 1); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
addOperand(Sec, MI.getOperand(Idx + 1));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
} else {
// Split opcode<s><c> Rd, Rn, Rm, shift Rs
@ -1020,20 +892,20 @@ MachineInstr *ARMInstructionSplitting::splitCS(MachineBasicBlock &MBB,
Fst.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Fst, MI.getOperand(Idx));
addOperand(Fst, MI.getOperand(Idx + 1));
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 2); N++) {
for (unsigned N = 1; N < (OpIdx - 2); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
addOperand(Sec, MI.getOperand(Idx + 1));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
}
}
} else {
@ -1049,42 +921,42 @@ MachineInstr *ARMInstructionSplitting::splitCS(MachineBasicBlock &MBB,
Fst.addImm(SOffSet);
Fst.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Fst, MI.getOperand(Idx));
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
// Build 'newOpc<s><c> Rd, Rn, VReg'
// The new MI both updates CPSR and checks CondCode.
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 1); N++) {
for (unsigned N = 1; N < (OpIdx - 1); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
addOperand(Sec, MI.getOperand(Idx + 1));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
} else {
if (ShiftOpc == ARM::RRX) {
// Split opcode<s><c> Rd, Rn, Rm, RRX
MachineInstrBuilder Fst =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(ShiftOpc), VReg);
addOperand(Fst, Rm);
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
// RRX implicit CPSR, how to add cpsr?
MachineInstrBuilder Sec =
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 1); N++) {
for (unsigned N = 1; N < (OpIdx - 1); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
addOperand(Sec, MI.getOperand(Idx + 1));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
} else {
// Split opcode<s><c> Rd, Rn, Rm, shift Rs
@ -1096,7 +968,7 @@ MachineInstr *ARMInstructionSplitting::splitCS(MachineBasicBlock &MBB,
addOperand(Fst, Rm);
Fst.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Fst, MI.getOperand(Idx));
Fst.addMetadata(N_fst);
Fst.addMetadata(MDNFir);
// Build 'newOpc<s><c> Rd, Rn, VReg'
// The new MI both updates CPSR and checks CondCode.
@ -1104,14 +976,14 @@ MachineInstr *ARMInstructionSplitting::splitCS(MachineBasicBlock &MBB,
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc));
addOperand(Sec, Rd, true);
for (unsigned N = 1; N < (i - 2); N++) {
for (unsigned N = 1; N < (OpIdx - 2); N++) {
addOperand(Sec, MI.getOperand(N));
}
Sec.addReg(VReg);
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
addOperand(Sec, MI.getOperand(Idx + 1));
Sec.addMetadata(N_sec);
Sec.addMetadata(MDNSec);
}
}
}

113
ARM/ARMInstructionSplitting.h
Просмотреть файл

@ -39,7 +39,118 @@ private:
unsigned checkisShifter(unsigned Opcode);
/// Get the shift opcode in MI.
unsigned getShiftOpcode(ARM_AM::ShiftOpc SOpc, unsigned OffSet);
MachineInstr *splitLDRSTR(MachineBasicBlock &MBB, MachineInstr &MI);
/// Split LDRxxx/STRxxx<c><q> <Rd>, [<Rn>, +/-<Rm>{, <shift>}] to:
/// Rm shift #imm, but write result to VReg.
/// Add VReg, Rn, Rm
/// LDRxxx/STRxxx Rd, [VReg]
MachineInstr* splitLDRSTR(MachineBasicBlock &MBB, MachineInstr &MI) {
unsigned Simm = MI.getOperand(3).getImm();
unsigned SOffSet = ARM_AM::getAM2Offset(Simm);
ARM_AM::ShiftOpc SOpc = ARM_AM::getAM2ShiftOpc(Simm);
Register SVReg = MRI->createVirtualRegister(&ARM::GPRnopcRegClass);
Register AVReg = MRI->createVirtualRegister(&ARM::GPRnopcRegClass);
MachineOperand &Rd = MI.getOperand(0);
MachineOperand &Rn = MI.getOperand(1);
MachineOperand &Rm = MI.getOperand(2);
unsigned ShiftOpc = getShiftOpcode(SOpc, SOffSet);
// Get Metadata for the fisrt insturction.
ConstantAsMetadata *CMDFir = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 0, false)));
MDNode *MDNFir = MDNode::get(*CTX, CMDFir);
// Get Metadata for the second insturction.
ConstantAsMetadata *CMDSec = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 1, false)));
MDNode *MDNSec = MDNode::get(*CTX, CMDSec);
// Get Metadata for the third insturction.
ConstantAsMetadata *CMD_thd = ConstantAsMetadata::get(
ConstantInt::get(*CTX, llvm::APInt(64, 2, false)));
MDNode *N_thd = MDNode::get(*CTX, CMD_thd);
unsigned NewOpc = getLoadStoreOpcode(MI.getOpcode());
int Idx = MI.findRegisterUseOperandIdx(ARM::CPSR);
if (SOffSet > 0) {
// Split LDRxxx/STRxxx Rd, [Rn, Rm, shift]
MachineInstrBuilder Fst = BuildMI(MBB, MI, MI.getDebugLoc(),
TII->get(ShiftOpc), SVReg);
addOperand(Fst, Rm);
Fst.addImm(SOffSet);
MachineInstrBuilder Sec = BuildMI(MBB, MI, MI.getDebugLoc(),
TII->get(ARM::ADDrr), AVReg);
addOperand(Sec, Rn);
Sec.addReg(SVReg);
MachineInstrBuilder Thd = BuildMI(MBB, MI, MI.getDebugLoc(),
TII->get(NewOpc));
if (MI.mayStore())
addOperand(Thd, Rd);
else
addOperand(Thd, Rd, true);
Thd.addReg(AVReg);
// Add CPSR if the MI has.
if (Idx != -1) {
Fst.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Fst, MI.getOperand(Idx));
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
Thd.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Thd, MI.getOperand(Idx));
}
Fst.addMetadata(MDNFir);
Sec.addMetadata(MDNSec);
Thd.addMetadata(N_thd);
} else if (ShiftOpc == ARM::RRX) {
// Split LDRxxx/STRxxx Rd, [Rn, Rm, rrx]
MachineInstrBuilder Fst = BuildMI(MBB, MI, MI.getDebugLoc(),
TII->get(ShiftOpc), SVReg);
addOperand(Fst, Rm);
MachineInstrBuilder Sec = BuildMI(MBB, MI, MI.getDebugLoc(),
TII->get(ARM::ADDrr), AVReg);
addOperand(Sec, Rn);
Sec.addReg(SVReg);
MachineInstrBuilder Thd = BuildMI(MBB, MI, MI.getDebugLoc(),
TII->get(NewOpc));
if (MI.mayStore())
addOperand(Thd, Rd);
else
addOperand(Thd, Rd, true);
Thd.addReg(AVReg);
// Add CPSR if the MI has.
if (Idx != -1) {
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
Thd.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Thd, MI.getOperand(Idx));
}
Fst.addMetadata(MDNFir);
Sec.addMetadata(MDNSec);
Thd.addMetadata(N_thd);
} else {
// Split LDRxxx/STRxxx Rd, [Rn, Rm]
MachineInstrBuilder Fst = BuildMI(MBB, MI, MI.getDebugLoc(),
TII->get(ARM::ADDrr), AVReg);
addOperand(Fst, Rn);
addOperand(Fst, Rm);
MachineInstrBuilder Sec = BuildMI(MBB, MI, MI.getDebugLoc(),
TII->get(NewOpc));
if (MI.mayStore())
addOperand(Sec, Rd);
else
addOperand(Sec, Rd, true);
Sec.addReg(AVReg);
// Add CPSR if the MI has.
if (Idx != -1) {
Fst.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Fst, MI.getOperand(Idx));
Sec.addImm(MI.getOperand(Idx - 1).getImm());
addOperand(Sec, MI.getOperand(Idx));
}
Fst.addMetadata(MDNFir);
Sec.addMetadata(MDNSec);
}
return &MI;
}
MachineInstr *splitLDRSTRPre(MachineBasicBlock &MBB, MachineInstr &MI);
MachineInstr *splitLDRSTRPreImm(MachineBasicBlock &MBB, MachineInstr &MI);
MachineInstr *splitLDRSTRImm(MachineBasicBlock &MBB, MachineInstr &MI);

4
ARM/ARMMIRevising.cpp
Просмотреть файл

@ -124,7 +124,7 @@ uint64_t ARMMIRevising::getCalledFunctionAtPLTOffset(uint64_t PLTEndOff,
assert(OpdAddIP.isImm() && "Unexpected immediate for offset.");
unsigned Bits = OpdAddIP.getImm() & 0xFF;
unsigned Rot = (OpdAddIP.getImm() & 0xF00) >> 7;
int64_t P_Align = static_cast<int64_t>(ARM_AM::rotr32(Bits, Rot));
int64_t PAlign = static_cast<int64_t>(ARM_AM::rotr32(Bits, Rot));
MCInst Inst;
uint64_t InstSz;
@ -144,7 +144,7 @@ uint64_t ARMMIRevising::getCalledFunctionAtPLTOffset(uint64_t PLTEndOff,
uint64_t Index = Operand.getImm();
uint64_t GotPltRelocOffset = PLTEndOff + Index + P_Align + 8;
uint64_t GotPltRelocOffset = PLTEndOff + Index + PAlign + 8;
const RelocationRef *GotPltReloc =
MR->getDynRelocAtOffset(GotPltRelocOffset);
assert(GotPltReloc != nullptr &&

18
ARM/ARMModuleRaiser.cpp
Просмотреть файл

@ -38,25 +38,25 @@ bool ARMModuleRaiser::collectDynamicRelocations() {
}
// Get rodata instruction addr.
uint64_t ARMModuleRaiser::getArgNumInstrAddr(uint64_t callAddr) {
uint64_t ARMModuleRaiser::getArgNumInstrAddr(uint64_t CallAddr) {
uint64_t InstArgCount = InstArgCollect.size();
if (InstArgCount == 0)
return InstArgCount;
for (uint64_t i = 0; i < InstArgCount; i++) {
if (InstArgCollect[i] > callAddr) {
return InstArgCollect[i - 1];
for (uint64_t Idx = 0; Idx < InstArgCount; Idx++) {
if (InstArgCollect[Idx] > CallAddr) {
return InstArgCollect[Idx - 1];
}
}
return InstArgCollect[InstArgCount - 1];
}
uint64_t ARMModuleRaiser::getFunctionArgNum(uint64_t callAddr) {
uint64_t rodataAddr = getArgNumInstrAddr(callAddr);
uint64_t ARMModuleRaiser::getFunctionArgNum(uint64_t CallAddr) {
uint64_t ROdataAddr = getArgNumInstrAddr(CallAddr);
if (rodataAddr == 0)
return rodataAddr;
return InstArgNumMap[rodataAddr];
if (ROdataAddr == 0)
return ROdataAddr;
return InstArgNumMap[ROdataAddr];
}
const Value *ARMModuleRaiser::getRODataValueAt(uint64_t Offset) const {

10
ARM/ARMSelectionDAGISel.cpp
Просмотреть файл

@ -79,22 +79,22 @@ void ARMSelectionDAGISel::doInstructionSelection() {
}
void ARMSelectionDAGISel::emitDAG() {
IREmitter imt(BB, DAGInfo, FuncInfo);
imt.setjtList(JTList);
IREmitter Imt(BB, DAGInfo, FuncInfo);
Imt.setjtList(JTList);
SelectionDAG::allnodes_iterator ISelPosition = CurDAG->allnodes_begin();
while (ISelPosition != CurDAG->allnodes_end()) {
SDNode *Node = &*ISelPosition++;
imt.emitNode(Node);
Imt.emitNode(Node);
}
}
void ARMSelectionDAGISel::initEntryBasicBlock() {
BasicBlock *BB = &RF->getEntryBlock();
for (unsigned i = 0; i < 4; i++) {
for (unsigned Idx = 0; Idx < 4; Idx++) {
Align MALG(32);
AllocaInst *Alloc = new AllocaInst(Type::getInt1Ty(RF->getContext()), 0,
nullptr, MALG, "", BB);
FuncInfo->AllocaMap[i] = Alloc;
FuncInfo->AllocaMap[Idx] = Alloc;
new StoreInst(ConstantInt::getFalse(RF->getContext()), Alloc, BB);
}
}

12
ARM/DAG/DAGBuilder.cpp
Просмотреть файл

@ -146,9 +146,9 @@ void DAGBuilder::visitCC(const MachineInstr &MI, MachineSDNode *MNode) {
NodeInfo.Special = true;
} else {
// Pattern matching: addeq r0, r0, 0
for (int i = 1; i < NumOps; i++) {
if (MI.getOperand(Idx - i).isImm()) {
NodeInfo.Cond = MI.getOperand(Idx - i).getImm();
for (int OpIdx = 1; OpIdx < NumOps; OpIdx++) {
if (MI.getOperand(Idx - OpIdx).isImm()) {
NodeInfo.Cond = MI.getOperand(Idx - OpIdx).getImm();
break;
}
}
@ -156,10 +156,10 @@ void DAGBuilder::visitCC(const MachineInstr &MI, MachineSDNode *MNode) {
} else {
if (MI.getOperand(Idx - 1).isReg() &&
MI.getOperand(Idx - 1).getReg() == ARM::CPSR) {
for (int i = 1; i < NumOps; i++) {
if (MI.getOperand(Idx - i).isImm()) {
for (int OpIdx = 1; OpIdx < NumOps; OpIdx++) {
if (MI.getOperand(Idx - OpIdx).isImm()) {
NodeInfo.Special = true;
NodeInfo.Cond = MI.getOperand(Idx - i).getImm();
NodeInfo.Cond = MI.getOperand(Idx - OpIdx).getImm();
break;
}
}

2
ARM/DAG/DAGRaisingInfo.cpp
Просмотреть файл

@ -16,7 +16,7 @@
using namespace llvm;
using namespace llvm::mctoll;
DAGRaisingInfo::DAGRaisingInfo(SelectionDAG &dag) : DAG(dag) {}
DAGRaisingInfo::DAGRaisingInfo(SelectionDAG &Dag) : DAG(Dag) {}
/// Gets the related IR Value of given SDNode.
Value *DAGRaisingInfo::getRealValue(SDNode *Node) {

424
ARM/DAG/IREmitter.cpp
Просмотреть файл

@ -136,88 +136,88 @@ void IREmitter::emitCondCode(unsigned CondValue, BasicBlock *BB,
default:
break;
case ARMCC::EQ: { // EQ Z set
Value *Z_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *InstEQ = IRB.CreateICmpEQ(Z_Flag, IRB.getTrue());
Value *ZFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *InstEQ = IRB.CreateICmpEQ(ZFlag, IRB.getTrue());
IRB.CreateCondBr(InstEQ, IfBB, ElseBB);
} break;
case ARMCC::NE: { // NE Z clear
Value *Z_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *InstEQ = IRB.CreateICmpEQ(Z_Flag, IRB.getFalse());
Value *ZFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *InstEQ = IRB.CreateICmpEQ(ZFlag, IRB.getFalse());
IRB.CreateCondBr(InstEQ, IfBB, ElseBB);
} break;
case ARMCC::HS: { // CS C set
Value *C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *InstEQ = IRB.CreateICmpEQ(C_Flag, IRB.getTrue());
Value *CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *InstEQ = IRB.CreateICmpEQ(CFlag, IRB.getTrue());
IRB.CreateCondBr(InstEQ, IfBB, ElseBB);
} break;
case ARMCC::LO: { // CC C clear
Value *C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *InstEQ = IRB.CreateICmpEQ(C_Flag, IRB.getFalse());
Value *CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *InstEQ = IRB.CreateICmpEQ(CFlag, IRB.getFalse());
IRB.CreateCondBr(InstEQ, IfBB, ElseBB);
} break;
case ARMCC::MI: { // MI N set
Value *N_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *InstEQ = IRB.CreateICmpEQ(N_Flag, IRB.getTrue());
Value *NFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *InstEQ = IRB.CreateICmpEQ(NFlag, IRB.getTrue());
IRB.CreateCondBr(InstEQ, IfBB, ElseBB);
} break;
case ARMCC::PL: { // PL N clear
Value *N_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *InstEQ = IRB.CreateICmpEQ(N_Flag, IRB.getFalse());
Value *NFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *InstEQ = IRB.CreateICmpEQ(NFlag, IRB.getFalse());
IRB.CreateCondBr(InstEQ, IfBB, ElseBB);
} break;
case ARMCC::VS: { // VS V set
Value *V_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
Value *InstEQ = IRB.CreateICmpEQ(V_Flag, IRB.getTrue());
Value *VFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
Value *InstEQ = IRB.CreateICmpEQ(VFlag, IRB.getTrue());
IRB.CreateCondBr(InstEQ, IfBB, ElseBB);
} break;
case ARMCC::VC: { // VC V clear
Value *V_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
Value *InstEQ = IRB.CreateICmpEQ(V_Flag, IRB.getFalse());
Value *VFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
Value *InstEQ = IRB.CreateICmpEQ(VFlag, IRB.getFalse());
IRB.CreateCondBr(InstEQ, IfBB, ElseBB);
} break;
case ARMCC::HI: { // HI C set & Z clear
Value *C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *Z_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *InstCEQ = IRB.CreateICmpEQ(C_Flag, IRB.getTrue());
Value *InstZEQ = IRB.CreateICmpEQ(Z_Flag, IRB.getFalse());
Value *CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *ZFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *InstCEQ = IRB.CreateICmpEQ(CFlag, IRB.getTrue());
Value *InstZEQ = IRB.CreateICmpEQ(ZFlag, IRB.getFalse());
Value *CondPass = IRB.CreateICmpEQ(InstCEQ, InstZEQ);
IRB.CreateCondBr(CondPass, IfBB, ElseBB);
} break;
case ARMCC::LS: { // LS C clear or Z set
Value *C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *Z_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *InstCEQ = IRB.CreateICmpEQ(C_Flag, IRB.getFalse());
Value *InstZEQ = IRB.CreateICmpEQ(Z_Flag, IRB.getTrue());
Value *CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *ZFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *InstCEQ = IRB.CreateICmpEQ(CFlag, IRB.getFalse());
Value *InstZEQ = IRB.CreateICmpEQ(ZFlag, IRB.getTrue());
Value *CondPass = IRB.CreateXor(InstCEQ, InstZEQ);
IRB.CreateCondBr(CondPass, IfBB, ElseBB);
} break;
case ARMCC::GE: { // GE N = V
Value *N_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *V_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
Value *InstEQ = IRB.CreateICmpEQ(N_Flag, V_Flag);
Value *NFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *VFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
Value *InstEQ = IRB.CreateICmpEQ(NFlag, VFlag);
IRB.CreateCondBr(InstEQ, IfBB, ElseBB);
} break;
case ARMCC::LT: { // LT N != V
Value *N_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *V_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
Value *InstNE = IRB.CreateICmpNE(N_Flag, V_Flag);
Value *NFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *VFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
Value *InstNE = IRB.CreateICmpNE(NFlag, VFlag);
IRB.CreateCondBr(InstNE, IfBB, ElseBB);
} break;
case ARMCC::GT: { // GT Z clear & N = V
Value *N_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *Z_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *V_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
Value *InstZEQ = IRB.CreateICmpEQ(Z_Flag, IRB.getFalse());
Value *InstNZEQ = IRB.CreateICmpEQ(N_Flag, V_Flag);
Value *NFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *ZFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *VFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
Value *InstZEQ = IRB.CreateICmpEQ(ZFlag, IRB.getFalse());
Value *InstNZEQ = IRB.CreateICmpEQ(NFlag, VFlag);
Value *CondPass = IRB.CreateICmpEQ(InstZEQ, InstNZEQ);
IRB.CreateCondBr(CondPass, IfBB, ElseBB);
} break;
case ARMCC::LE: { // LE Z set or N != V
Value *N_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *Z_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *V_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
Value *InstZEQ = IRB.CreateICmpEQ(Z_Flag, IRB.getTrue());
Value *InstNZNE = IRB.CreateICmpNE(N_Flag, V_Flag);
Value *NFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *ZFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *VFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
Value *InstZEQ = IRB.CreateICmpEQ(ZFlag, IRB.getTrue());
Value *InstNZNE = IRB.CreateICmpNE(NFlag, VFlag);
Value *CondPass = IRB.CreateXor(InstZEQ, InstNZNE);
IRB.CreateCondBr(CondPass, IfBB, ElseBB);
} break;
@ -231,19 +231,19 @@ void IREmitter::emitCondCode(unsigned CondValue, BasicBlock *BB,
PHINode *IREmitter::createAndEmitPHINode(SDNode *Node, BasicBlock *BB,
BasicBlock *IfBB, BasicBlock *ElseBB,
Instruction *IfInst) {
PHINode *phi = PHINode::Create(getDefaultType(), 2, "", ElseBB);
PHINode *Phi = PHINode::Create(getDefaultType(), 2, "", ElseBB);
if (FuncInfo->ArgValMap.count(FuncInfo->NodeRegMap[Node]) > 0) {
phi->addIncoming(FuncInfo->ArgValMap[FuncInfo->NodeRegMap[Node]], BB);
Phi->addIncoming(FuncInfo->ArgValMap[FuncInfo->NodeRegMap[Node]], BB);
} else {
ConstantInt *zero = ConstantInt::get(getDefaultType(), 0, true);
Instruction *ti = BB->getTerminator();
Value *p = BinaryOperator::CreateAdd(zero, zero, "", ti);
phi->addIncoming(p, BB);
ConstantInt *Zero = ConstantInt::get(getDefaultType(), 0, true);
Instruction *TermInst = BB->getTerminator();
Value *AddVal = BinaryOperator::CreateAdd(Zero, Zero, "", TermInst);
Phi->addIncoming(AddVal, BB);
}
phi->addIncoming(IfInst, IfBB);
return phi;
Phi->addIncoming(IfInst, IfBB);
return Phi;
}
/// Update the N Z C V flags of global variable.
@ -254,75 +254,75 @@ void IREmitter::emitCPSR(Value *Operand0, Value *Operand1, BasicBlock *BB,
Module &M = *MR->getModule();
Type *Ty = IRB.getInt1Ty();
Type *OperandTy = getDefaultType();
Function *F_Signed =
Function *FSigned =
Intrinsic::getDeclaration(&M, Intrinsic::sadd_with_overflow, OperandTy);
Function *F_Unsigned =
Function *FUnsigned =
Intrinsic::getDeclaration(&M, Intrinsic::uadd_with_overflow, OperandTy);
Value *Args[] = {Operand0, Operand1};
Value *Unsigned_Sum;
Value *Signed_Sum;
Value *UnsignedSum;
Value *SignedSum;
if (Flag) {
Value *OperandFlag = IRB.CreateAdd(Operand0, IRB.getInt32(1));
Value *Args_Flag[] = {Operand1, OperandFlag};
Unsigned_Sum = IRB.CreateCall(F_Unsigned, Args_Flag);
Signed_Sum = IRB.CreateCall(F_Signed, Args_Flag);
Value *ArgsFlag[] = {Operand1, OperandFlag};
UnsignedSum = IRB.CreateCall(FUnsigned, ArgsFlag);
SignedSum = IRB.CreateCall(FSigned, ArgsFlag);
} else {
Unsigned_Sum = IRB.CreateCall(F_Unsigned, Args);
Signed_Sum = IRB.CreateCall(F_Signed, Args);
UnsignedSum = IRB.CreateCall(FUnsigned, Args);
SignedSum = IRB.CreateCall(FSigned, Args);
}
Value *Sum = ExtractValueInst::Create(Unsigned_Sum, 0, "", BB);
Value *Sum = ExtractValueInst::Create(UnsignedSum, 0, "", BB);
Value *Result = Sum;
// Update the corresponding flags.
// Update N flag.
Value *N_Flag = IRB.CreateLShr(Result, IRB.getInt32(31));
Value *NTrunc = IRB.CreateTrunc(N_Flag, Ty);
Value *NFlag = IRB.CreateLShr(Result, IRB.getInt32(31));
Value *NTrunc = IRB.CreateTrunc(NFlag, Ty);
IRB.CreateStore(NTrunc, FuncInfo->AllocaMap[0]);
// Update Z flag.
Value *Z_Flag = IRB.CreateICmpEQ(Result, IRB.getInt32(0));
Value *ZTrunc = IRB.CreateTrunc(Z_Flag, Ty);
Value *ZFlag = IRB.CreateICmpEQ(Result, IRB.getInt32(0));
Value *ZTrunc = IRB.CreateTrunc(ZFlag, Ty);
IRB.CreateStore(ZTrunc, FuncInfo->AllocaMap[1]);
// Update C flag.
Value *C_Flag = ExtractValueInst::Create(Unsigned_Sum, 1, "", BB);
IRB.CreateStore(C_Flag, FuncInfo->AllocaMap[2]);
Value *CFlag = ExtractValueInst::Create(UnsignedSum, 1, "", BB);
IRB.CreateStore(CFlag, FuncInfo->AllocaMap[2]);
// Update V flag.
Value *V_Flag = ExtractValueInst::Create(Signed_Sum, 1, "", BB);
IRB.CreateStore(V_Flag, FuncInfo->AllocaMap[3]);
Value *VFlag = ExtractValueInst::Create(SignedSum, 1, "", BB);
IRB.CreateStore(VFlag, FuncInfo->AllocaMap[3]);
}
void IREmitter::emitSpecialCPSR(Value *Result, BasicBlock *BB, unsigned Flag) {
Type *Ty = IRB.getInt1Ty();
// Update N flag.
Value *N_Flag = IRB.CreateLShr(Result, IRB.getInt32(31));
N_Flag = IRB.CreateTrunc(N_Flag, Ty);
IRB.CreateStore(N_Flag, FuncInfo->AllocaMap[0]);
Value *NFlag = IRB.CreateLShr(Result, IRB.getInt32(31));
NFlag = IRB.CreateTrunc(NFlag, Ty);
IRB.CreateStore(NFlag, FuncInfo->AllocaMap[0]);
// Update Z flag.
Value *Z_Flag = IRB.CreateICmpEQ(Result, IRB.getInt32(0));
Value *ZFlag = IRB.CreateICmpEQ(Result, IRB.getInt32(0));
IRB.CreateStore(Z_Flag, FuncInfo->AllocaMap[1]);
IRB.CreateStore(ZFlag, FuncInfo->AllocaMap[1]);
}
Type *IREmitter::getIntTypeByPtr(Type *pty) {
assert(pty && pty->isPointerTy() && "The input type is not a pointer!");
Type *ty = nullptr;
Type *IREmitter::getIntTypeByPtr(Type *PTy) {
assert(PTy && PTy->isPointerTy() && "The input type is not a pointer!");
Type *Ty = nullptr;
if (pty == Type::getInt64PtrTy(*CTX))
ty = Type::getInt64Ty(*CTX);
else if (pty == Type::getInt32PtrTy(*CTX))
ty = Type::getInt32Ty(*CTX);
else if (pty == Type::getInt16PtrTy(*CTX))
ty = Type::getInt16Ty(*CTX);
else if (pty == Type::getInt8PtrTy(*CTX))
ty = Type::getInt8Ty(*CTX);
else if (pty == Type::getInt1PtrTy(*CTX))
ty = Type::getInt1Ty(*CTX);
if (PTy == Type::getInt64PtrTy(*CTX))
Ty = Type::getInt64Ty(*CTX);
else if (PTy == Type::getInt32PtrTy(*CTX))
Ty = Type::getInt32Ty(*CTX);
else if (PTy == Type::getInt16PtrTy(*CTX))
Ty = Type::getInt16Ty(*CTX);
else if (PTy == Type::getInt8PtrTy(*CTX))
Ty = Type::getInt8Ty(*CTX);
else if (PTy == Type::getInt1PtrTy(*CTX))
Ty = Type::getInt1Ty(*CTX);
else
ty = getDefaultType();
Ty = getDefaultType();
return ty;
return Ty;
}
#define HANDLE_EMIT_CONDCODE_COMMON(OPC) \
@ -387,10 +387,10 @@ void IREmitter::emitBinaryCPSR(Value *Inst, BasicBlock *BB, unsigned Opcode,
// c flag = (s0 lsl (s1 -1))[31]
Type *Ty = IRB.getInt1Ty();
Value *Val = cast<Value>(ConstantInt::get(getDefaultType(), 1, true));
Value *C_Flag = IRB.CreateSub(S1, Val);
C_Flag = IRB.CreateShl(S0, C_Flag);
C_Flag = IRB.CreateLShr(C_Flag, IRB.getInt32(31));
Value *CTrunc = IRB.CreateTrunc(C_Flag, Ty);
Value *CFlag = IRB.CreateSub(S1, Val);
CFlag = IRB.CreateShl(S0, CFlag);
CFlag = IRB.CreateLShr(CFlag, IRB.getInt32(31));
Value *CTrunc = IRB.CreateTrunc(CFlag, Ty);
IRB.CreateStore(CTrunc, FuncInfo->AllocaMap[2]);
} break;
@ -401,10 +401,10 @@ void IREmitter::emitBinaryCPSR(Value *Inst, BasicBlock *BB, unsigned Opcode,
// c flag = (s0 lsr (s1 -1))[0]
Type *Ty = IRB.getInt1Ty();
Value *Val = cast<Value>(ConstantInt::get(getDefaultType(), 1, true));
Value *C_Flag = IRB.CreateSub(S1, Val);
C_Flag = IRB.CreateLShr(S0, C_Flag);
C_Flag = IRB.CreateAnd(C_Flag, Val);
Value *CTrunc = IRB.CreateTrunc(C_Flag, Ty);
Value *CFlag = IRB.CreateSub(S1, Val);
CFlag = IRB.CreateLShr(S0, CFlag);
CFlag = IRB.CreateAnd(CFlag, Val);
Value *CTrunc = IRB.CreateTrunc(CFlag, Ty);
IRB.CreateStore(CTrunc, FuncInfo->AllocaMap[2]);
} break;
@ -415,10 +415,10 @@ void IREmitter::emitBinaryCPSR(Value *Inst, BasicBlock *BB, unsigned Opcode,
// c flag = (s0 asr (s1 -1))[0]
Type *Ty = IRB.getInt1Ty();
Value *Val = ConstantInt::get(getDefaultType(), 1, true);
Value *C_Flag = IRB.CreateSub(S1, Val);
C_Flag = IRB.CreateAShr(S0, C_Flag);
C_Flag = IRB.CreateAnd(C_Flag, Val);
Value *CTrunc = IRB.CreateTrunc(C_Flag, Ty);
Value *CFlag = IRB.CreateSub(S1, Val);
CFlag = IRB.CreateAShr(S0, CFlag);
CFlag = IRB.CreateAnd(CFlag, Val);
Value *CTrunc = IRB.CreateTrunc(CFlag, Ty);
IRB.CreateStore(CTrunc, FuncInfo->AllocaMap[2]);
} break;
}
@ -729,22 +729,22 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
if (StackNum > StackArg)
StackArg = StackNum;
}
for (unsigned i = 0; i < ArgNum; i++) {
if (i < 4)
ArgVal = FuncInfo->ArgValMap[ARM::R0 + i];
for (unsigned Idx = 0; Idx < ArgNum; Idx++) {
if (Idx < 4)
ArgVal = FuncInfo->ArgValMap[ARM::R0 + Idx];
else {
const Value *StackAlloc =
MFI.getObjectAllocation(StackArg - i - 4 + 1);
MFI.getObjectAllocation(StackArg - Idx - 4 + 1);
ArgVal = callCreateAlignedLoad(
const_cast<Value *>(StackAlloc),
MaybeAlign(Log2(DLT->getPointerPrefAlignment())));
}
if (IsSyscall && i < CallFunc->arg_size() &&
ArgVal->getType() != CalledFuncArgs[i].getType()) {
if (IsSyscall && Idx < CallFunc->arg_size() &&
ArgVal->getType() != CalledFuncArgs[Idx].getType()) {
CastInst *CInst = CastInst::Create(
CastInst::getCastOpcode(ArgVal, false,
CalledFuncArgs[i].getType(), false),
ArgVal, CalledFuncArgs[i].getType());
CalledFuncArgs[Idx].getType(), false),
ArgVal, CalledFuncArgs[Idx].getType());
IRB.GetInsertBlock()->getInstList().push_back(CInst);
ArgVal = CInst;
}
@ -764,53 +764,53 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
case ISD::BR_JT: {
// Emit the switch instruction.
if (JTList.size() > 0) {
MachineBasicBlock *mbb = FuncInfo->MBBMap[CurBB];
MachineFunction *MF = mbb->getParent();
MachineBasicBlock *Mbb = FuncInfo->MBBMap[CurBB];
MachineFunction *MF = Mbb->getParent();
std::vector<JumpTableBlock> JTCases;
const MachineJumpTableInfo *MJT = MF->getJumpTableInfo();
unsigned jtIndex = Node->getConstantOperandVal(0);
unsigned JTIndex = Node->getConstantOperandVal(0);
std::vector<MachineJumpTableEntry> JumpTables = MJT->getJumpTables();
for (unsigned j = 0, f = JumpTables[jtIndex].MBBs.size(); j != f; ++j) {
llvm::Type *i32_type = llvm::IntegerType::getInt32Ty(*CTX);
llvm::ConstantInt *i32_val =
cast<ConstantInt>(llvm::ConstantInt::get(i32_type, j, true));
MachineBasicBlock *Succ = JumpTables[jtIndex].MBBs[j];
ConstantInt *CaseVal = i32_val;
for (unsigned Idx = 0, MBBSz = JumpTables[JTIndex].MBBs.size(); Idx != MBBSz; ++Idx) {
llvm::Type *I32Type = llvm::IntegerType::getInt32Ty(*CTX);
llvm::ConstantInt *I32Val =
cast<ConstantInt>(llvm::ConstantInt::get(I32Type, Idx, true));
MachineBasicBlock *Succ = JumpTables[JTIndex].MBBs[Idx];
ConstantInt *CaseVal = I32Val;
JTCases.push_back(std::make_pair(CaseVal, Succ));
}
// main->getEntryBlock().setName("entry");
unsigned int numCases = JTCases.size();
BasicBlock *def_bb =
FuncInfo->getOrCreateBasicBlock(JTList[jtIndex].DefaultMBB);
unsigned int NumCases = JTCases.size();
BasicBlock *DefBB =
FuncInfo->getOrCreateBasicBlock(JTList[JTIndex].DefaultMBB);
BasicBlock *cd_bb =
FuncInfo->getOrCreateBasicBlock(JTList[jtIndex].ConditionMBB);
BasicBlock *CondBB =
FuncInfo->getOrCreateBasicBlock(JTList[JTIndex].ConditionMBB);
// conditon instruction
Instruction *cdi = nullptr;
for (BasicBlock::iterator DI = cd_bb->begin(); DI != cd_bb->end(); DI++) {
Instruction *ins = dyn_cast<Instruction>(DI);
if (isa<LoadInst>(DI) && !cdi) {
cdi = ins;
Instruction *CondInst = nullptr;
for (BasicBlock::iterator DI = CondBB->begin(); DI != CondBB->end(); DI++) {
Instruction *Ins = dyn_cast<Instruction>(DI);
if (isa<LoadInst>(DI) && !CondInst) {
CondInst = Ins;
}
if (cdi && (ins->getOpcode() == Instruction::Sub)) {
if (isa<ConstantInt>(ins->getOperand(1))) {
ConstantInt *opr = dyn_cast<ConstantInt>(ins->getOperand(1));
if (opr->uge(0)) {
cdi = ins;
if (CondInst && (Ins->getOpcode() == Instruction::Sub)) {
if (isa<ConstantInt>(Ins->getOperand(1))) {
ConstantInt *IntOp = dyn_cast<ConstantInt>(Ins->getOperand(1));
if (IntOp->uge(0)) {
CondInst = Ins;
}
}
}
}
SwitchInst *Inst = IRB.CreateSwitch(cdi, def_bb, numCases);
for (unsigned i = 0, e = numCases; i != e; ++i) {
BasicBlock *case_bb =
FuncInfo->getOrCreateBasicBlock(JTCases[i].second);
Inst->addCase(JTCases[i].first, case_bb);
SwitchInst *Inst = IRB.CreateSwitch(CondInst, DefBB, NumCases);
for (unsigned Idx = 0, Cnt = NumCases; Idx != Cnt; ++Idx) {
BasicBlock *CaseBB =
FuncInfo->getOrCreateBasicBlock(JTCases[Idx].second);
Inst->addCase(JTCases[Idx].first, CaseBB);
}
}
} break;
@ -871,9 +871,9 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
if (DAGInfo->NPMap[Node]->UpdateCPSR) {
Value *InstLShr = IRB.CreateLShr(S0, Val1);
Value *C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
C_Flag = IRB.CreateZExt(C_Flag, Ty);
Value *Bit31 = IRB.CreateShl(C_Flag, Val2);
Value *CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
CFlag = IRB.CreateZExt(CFlag, Ty);
Value *Bit31 = IRB.CreateShl(CFlag, Val2);
Value *Inst = IRB.CreateAdd(InstLShr, Bit31);
DAGInfo->setRealValue(Node, Inst);
FuncInfo->ArgValMap[FuncInfo->NodeRegMap[Node]] = Inst;
@ -882,8 +882,8 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
emitSpecialCPSR(Inst, BB, 0);
// Update C flag.
// c flag = s0[0]
C_Flag = IRB.CreateAnd(S0, Val1);
IRB.CreateStore(C_Flag, FuncInfo->AllocaMap[2]);
CFlag = IRB.CreateAnd(S0, Val1);
IRB.CreateStore(CFlag, FuncInfo->AllocaMap[2]);
} else {
// Create new BB for EQ instructin exectute.
BasicBlock *IfBB = BasicBlock::Create(*CTX, "", BB->getParent());
@ -894,11 +894,11 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
emitCondCode(CondValue, BB, IfBB, ElseBB);
IRB.SetInsertPoint(IfBB);
Value *InstLShr = IRB.CreateLShr(S0, Val1);
Value *C_Flag = nullptr;
Value *CFlag = nullptr;
C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
C_Flag = IRB.CreateZExt(C_Flag, Ty);
Value *Bit31 = IRB.CreateShl(C_Flag, Val2);
CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
CFlag = IRB.CreateZExt(CFlag, Ty);
Value *Bit31 = IRB.CreateShl(CFlag, Val2);
Value *Inst = IRB.CreateAdd(InstLShr, Bit31);
PHINode *Phi = createAndEmitPHINode(Node, BB, IfBB, ElseBB,
dyn_cast<Instruction>(Inst));
@ -909,9 +909,9 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
}
} else {
Value *InstLShr = IRB.CreateLShr(S0, Val1);
Value *C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
C_Flag = IRB.CreateZExt(C_Flag, Ty);
Value *Bit31 = IRB.CreateShl(C_Flag, Val2);
Value *CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
CFlag = IRB.CreateZExt(CFlag, Ty);
Value *Bit31 = IRB.CreateShl(CFlag, Val2);
Value *Inst = IRB.CreateAdd(InstLShr, Bit31);
DAGInfo->setRealValue(Node, Inst);
FuncInfo->ArgValMap[FuncInfo->NodeRegMap[Node]] = Inst;
@ -920,14 +920,14 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
case EXT_ARMISD::BIC: {
Value *S0 = getIRValue(Node->getOperand(0));
Value *S1 = getIRValue(Node->getOperand(1));
Type *tp = getDefaultType();
Value *val = ConstantInt::get(tp, -1, true);
Type *Ty = getDefaultType();
Value *Val = ConstantInt::get(Ty, -1, true);
if (DAGInfo->NPMap[Node]->HasCPSR) {
unsigned CondValue = DAGInfo->NPMap[Node]->Cond;
if (DAGInfo->NPMap[Node]->UpdateCPSR) {
Value *InstXor = IRB.CreateXor(val, S1);
Value *InstXor = IRB.CreateXor(Val, S1);
Value *Inst = IRB.CreateAnd(S0, InstXor);
DAGInfo->setRealValue(Node, Inst);
@ -947,7 +947,7 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
// Emit the condition code.
emitCondCode(CondValue, BB, IfBB, ElseBB);
IRB.SetInsertPoint(IfBB);
Value *InstXor = IRB.CreateXor(val, S1);
Value *InstXor = IRB.CreateXor(Val, S1);
Value *Inst = IRB.CreateAnd(S0, InstXor);
PHINode *Phi = createAndEmitPHINode(Node, BB, IfBB, ElseBB,
dyn_cast<Instruction>(Inst));
@ -959,7 +959,7 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
}
} else {
Value *InstXor, *Inst;
InstXor = IRB.CreateXor(val, S1);
InstXor = IRB.CreateXor(Val, S1);
Inst = IRB.CreateAnd(S0, InstXor);
DAGInfo->setRealValue(Node, Inst);
FuncInfo->ArgValMap[FuncInfo->NodeRegMap[Node]] = Inst;
@ -986,12 +986,12 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
Value *S0 = getIRValue(Node->getOperand(0));
Function *CTLZ = Intrinsic::getDeclaration(BB->getParent()->getParent(),
Intrinsic::ctlz, S0->getType());
Type *i1_type = llvm::IntegerType::getInt1Ty(*CTX);
Value *is_zero_undef = ConstantInt::get(i1_type, true, true);
Type *I1ype = llvm::IntegerType::getInt1Ty(*CTX);
Value *IsZeroUndef = ConstantInt::get(I1ype, true, true);
std::vector<Value *> Vec;
Vec.push_back(S0);
Vec.push_back(is_zero_undef);
Vec.push_back(IsZeroUndef);
ArrayRef<Value *> Args(Vec);
Value *Inst = IRB.CreateCall(CTLZ, Args);
@ -1045,9 +1045,9 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
if (DAGInfo->NPMap[Node]->UpdateCPSR) {
Value *InstSub = IRB.CreateSub(S1, S2);
Value *C_Flag = nullptr;
C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *CZext = IRB.CreateZExt(C_Flag, Ty);
Value *CFlag = nullptr;
CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *CZext = IRB.CreateZExt(CFlag, Ty);
Value *InstSBC = IRB.CreateAdd(InstSub, CZext);
DAGInfo->setRealValue(Node, InstSBC);
Value *InstNot = IRB.CreateNot(S2);
@ -1063,9 +1063,9 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
IRB.SetInsertPoint(IfBB);
Value *InstSub = IRB.CreateSub(S1, S2);
Value *C_Flag = nullptr;
C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *CZext = IRB.CreateZExt(C_Flag, Ty);
Value *CFlag = nullptr;
CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *CZext = IRB.CreateZExt(CFlag, Ty);
Value *Inst = IRB.CreateAdd(InstSub, CZext);
PHINode *Phi = createAndEmitPHINode(Node, BB, IfBB, ElseBB,
dyn_cast<Instruction>(Inst));
@ -1077,9 +1077,9 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
}
} else {
Value *InstSub = IRB.CreateSub(S1, S2);
Value *C_Flag = nullptr;
C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *CZext = IRB.CreateZExt(C_Flag, Ty);
Value *CFlag = nullptr;
CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *CZext = IRB.CreateZExt(CFlag, Ty);
Value *InstSBC = IRB.CreateAdd(InstSub, CZext);
DAGInfo->setRealValue(Node, InstSBC);
}
@ -1119,24 +1119,24 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
IRB.CreateStore(Cond, dyn_cast<Value>(M.getGlobalVariable("Reserved")));
// Pattern msr CPSR_f, Rn
if (1) {
Value *Shift_Num = IRB.getInt32(28);
Value *Shift = IRB.CreateLShr(Cond, Shift_Num);
Value *ShiftNum = IRB.getInt32(28);
Value *Shift = IRB.CreateLShr(Cond, ShiftNum);
// Update N Flag.
Value *N_Cmp = IRB.getInt32(8);
Value *N_Flag = IRB.CreateICmpEQ(Shift, N_Cmp);
IRB.CreateStore(N_Flag, FuncInfo->AllocaMap[0]);
Value *NCmp = IRB.getInt32(8);
Value *NFlag = IRB.CreateICmpEQ(Shift, NCmp);
IRB.CreateStore(NFlag, FuncInfo->AllocaMap[0]);
// Update Z Flag.
Value *Z_Cmp = IRB.getInt32(4);
Value *Z_Flag = IRB.CreateICmpEQ(Shift, Z_Cmp);
IRB.CreateStore(Z_Flag, FuncInfo->AllocaMap[1]);
Value *ZCmp = IRB.getInt32(4);
Value *ZFlag = IRB.CreateICmpEQ(Shift, ZCmp);
IRB.CreateStore(ZFlag, FuncInfo->AllocaMap[1]);
// Update C Flag.
Value *C_Cmp = IRB.getInt32(2);
Value *C_Flag = IRB.CreateICmpEQ(Shift, C_Cmp);
IRB.CreateStore(C_Flag, FuncInfo->AllocaMap[2]);
Value *CCmp = IRB.getInt32(2);
Value *CFlag = IRB.CreateICmpEQ(Shift, CCmp);
IRB.CreateStore(CFlag, FuncInfo->AllocaMap[2]);
// Update V Flag.
Value *V_Cmp = IRB.getInt32(1);
Value *V_Flag = IRB.CreateICmpEQ(Shift, V_Cmp);
IRB.CreateStore(V_Flag, FuncInfo->AllocaMap[3]);
Value *VCmp = IRB.getInt32(1);
Value *VFlag = IRB.CreateICmpEQ(Shift, VCmp);
IRB.CreateStore(VFlag, FuncInfo->AllocaMap[3]);
} else {
// Pattern msr CSR_f, #const.
}
@ -1152,29 +1152,29 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
Value *BitCShift = IRB.getInt32(29);
Value *BitVShift = IRB.getInt32(28);
Value *N_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *Z_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *V_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
Value *NFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[0]);
Value *ZFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[1]);
Value *CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *VFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[3]);
N_Flag = IRB.CreateZExt(N_Flag, Ty);
Z_Flag = IRB.CreateZExt(Z_Flag, Ty);
C_Flag = IRB.CreateZExt(C_Flag, Ty);
V_Flag = IRB.CreateZExt(V_Flag, Ty);
NFlag = IRB.CreateZExt(NFlag, Ty);
ZFlag = IRB.CreateZExt(ZFlag, Ty);
CFlag = IRB.CreateZExt(CFlag, Ty);
VFlag = IRB.CreateZExt(VFlag, Ty);
Value *N_Shift = IRB.CreateShl(N_Flag, BitNShift);
Value *Z_Shift = IRB.CreateShl(Z_Flag, BitZShift);
Value *C_Shift = IRB.CreateShl(C_Flag, BitCShift);
Value *V_Shift = IRB.CreateShl(V_Flag, BitVShift);
Value *NZ_Val = IRB.CreateAdd(N_Shift, Z_Shift);
Value *CV_Val = IRB.CreateAdd(C_Shift, V_Shift);
Value *NZCV_Val = IRB.CreateAdd(NZ_Val, CV_Val);
Value *NShift = IRB.CreateShl(NFlag, BitNShift);
Value *ZShift = IRB.CreateShl(ZFlag, BitZShift);
Value *CShift = IRB.CreateShl(CFlag, BitCShift);
Value *VShift = IRB.CreateShl(VFlag, BitVShift);
Value *NZVal = IRB.CreateAdd(NShift, ZShift);
Value *CVVal = IRB.CreateAdd(CShift, VShift);
Value *NZCVVal = IRB.CreateAdd(NZVal, CVVal);
Value *Reserved =
callCreateAlignedLoad(dyn_cast<Value>(M.getGlobalVariable("Reserved")));
Value *CPSR_Val = IRB.CreateAdd(NZCV_Val, Reserved);
Value *Rn_Ptr = IRB.CreateIntToPtr(Rn, PtrTy);
Value *RnStore = IRB.CreateStore(CPSR_Val, Rn_Ptr);
Value *CPSRVal = IRB.CreateAdd(NZCVVal, Reserved);
Value *RnPtr = IRB.CreateIntToPtr(Rn, PtrTy);
Value *RnStore = IRB.CreateStore(CPSRVal, RnPtr);
DAGInfo->setRealValue(Node, RnStore);
FuncInfo->ArgValMap[FuncInfo->NodeRegMap[Node]] = RnStore;
@ -1189,9 +1189,9 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
if (DAGInfo->NPMap[Node]->UpdateCPSR) {
// Create add emit.
Value *C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *Result = IRB.CreateAdd(S0, S1);
Value *CZext = IRB.CreateZExt(C_Flag, OperandTy);
Value *CZext = IRB.CreateZExt(CFlag, OperandTy);
Value *InstADC = IRB.CreateAdd(Result, CZext);
DAGInfo->setRealValue(Node, InstADC);
FuncInfo->ArgValMap[FuncInfo->NodeRegMap[Node]] =
@ -1213,10 +1213,10 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
// Emit the condition code.
emitCondCode(CondValue, BB, IfBB, ElseBB);
Value *C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
IRB.SetInsertPoint(IfBB);
Value *InstAdd = IRB.CreateAdd(S0, S1);
Value *CZext = IRB.CreateZExtOrTrunc(C_Flag, OperandTy);
Value *CZext = IRB.CreateZExtOrTrunc(CFlag, OperandTy);
Value *Inst = IRB.CreateAdd(InstAdd, CZext);
PHINode *Phi = createAndEmitPHINode(Node, BB, IfBB, ElseBB,
dyn_cast<Instruction>(Inst));
@ -1227,9 +1227,9 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
IRB.SetInsertPoint(ElseBB);
}
} else {
Value *C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *Inst = IRB.CreateAdd(S0, S1);
Value *CTrunc = IRB.CreateZExtOrTrunc(C_Flag, getDefaultType());
Value *CTrunc = IRB.CreateZExtOrTrunc(CFlag, getDefaultType());
Value *InstADC = IRB.CreateAdd(Inst, CTrunc);
DAGInfo->setRealValue(Node, InstADC);
@ -1240,8 +1240,8 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
Value *S0 = getIRValue(Node->getOperand(0));
Value *S1 = getIRValue(Node->getOperand(1));
Value *C_Flag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *CZext = IRB.CreateZExt(C_Flag, getDefaultType());
Value *CFlag = callCreateAlignedLoad(FuncInfo->AllocaMap[2]);
Value *CZext = IRB.CreateZExt(CFlag, getDefaultType());
Value *Inst = IRB.CreateAdd(S0, CZext);
Inst = IRB.CreateSub(S1, Inst);
@ -1251,14 +1251,14 @@ void IREmitter::emitSpecialNode(SDNode *Node) {
case EXT_ARMISD::UXTB: {
Value *S1 = getIRValue(Node->getOperand(1));
Value *Rotation = getIRValue(Node->getOperand(2));
Value *ror_val = ConstantInt::get(getDefaultType(), 8, true);
Value *add_val = ConstantInt::get(getDefaultType(), 0, true);
Value *and_val = ConstantInt::get(getDefaultType(), 0xff, true);
Value *Inst_mul = IRB.CreateMul(Rotation, ror_val);
Value *Inst_lshr = IRB.CreateLShr(S1, Inst_mul);
Value *Inst_add = IRB.CreateAdd(Inst_lshr, add_val);
Value *Inst_and = IRB.CreateAnd(Inst_add, and_val);
DAGInfo->setRealValue(Node, Inst_and);
Value *RorVal = ConstantInt::get(getDefaultType(), 8, true);
Value *AddVal = ConstantInt::get(getDefaultType(), 0, true);
Value *AndVal = ConstantInt::get(getDefaultType(), 0xff, true);
Value *InstMul = IRB.CreateMul(Rotation, RorVal);
Value *InstLshr = IRB.CreateLShr(S1, InstMul);
Value *InstAdd = IRB.CreateAdd(InstLshr, AddVal);
Value *InstAnd = IRB.CreateAnd(InstAdd, AndVal);
DAGInfo->setRealValue(Node, InstAnd);
} break;
case EXT_ARMISD::RSB: {
Value *S0 = getIRValue(Node->getOperand(0));

12
ARM/DAG/InstSelector.cpp
Просмотреть файл

@ -511,17 +511,17 @@ void InstSelector::selectCode(SDNode *N) {
case ARM::tCMPi8:
case ARM::t2CMPrr:
case ARM::tCMPr: {
SDValue cmpl = N->getOperand(0);
SDValue cmph = N->getOperand(1);
if (RegisterSDNode::classof(cmph.getNode()))
cmph = FuncInfo->getValFromRegMap(N->getOperand(1));
cmpl = FuncInfo->getValFromRegMap(cmpl);
SDValue Cmpl = N->getOperand(0);
SDValue Cmph = N->getOperand(1);
if (RegisterSDNode::classof(Cmph.getNode()))
Cmph = FuncInfo->getValFromRegMap(N->getOperand(1));
Cmpl = FuncInfo->getValFromRegMap(Cmpl);
// Create condition SDValuleR
// TODO: It should be verified why this type node can not be added Metadata
// Operand.
SDNode *Node = CurDAG
->getNode(ISD::SETCC, Dl, getDefaultEVT(), cmpl, cmph
->getNode(ISD::SETCC, Dl, getDefaultEVT(), Cmpl, Cmph
/* , getMDOperand(N) */)
.getNode();

5
CMakeLists.txt
Просмотреть файл

@ -2,6 +2,11 @@ if(NOT (LLVM_TARGETS_TO_BUILD MATCHES "X86" OR LLVM_TARGETS_TO_BUILD MATCHES "AR
return()
endif()
if (MCTOLL_CLANG_TIDY)
message(STATUS "Enabled clang-tidy checks for llvm-mctoll source files")
set(CMAKE_CXX_CLANG_TIDY "clang-tidy")
endif()
set(LLVM_MCTOLL_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
set(LLVM_MCTOLL_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR})

8
COFFDump.cpp
Просмотреть файл

@ -14,18 +14,20 @@
///
//===----------------------------------------------------------------------===//
// NOLINTBEGIN
#include "llvm-mctoll.h"
#include "Raiser/ModuleRaiser.h"
#include "llvm/Object/COFF.h"
#include "llvm/Object/COFFImportFile.h"
#include "llvm/Object/ObjectFile.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/Win64EH.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cstring>
#include <system_error>
#include "Raiser/ModuleRaiser.h"
using namespace llvm;
using namespace llvm::mctoll;
@ -732,3 +734,5 @@ void mctoll::printCOFFSymbolTable(const COFFObjectFile *coff) {
}
}
}
// NOLINTEND

17
MachODump.cpp
Просмотреть файл

@ -10,8 +10,11 @@
//
//===----------------------------------------------------------------------===//
#include "llvm-mctoll.h"
// NOLINTBEGIN
#include "llvm-c/Disassembler.h"
#include "llvm-mctoll.h"
#include "Raiser/ModuleRaiser.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/Triple.h"
@ -42,13 +45,12 @@
#include "llvm/Support/GraphWriter.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Support/ToolOutputFile.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cstring>
#include <system_error>
#include "Raiser/ModuleRaiser.h"
#ifdef HAVE_LIBXAR
extern "C" {
@ -957,7 +959,7 @@ void mctoll::parseInputMachO(StringRef Filename) {
} else if (auto E = isNotObjectErrorInvalidFileType(
ObjOrErr.takeError())) {
reportError(std::move(E), Filename, StringRef(),
ArchitectureName);
ArchitectureName);
continue;
} else if (Expected<std::unique_ptr<Archive>> AOrErr =
I->getAsArchive()) {
@ -3295,7 +3297,7 @@ static const char *GuessLiteralPointer(uint64_t ReferenceValue,
auto SymOrErr = Symbol.getValue();
if (!SymOrErr)
reportError(SymOrErr.takeError(),
Symbol.getObject()->getFileName());
Symbol.getObject()->getFileName());
ReferenceValue = *SymOrErr;
}
}
@ -3874,7 +3876,7 @@ static void DisassembleMachO(StringRef Filename, MachOObjectFile *MachOOF,
auto SymOrErr = Symbols[SymIdx].getValue();
if (!SymOrErr)
reportError(SymOrErr.takeError(),
Symbols[SymIdx].getObject()->getFileName());
Symbols[SymIdx].getObject()->getFileName());
uint64_t Start = *SymOrErr;
uint64_t SectionAddress = Sections[SectIdx].getAddress();
Start -= SectionAddress;
@ -3901,7 +3903,7 @@ static void DisassembleMachO(StringRef Filename, MachOObjectFile *MachOOF,
auto SymOrErr = Symbols[NextSymIdx].getValue();
if (!SymOrErr)
reportError(SymOrErr.takeError(),
Symbols[NextSymIdx].getObject()->getFileName());
Symbols[NextSymIdx].getObject()->getFileName());
NextSym = *SymOrErr;
NextSym -= SectionAddress;
@ -6125,3 +6127,4 @@ static const char *get_dyld_bind_info_symbolname(uint64_t ReferenceValue,
auto name = info->bindtable->lookup(ReferenceValue);
return !name.empty() ? name.data() : nullptr;
}
// NOLINTEND

3
README.md
Просмотреть файл

@ -55,6 +55,9 @@ git checkout <hash from llvm-project-git-commit-to-use.txt>
```sh
cmake -S llvm -B <build-dir> -G "Ninja" -DLLVM_TARGETS_TO_BUILD="X86;ARM" -DLLVM_ENABLE_PROJECTS="clang;lld" -DLLVM_ENABLE_ASSERTIONS=true -DCMAKE_BUILD_TYPE=<build-type>
```
`clang-tidy` checks can be enabled for the `llvm-mctoll` project sources by using the additional cmake option `-DMCTOLL_CLANG_TIDY`.
5. Build `llvm-mctoll`
```sh
cmake --build <build-dir> -- llvm-mctoll

5
Raiser/FunctionFilter.cpp
Просмотреть файл

@ -296,11 +296,12 @@ bool FunctionFilter::readFilterFunctionConfigFile(
if (Grp[1].equals(sys::path::filename(M.getSourceFileName()))) {
if (FFType == FunctionFilter::FILTER_EXCLUDE) {
addExcludedFunction(Grp[2]);
continue;
} else if (FFType == FunctionFilter::FILTER_INCLUDE) {
addIncludedFunction(Grp[2]);
continue;
} else {
assert(false && "Unexpected function filter type");
}
continue;
}
}

9
Raiser/IncludedFileInfo.cpp
Просмотреть файл

@ -21,7 +21,9 @@
#include "clang/Tooling/Tooling.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include <clang-c/Index.h>
#include <memory>
#include <sstream>
#include <string>
@ -201,8 +203,8 @@ Function *IncludedFileInfo::CreateFunction(StringRef &CFuncName,
MR.getFunctionFilter()->getPrimitiveDataType(RetAndArgs.ReturnType);
std::vector<Type *> ArgVec;
for (StringRef Arg : RetAndArgs.Arguments) {
Type *argType = MR.getFunctionFilter()->getPrimitiveDataType(Arg);
ArgVec.push_back(argType);
Type *ArgType = MR.getFunctionFilter()->getPrimitiveDataType(Arg);
ArgVec.push_back(ArgType);
}
ArrayRef<Type *> Args(ArgVec);
@ -247,7 +249,8 @@ bool IncludedFileInfo::getExternalFunctionPrototype(
std::string ErrorMessage;
std::unique_ptr<clang::tooling::CompilationDatabase> Compilations =
clang::tooling::FixedCompilationDatabase::loadFromCommandLine(ArgSz, ToolArgv, ErrorMessage);
clang::tooling::FixedCompilationDatabase::loadFromCommandLine(
ArgSz, ToolArgv, ErrorMessage);
if (!ErrorMessage.empty())
llvm::errs() << ErrorMessage.append("\n");

22
Raiser/MCInstRaiser.cpp
Просмотреть файл

@ -120,11 +120,11 @@ void MCInstRaiser::buildCFG(MachineFunction &MF, const MCInstrAnalysis *MIA,
if (MF.size()) {
// If the terminating instruction of last MBB is a branch instruction,
// ensure appropriate control flow edges are added.
std::vector<uint64_t> termMCInstTargets;
auto mcIDMapIter = InstMap.rbegin();
if (mcIDMapIter != InstMap.rend()) {
uint64_t termMCInstIndex = mcIDMapIter->first;
auto termMCInst = mcIDMapIter->second.getMCInst();
std::vector<uint64_t> TermMCInstTargets;
auto MCIDMapIter = InstMap.rbegin();
if (MCIDMapIter != InstMap.rend()) {
uint64_t TermMCInstIndex = MCIDMapIter->first;
auto TermMCInst = MCIDMapIter->second.getMCInst();
// The following code handles a situation where the text section ends with
// an unconditional branch. In such situations, no fall-through target is
// recorded in targetIndices since offset after the branch is not within
@ -133,15 +133,15 @@ void MCInstRaiser::buildCFG(MachineFunction &MF, const MCInstrAnalysis *MIA,
// to add them for the last MBB with a branch. If the function were padded
// with noop, this would not trigger and the case would be naturally
// handled in the above loop.
if (MIA->isBranch(termMCInst)) {
if (MIA->isBranch(TermMCInst)) {
uint64_t Target;
// Get its target
assert(!MIA->isConditionalBranch(termMCInst) &&
assert(!MIA->isConditionalBranch(TermMCInst) &&
"Unexpected conditional branch at the end of text section");
// Since this instruction is the last one, its size is
// (FuncEnd - termMCInstIndex).
if (MIA->evaluateBranch(termMCInst, termMCInstIndex,
(FuncEnd - termMCInstIndex), Target)) {
if (MIA->evaluateBranch(TermMCInst, TermMCInstIndex,
(FuncEnd - TermMCInstIndex), Target)) {
// Record its target if it is within the function start
// and function end. Branch instructions with such
// targets are - for now - treated not to be instructions
@ -149,13 +149,13 @@ void MCInstRaiser::buildCFG(MachineFunction &MF, const MCInstrAnalysis *MIA,
// TODO: How to handle any branches out of these bounds?
// Does such a situation exist?
if ((Target >= FuncStart) && (Target < FuncEnd)) {
termMCInstTargets.push_back(Target);
TermMCInstTargets.push_back(Target);
}
}
}
}
MBBNumToMCInstTargetsMap.insert(
std::make_pair(MF.back().getNumber(), termMCInstTargets));
std::make_pair(MF.back().getNumber(), TermMCInstTargets));
InstToMBBNum.insert(
std::make_pair(CurMBBEntryInstIndex, MF.back().getNumber()));
}

2
Raiser/ModuleRaiser.cpp
Просмотреть файл

@ -203,7 +203,7 @@ bool ModuleRaiser::runMachineFunctionPasses() {
// that might call those whose prototypes were not yet constructed.
bool AllPrototypesConstructed;
const int IterCount = 2;
for (int i = 0; i < IterCount; i++) {
for (int Idx = 0; Idx < IterCount; Idx++) {
AllPrototypesConstructed = true;
for (auto *MFR : MFRaiserVector) {
LLVM_DEBUG(dbgs() << "Build Prototype for : "

6
X86/X86AdditionalInstrInfo.cpp
Просмотреть файл

@ -19,7 +19,7 @@
using namespace llvm;
using namespace llvm::mctoll;
static constexpr const_addl_instr_info::value_type mapdata[] = {
static constexpr const_addl_instr_info::value_type MapData[] = {
{X86::AAA, {0, Unknown}},
{X86::AAD8i8, {0, Unknown}},
{X86::AAM8i8, {0, Unknown}},
@ -13935,5 +13935,5 @@ static constexpr const_addl_instr_info::value_type mapdata[] = {
{X86::XSTORE, {0, Unknown}},
{X86::XTEST, {0, Unknown}}};
const const_addl_instr_info mctoll::X86AddlInstrInfo(std::begin(mapdata),
std::end(mapdata));
const const_addl_instr_info mctoll::X86AddlInstrInfo(std::begin(MapData),
std::end(MapData));

162
X86/X86FuncPrototypeDiscovery.cpp
Просмотреть файл

@ -59,44 +59,44 @@ static bool hasExactImplicitDefOfPhysReg(const MachineInstr &I, unsigned Reg,
// register PReg according to C calling convention.
int X86MachineInstructionRaiser::getArgumentNumber(unsigned PReg) {
int pos = -1;
int Pos = -1;
if (is8BitPhysReg(PReg)) {
int diff = std::distance(
int Diff = std::distance(
GPR64ArgRegs8Bit.begin(),
std::find(GPR64ArgRegs8Bit.begin(), GPR64ArgRegs8Bit.end(), PReg));
if ((diff >= 0) && (diff < (int)GPR64ArgRegs8Bit.size())) {
pos = diff + 1;
if ((Diff >= 0) && (Diff < (int)GPR64ArgRegs8Bit.size())) {
Pos = Diff + 1;
}
} else if (is16BitPhysReg(PReg)) {
int diff = std::distance(
int Diff = std::distance(
GPR64ArgRegs16Bit.begin(),
std::find(GPR64ArgRegs16Bit.begin(), GPR64ArgRegs16Bit.end(), PReg));
if ((diff >= 0) && (diff < (int)GPR64ArgRegs16Bit.size())) {
pos = diff + 1;
if ((Diff >= 0) && (Diff < (int)GPR64ArgRegs16Bit.size())) {
Pos = Diff + 1;
}
} else if (is32BitPhysReg(PReg)) {
int diff = std::distance(
int Diff = std::distance(
GPR64ArgRegs32Bit.begin(),
std::find(GPR64ArgRegs32Bit.begin(), GPR64ArgRegs32Bit.end(), PReg));
if ((diff >= 0) && (diff < (int)GPR64ArgRegs32Bit.size())) {
pos = diff + 1;
if ((Diff >= 0) && (Diff < (int)GPR64ArgRegs32Bit.size())) {
Pos = Diff + 1;
}
} else if (is64BitPhysReg(PReg)) {
int diff = std::distance(
int Diff = std::distance(
GPR64ArgRegs64Bit.begin(),
std::find(GPR64ArgRegs64Bit.begin(), GPR64ArgRegs64Bit.end(), PReg));
if ((diff >= 0) && (diff < (int)GPR64ArgRegs64Bit.size())) {
pos = diff + 1;
if ((Diff >= 0) && (Diff < (int)GPR64ArgRegs64Bit.size())) {
Pos = Diff + 1;
}
} else if (isSSE2Reg(PReg)) {
int diff = std::distance(
int Diff = std::distance(
SSEArgRegs64Bit.begin(),
std::find(SSEArgRegs64Bit.begin(), SSEArgRegs64Bit.end(), PReg));
if ((diff >= 0) && (diff < (int)SSEArgRegs64Bit.size())) {
pos = diff + 1;
if ((Diff >= 0) && (Diff < (int)SSEArgRegs64Bit.size())) {
Pos = Diff + 1;
}
}
return pos;
return Pos;
}
// Add Reg to LiveInSet. This function adds the actual register Reg - not its
@ -146,7 +146,7 @@ void X86MachineInstructionRaiser::addRegisterToFunctionLiveInSet(
}
Type *X86MachineInstructionRaiser::getFunctionReturnType() {
Type *returnType = nullptr;
Type *ReturnType = nullptr;
assert(x86TargetInfo.is64Bit() && "Only x86_64 binaries supported for now");
@ -162,16 +162,16 @@ Type *X86MachineInstructionRaiser::getFunctionReturnType() {
}
}
while (!WorkList.empty() && returnType == nullptr) {
while (!WorkList.empty() && ReturnType == nullptr) {
MachineBasicBlock *MBB = WorkList.pop_back_val();
returnType = getReachingReturnType(*MBB);
ReturnType = getReachingReturnType(*MBB);
}
// If return type is still not discovered, assume it to be void
if (returnType == nullptr)
returnType = Type::getVoidTy(MF.getFunction().getContext());
if (ReturnType == nullptr)
ReturnType = Type::getVoidTy(MF.getFunction().getContext());
return returnType;
return ReturnType;
}
// Construct prototype of the Function for the MachineFunction being raised.
@ -188,7 +188,7 @@ FunctionType *X86MachineInstructionRaiser::getRaisedFunctionPrototype() {
unlinkEmptyMBBs();
MF.getRegInfo().freezeReservedRegs(MF);
std::vector<Type *> argTypeVector;
std::vector<Type *> ArgTypeVector;
// 1. Discover function arguments.
// Function livein set will contain the actual registers that are
@ -231,7 +231,7 @@ FunctionType *X86MachineInstructionRaiser::getRaisedFunctionPrototype() {
}
// Union of defined registers of all predecessors
for (auto PredMBB : MBB->predecessors()) {
for (auto *PredMBB : MBB->predecessors()) {
auto PredMBBRegDefSizeIter =
PerMBBDefinedPhysRegMap.find(PredMBB->getNumber());
// Register defs of all predecessors may not be available if MBB
@ -285,7 +285,7 @@ FunctionType *X86MachineInstructionRaiser::getRaisedFunctionPrototype() {
if (Use1Op.getReg() != Use2Op.getReg()) {
// If the source register has not been used before, add it to
// the list of first use registers.
unsigned UseReg = Use1Op.getReg();
Register UseReg = Use1Op.getReg();
if (MBBDefRegs.find(find64BitSuperReg(UseReg)) == MBBDefRegs.end())
addRegisterToFunctionLiveInSet(FunctionLiveInRegs, UseReg);
@ -295,7 +295,7 @@ FunctionType *X86MachineInstructionRaiser::getRaisedFunctionPrototype() {
}
// Add def reg to MBBDefRegs set
unsigned DestReg = DestOp.getReg();
Register DestReg = DestOp.getReg();
// We need the last definition. Even if there is a previous definition,
// it is correct to just over write the size information.
MBBDefRegs[find64BitSuperReg(DestReg)] =
@ -417,7 +417,7 @@ FunctionType *X86MachineInstructionRaiser::getRaisedFunctionPrototype() {
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
Register Reg = MO.getReg();
if (!(isGPReg(Reg) || isSSE2Reg(Reg)))
continue;
@ -433,7 +433,7 @@ FunctionType *X86MachineInstructionRaiser::getRaisedFunctionPrototype() {
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
Register Reg = MO.getReg();
if (!(isGPReg(Reg) || isSSE2Reg(Reg)))
continue;
@ -460,11 +460,11 @@ FunctionType *X86MachineInstructionRaiser::getRaisedFunctionPrototype() {
// Use the first register usage list to form argument vector using
// first argument register usage.
buildFuncArgTypeVector(FunctionLiveInRegs, argTypeVector);
buildFuncArgTypeVector(FunctionLiveInRegs, ArgTypeVector);
// 2. Discover function return type
Type *returnType = DiscoveredRetType != nullptr ? DiscoveredRetType
Type *ReturnType = DiscoveredRetType != nullptr ? DiscoveredRetType
: getFunctionReturnType();
if (returnType == nullptr)
if (ReturnType == nullptr)
return nullptr;
// The Function object associated with current MachineFunction object
@ -476,24 +476,24 @@ FunctionType *X86MachineInstructionRaiser::getRaisedFunctionPrototype() {
// module with the correct Function object being created now.
// 1. Get the current function name
StringRef functionName = MF.getFunction().getName();
Module *module = MR->getModule();
StringRef FunctionName = MF.getFunction().getName();
Module *Mod = MR->getModule();
// 2. Get the corresponding Function* registered in module
Function *tempFunctionPtr = module->getFunction(functionName);
assert(tempFunctionPtr != nullptr && "Function not found in module list");
Function *TempFunctionPtr = Mod->getFunction(FunctionName);
assert(TempFunctionPtr != nullptr && "Function not found in module list");
// 4. Delete the tempFunc from module list to allow for the creation of the
// real function to add the correct one to FunctionList of the module.
module->getFunctionList().remove(tempFunctionPtr);
Mod->getFunctionList().remove(TempFunctionPtr);
// 3. Create a function type using the discovered arguments and return value.
FunctionType *FT =
FunctionType::get(returnType, argTypeVector, false /* isVarArg*/);
FunctionType::get(ReturnType, ArgTypeVector, false /* isVarArg*/);
// 4. Create the real Function now that we have discovered the arguments.
RaisedFunction =
Function::Create(FT, GlobalValue::ExternalLinkage, functionName, module);
Function::Create(FT, GlobalValue::ExternalLinkage, FunctionName, Mod);
// Set global linkage
RaisedFunction->setLinkage(GlobalValue::ExternalLinkage);
@ -506,15 +506,15 @@ FunctionType *X86MachineInstructionRaiser::getRaisedFunctionPrototype() {
// Note: Call to arg_begin() calls Function::BuildLazyArguments()
// to build the arguments.
Function::arg_iterator ArgIt = RaisedFunction->arg_begin();
unsigned numFuncArgs = RaisedFunction->arg_size();
StringRef prefix("arg");
unsigned NumFuncArgs = RaisedFunction->arg_size();
StringRef Prefix("arg");
// Set the name.
for (unsigned i = 0; i < numFuncArgs; ++i, ++ArgIt)
ArgIt->setName(prefix + std::to_string(i + 1));
for (unsigned Idx = 0; Idx < NumFuncArgs; ++Idx, ++ArgIt)
ArgIt->setName(Prefix + std::to_string(Idx + 1));
// Insert the map of raised function to tempFunctionPointer.
const_cast<ModuleRaiser *>(MR)->insertPlaceholderRaisedFunctionMap(
RaisedFunction, tempFunctionPtr);
RaisedFunction, TempFunctionPtr);
return RaisedFunction->getFunctionType();
}
@ -625,11 +625,11 @@ X86MachineInstructionRaiser::getReturnTypeFromMBB(const MachineBasicBlock &MBB,
if (I->isReturn())
continue;
// No need to inspect padding instructions. ld uses nop and lld uses int3 for
// alignment padding in text section.
// No need to inspect padding instructions. ld uses nop and lld uses int3
// for alignment padding in text section.
auto Opcode = I->getOpcode();
if (isNoop(Opcode) || (Opcode == X86::INT3))
continue;
continue;
unsigned DefReg = X86::NoRegister;
const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
@ -637,7 +637,7 @@ X86MachineInstructionRaiser::getReturnTypeFromMBB(const MachineBasicBlock &MBB,
if (I->getDesc().getNumDefs() != 0) {
const MachineOperand &MO = I->getOperand(0);
if (MO.isReg()) {
unsigned PReg = MO.getReg();
Register PReg = MO.getReg();
if (!Register::isPhysicalRegister(PReg))
continue;
@ -645,7 +645,7 @@ X86MachineInstructionRaiser::getReturnTypeFromMBB(const MachineBasicBlock &MBB,
for (MCSubRegIterator SubRegs(X86::RAX, TRI,
/*IncludeSelf=*/true);
(SubRegs.isValid() && DefReg == X86::NoRegister); ++SubRegs) {
if (*SubRegs == PReg) {
if (*SubRegs == PReg.asMCReg()) {
DefReg = *SubRegs;
break;
}
@ -698,45 +698,45 @@ X86MachineInstructionRaiser::getReturnTypeFromMBB(const MachineBasicBlock &MBB,
bool X86MachineInstructionRaiser::buildFuncArgTypeVector(
const std::set<MCPhysReg> &PhysRegs, std::vector<Type *> &ArgTyVec) {
// A map of argument number and type as discovered
std::map<unsigned int, Type *> argNumTypeMap;
std::map<unsigned int, Type *> sseArgNumTypeMap;
llvm::LLVMContext &funcLLVMContext = MF.getFunction().getContext();
std::map<unsigned int, Type *> ArgNumTypeMap;
std::map<unsigned int, Type *> SSEArgNumTypeMap;
llvm::LLVMContext &Ctx = MF.getFunction().getContext();
int MaxGPArgNum = 0;
int MaxSSEArgNum = 0;
for (MCPhysReg PReg : PhysRegs) {
// If Reg is an argument register per C standard calling convention
// construct function argument.
int argNum = getArgumentNumber(PReg);
if (argNum > 0) {
int ArgNum = getArgumentNumber(PReg);
if (ArgNum > 0) {
if (isGPReg(PReg)) {
if (argNum > MaxGPArgNum)
MaxGPArgNum = argNum;
if (ArgNum > MaxGPArgNum)
MaxGPArgNum = ArgNum;
// Make sure each argument position is discovered only once
assert(argNumTypeMap.find(argNum) == argNumTypeMap.end());
assert(ArgNumTypeMap.find(ArgNum) == ArgNumTypeMap.end());
if (is8BitPhysReg(PReg)) {
argNumTypeMap.insert(
std::make_pair(argNum, Type::getInt8Ty(funcLLVMContext)));
ArgNumTypeMap.insert(
std::make_pair(ArgNum, Type::getInt8Ty(Ctx)));
} else if (is16BitPhysReg(PReg)) {
argNumTypeMap.insert(
std::make_pair(argNum, Type::getInt16Ty(funcLLVMContext)));
ArgNumTypeMap.insert(
std::make_pair(ArgNum, Type::getInt16Ty(Ctx)));
} else if (is32BitPhysReg(PReg)) {
argNumTypeMap.insert(
std::make_pair(argNum, Type::getInt32Ty(funcLLVMContext)));
ArgNumTypeMap.insert(
std::make_pair(ArgNum, Type::getInt32Ty(Ctx)));
} else if (is64BitPhysReg(PReg)) {
argNumTypeMap.insert(
std::make_pair(argNum, Type::getInt64Ty(funcLLVMContext)));
ArgNumTypeMap.insert(
std::make_pair(ArgNum, Type::getInt64Ty(Ctx)));
}
} else if (isSSE2Reg(PReg)) {
if (argNum > MaxSSEArgNum)
MaxSSEArgNum = argNum;
if (ArgNum > MaxSSEArgNum)
MaxSSEArgNum = ArgNum;
// Make sure each argument position is discovered only once
assert(sseArgNumTypeMap.find(argNum) == sseArgNumTypeMap.end());
sseArgNumTypeMap.insert(
std::make_pair(argNum, Type::getDoubleTy(funcLLVMContext)));
assert(SSEArgNumTypeMap.find(ArgNum) == SSEArgNumTypeMap.end());
SSEArgNumTypeMap.insert(
std::make_pair(ArgNum, Type::getDoubleTy(Ctx)));
} else {
outs() << x86RegisterInfo->getRegAsmName(PReg) << "\n";
llvm_unreachable("Unhandled register type encountered in binary");
@ -746,25 +746,25 @@ bool X86MachineInstructionRaiser::buildFuncArgTypeVector(
// Build argument type vector that will be used to build FunctionType
// while sanity checking arguments discovered
for (int i = 1; i <= MaxGPArgNum; i++) {
auto argIter = argNumTypeMap.find(i);
if (argIter == argNumTypeMap.end()) {
for (int Idx = 1; Idx <= MaxGPArgNum; Idx++) {
auto ArgIter = ArgNumTypeMap.find(Idx);
if (ArgIter == ArgNumTypeMap.end()) {
// Argument register not used. It is most likely optimized.
// The argument is not used. Safe to consider it to be of 64-bit
// type.
ArgTyVec.push_back(Type::getInt64Ty(funcLLVMContext));
ArgTyVec.push_back(Type::getInt64Ty(Ctx));
} else
ArgTyVec.push_back(argNumTypeMap.find(i)->second);
ArgTyVec.push_back(ArgNumTypeMap.find(Idx)->second);
}
// TODO: for now we just assume that SSE registers are always the last
// arguments This may work when compiling to X86 using the System V ABI, not
// necessarily for other ABIs.
for (int i = 1; i <= MaxSSEArgNum; i++) {
auto argIter = sseArgNumTypeMap.find(i);
if (argIter == sseArgNumTypeMap.end()) {
ArgTyVec.push_back(Type::getDoubleTy(funcLLVMContext));
for (int Idx = 1; Idx <= MaxSSEArgNum; Idx++) {
auto ArgIter = SSEArgNumTypeMap.find(Idx);
if (ArgIter == SSEArgNumTypeMap.end()) {
ArgTyVec.push_back(Type::getDoubleTy(Ctx));
} else {
ArgTyVec.push_back(argIter->second);
ArgTyVec.push_back(ArgIter->second);
}
}
return true;
@ -836,7 +836,7 @@ X86MachineInstructionRaiser::getCalledFunction(const MachineInstr &MI) {
// Search the called function from the excluded set of function filter.
if (CalledFunc == nullptr) {
auto Filter = MR->getFunctionFilter();
auto *Filter = MR->getFunctionFilter();
CalledFunc = Filter->findFunctionByIndex(
MCInstOffset + RelCallTargetOffset + MCInstSize,
FunctionFilter::FILTER_EXCLUDE);

6
X86/X86JumpTables.cpp
Просмотреть файл

@ -169,13 +169,13 @@ bool X86MachineInstructionRaiser::raiseMachineJumpTable() {
size_t CurReadByteOffset = JmpTblBaseOffset;
while (CurReadByteOffset < DataSize) {
ArrayRef<uint8_t> v(MemReadTargetByteSz);
ArrayRef<uint8_t> ARef(MemReadTargetByteSz);
if (CurReadByteOffset + MemReadTargetByteSz > DataSize)
break;
Error EC = SectionContent.readBytes(CurReadByteOffset,
MemReadTargetByteSz, v);
MemReadTargetByteSz, ARef);
// Eat the error; the section does not have jumptable data
if (EC) {
handleAllErrors(std::move(EC),
@ -184,7 +184,7 @@ bool X86MachineInstructionRaiser::raiseMachineJumpTable() {
}
uint64_t JmpTgtMemAddr =
llvm::support::endian::read64le(v.data());
llvm::support::endian::read64le(ARef.data());
// get MBB corresponding to file offset into text section of
// JmpTgtMemAddr
auto MBBNo = MCIR->getMBBNumberOfMCInstOffset(

923
X86/X86MachineInstructionRaiser.cpp
Просмотреть файл

Разница между файлами не показана из-за своего большого размера Загрузить разницу

76
X86/X86MachineInstructionRaiserSSE.cpp
Просмотреть файл

@ -12,15 +12,17 @@
//===----------------------------------------------------------------------===//
#include "IncludedFileInfo.h"
#include "llvm-mctoll.h"
#include "X86InstrBuilder.h"
#include "X86MachineInstructionRaiser.h"
#include "X86RaisedValueTracker.h"
#include "X86RegisterUtils.h"
#include "llvm-mctoll.h"
#include "X86Subtarget.h"
#include "llvm/Object/ELF.h"
#include "llvm/Object/ELFObjectFile.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include <X86InstrBuilder.h>
#include <X86Subtarget.h>
#include <iterator>
using namespace llvm;
@ -34,7 +36,8 @@ bool X86MachineInstructionRaiser::raiseSSECompareMachineInstr(
int MBBNo = MI.getParent()->getNumber();
MCInstrDesc MCIDesc = MI.getDesc();
assert((MCIDesc.getNumDefs() == 0 || MCIDesc.getNumDefs() == 1) &&
(MCIDesc.getNumOperands() == 2 || MCIDesc.getNumOperands() == 3 || MCIDesc.getNumOperands() == 4) &&
(MCIDesc.getNumOperands() == 2 || MCIDesc.getNumOperands() == 3 ||
MCIDesc.getNumOperands() == 4) &&
"Unexpected operands found in SSE compare instruction");
unsigned int Src1Idx, Src2Idx;
@ -77,8 +80,10 @@ bool X86MachineInstructionRaiser::raiseSSECompareMachineInstr(
getRaisedValues()->getSSEInstructionType(MI, SSERegSzInBits, Ctx);
BasicBlock *RaisedBB = getRaisedBasicBlock(MI.getParent());
CmpOpVal1 = getRaisedValues()->reinterpretSSERegValue(CmpOpVal1, OpType, RaisedBB);
CmpOpVal2 = getRaisedValues()->reinterpretSSERegValue(CmpOpVal2, OpType, RaisedBB);
CmpOpVal1 =
getRaisedValues()->reinterpretSSERegValue(CmpOpVal1, OpType, RaisedBB);
CmpOpVal2 =
getRaisedValues()->reinterpretSSERegValue(CmpOpVal2, OpType, RaisedBB);
return raiseSSECompareMachineInstr(MI, CmpOpVal1, CmpOpVal2, false);
}
@ -154,7 +159,7 @@ bool X86MachineInstructionRaiser::raiseSSECompareMachineInstr(
CmpOpVal2->getType()->isVectorTy() &&
"Expected operand types to be vector types");
auto Idx = ConstantInt::get(Type::getInt64Ty(Ctx), 0);
auto *Idx = ConstantInt::get(Type::getInt64Ty(Ctx), 0);
CmpOpVal1 =
ExtractElementInst::Create(CmpOpVal1, Idx, "cmp_operand_1", RaisedBB);
CmpOpVal2 =
@ -170,18 +175,18 @@ bool X86MachineInstructionRaiser::raiseSSECompareMachineInstr(
raisedValues->setEflagBoolean(EFLAGS::SF, MBBNo, false);
// Unordered or Less-than
auto ULTCmp = new FCmpInst(*RaisedBB, CmpInst::Predicate::FCMP_ULT,
CmpOpVal1, CmpOpVal2);
auto *ULTCmp = new FCmpInst(*RaisedBB, CmpInst::Predicate::FCMP_ULT,
CmpOpVal1, CmpOpVal2);
raisedValues->setEflagValue(EFLAGS::CF, MBBNo, ULTCmp);
// Unordered or Equal
auto UEQCmp = new FCmpInst(*RaisedBB, CmpInst::Predicate::FCMP_UEQ,
CmpOpVal1, CmpOpVal2);
auto *UEQCmp = new FCmpInst(*RaisedBB, CmpInst::Predicate::FCMP_UEQ,
CmpOpVal1, CmpOpVal2);
raisedValues->setEflagValue(EFLAGS::ZF, MBBNo, UEQCmp);
// Unordered
auto UNOCmp = new FCmpInst(*RaisedBB, CmpInst::Predicate::FCMP_UNO,
CmpOpVal1, CmpOpVal2);
auto *UNOCmp = new FCmpInst(*RaisedBB, CmpInst::Predicate::FCMP_UNO,
CmpOpVal1, CmpOpVal2);
raisedValues->setEflagValue(EFLAGS::PF, MBBNo, UNOCmp);
} break;
case X86::CMPSDrr_Int:
@ -230,13 +235,13 @@ bool X86MachineInstructionRaiser::raiseSSECompareMachineInstr(
"CMPNEQ");
break;
case 5: { // CMPNLTSD
auto LTInst = new FCmpInst(*RaisedBB, CmpInst::FCMP_OLT, CmpOpVal1,
CmpOpVal2, "CMPLT");
auto *LTInst = new FCmpInst(*RaisedBB, CmpInst::FCMP_OLT, CmpOpVal1,
CmpOpVal2, "CMPLT");
CmpInst = BinaryOperator::CreateNot(LTInst, "CMPNLT", RaisedBB);
} break;
case 6: { // CMPNLESD
auto LEInst = new FCmpInst(*RaisedBB, CmpInst::FCMP_OLE, CmpOpVal1,
CmpOpVal2, "CMPLE");
auto *LEInst = new FCmpInst(*RaisedBB, CmpInst::FCMP_OLE, CmpOpVal1,
CmpOpVal2, "CMPLE");
CmpInst = BinaryOperator::CreateNot(LEInst, "CMPNLE", RaisedBB);
} break;
case 7: // CMPORDSD
@ -306,23 +311,30 @@ bool X86MachineInstructionRaiser::raiseSSECompareMachineInstr(
llvm_unreachable("Unhandled pcmp instruction");
}
FixedVectorType *VecTy = FixedVectorType::get(Type::getIntNTy(Ctx, ElementSizeInBits), 128 / ElementSizeInBits);
FixedVectorType *VecTy = FixedVectorType::get(
Type::getIntNTy(Ctx, ElementSizeInBits), 128 / ElementSizeInBits);
CmpOpVal1 = new BitCastInst(CmpOpVal1, VecTy, "", RaisedBB);
CmpOpVal2 = new BitCastInst(CmpOpVal2, VecTy, "", RaisedBB);
auto IntNTy = IntegerType::getIntNTy(Ctx, VecTy->getElementType()->getPrimitiveSizeInBits());
auto *IntNTy = IntegerType::getIntNTy(
Ctx, VecTy->getElementType()->getPrimitiveSizeInBits());
Value *BitmaskVal = ConstantInt::get(IntNTy, IntNTy->getBitMask());
Value *ZeroVal = ConstantInt::get(IntNTy, 0);
// compare each pair and insert the result in the resulting vector
Value *Result = ConstantInt::get(VecTy, 0);
for (unsigned int i = 0; i < VecTy->getNumElements(); ++i) {
auto Index = ConstantInt::get(VecTy->getElementType(), i);
auto CmpSegment1 = ExtractElementInst::Create(CmpOpVal1, Index, "", RaisedBB);
auto CmpSegment2 = ExtractElementInst::Create(CmpOpVal2, Index, "", RaisedBB);
auto CmpInst = new ICmpInst(*RaisedBB, CmpInst::ICMP_EQ, CmpSegment1, CmpSegment2, "cmp_segment");
auto SelectInstr = SelectInst::Create(CmpInst, BitmaskVal, ZeroVal, "segment", RaisedBB);
Result = InsertElementInst::Create(Result, SelectInstr, Index, "", RaisedBB);
for (unsigned int Idx = 0; Idx < VecTy->getNumElements(); ++Idx) {
auto *Index = ConstantInt::get(VecTy->getElementType(), Idx);
auto *CmpSegment1 =
ExtractElementInst::Create(CmpOpVal1, Index, "", RaisedBB);
auto *CmpSegment2 =
ExtractElementInst::Create(CmpOpVal2, Index, "", RaisedBB);
auto *CmpInst = new ICmpInst(*RaisedBB, CmpInst::ICMP_EQ, CmpSegment1,
CmpSegment2, "cmp_segment");
auto *SelectInstr =
SelectInst::Create(CmpInst, BitmaskVal, ZeroVal, "segment", RaisedBB);
Result =
InsertElementInst::Create(Result, SelectInstr, Index, "", RaisedBB);
}
raisedValues->setPhysRegSSAValue(DstReg, MI.getParent()->getNumber(),
@ -435,13 +447,12 @@ bool X86MachineInstructionRaiser::raiseSSEConvertPrecisionMachineInstr(
getRegisterInfo()->getRegSizeInBits(PReg, machineRegInfo);
if (SrcTy == nullptr) {
// re-interpret value as expected source value
SrcTy =
getRaisedValues()->getSSEInstructionType(MI, SSERegSzInBits, Ctx);
SrcTy = getRaisedValues()->getSSEInstructionType(MI, SSERegSzInBits, Ctx);
}
SrcVal = getRaisedValues()->reinterpretSSERegValue(SrcVal, SrcTy, RaisedBB);
}
auto CastToInst =
auto *CastToInst =
CastInst::Create(CastInst::getCastOpcode(SrcVal, true, CastTy, true),
SrcVal, CastTy, "cvt", RaisedBB);
@ -579,7 +590,7 @@ bool X86MachineInstructionRaiser::raiseSSEConvertPrecisionFromMemMachineInstr(
Value *SrcVal = loadMemoryRefValue(MI, MemRefValue, MemoryRefOpIndex, SrcTy);
auto CastInst =
auto *CastInst =
CastInst::Create(CastInst::getCastOpcode(SrcVal, true, CastTy, true),
SrcVal, CastTy, "cvt", RaisedBB);
raisedValues->setPhysRegSSAValue(DstOp.getReg(), MI.getParent()->getNumber(),
@ -602,7 +613,7 @@ bool X86MachineInstructionRaiser::raiseSSEMoveRegToRegMachineInstr(
"Expecting exactly two operands for sse move reg-to-reg "
"instructions");
unsigned int DstPReg = MI.getOperand(DstIndex).getReg();
Register DstPReg = MI.getOperand(DstIndex).getReg();
// Get source operand value
Value *SrcValue;
@ -656,7 +667,8 @@ bool X86MachineInstructionRaiser::raiseSSEMoveRegToRegMachineInstr(
DstType = Type::getIntNTy(Ctx, DstPRegSize * 8);
}
SrcValue = getRaisedValues()->reinterpretSSERegValue(SrcValue, DstType, RaisedBB);
SrcValue =
getRaisedValues()->reinterpretSSERegValue(SrcValue, DstType, RaisedBB);
raisedValues->setPhysRegSSAValue(DstPReg, MBBNo, SrcValue);
} break;
default:

18
X86/X86MachineInstructionRaiserUtils.cpp
Просмотреть файл

@ -1032,8 +1032,8 @@ static bool isStackLocation(Value *Val) {
BinaryOperator *BinaryOp = dyn_cast<BinaryOperator>(V);
int NumUseOps = BinaryOp->getNumOperands();
assert((NumUseOps == 2) && "Unexpected operands of binary operands");
for (int i = 0; i < NumUseOps; i++) {
auto *Op = BinaryOp->getOperand(i);
for (int Idx = 0; Idx < NumUseOps; Idx++) {
auto *Op = BinaryOp->getOperand(Idx);
if (isa<CastInst>(Op)) {
CastInst *P = dyn_cast<CastInst>(Op);
V = P->getOperand(0);
@ -2280,14 +2280,14 @@ Value *X86MachineInstructionRaiser::getRegOrArgValue(unsigned PReg, int MBBNo) {
if (Pos <= (int)RaisedFunction->arg_size()) {
bool IsRegFloatingPointType = isSSE2Reg(PReg);
int ActualPos = 0; // SSE regs and int regs are scrambled
int i = 0;
int Idx = 0;
while (ActualPos < (int)RaisedFunction->arg_size() && i < Pos) {
while (ActualPos < (int)RaisedFunction->arg_size() && Idx < Pos) {
bool IsArgFloatingPointType =
RaisedFunction->getArg(i)->getType()->isFloatingPointTy();
RaisedFunction->getArg(Idx)->getType()->isFloatingPointTy();
if (IsArgFloatingPointType == IsRegFloatingPointType) {
i++;
Idx++;
}
ActualPos++;
}
@ -2490,9 +2490,9 @@ bool X86MachineInstructionRaiser::recordMachineInstrInfo(
unsigned ImplUsesCount = MCID.getNumImplicitUses();
if (ImplUsesCount > 0) {
const MCPhysReg *ImplUses = MCID.getImplicitUses();
for (unsigned i = 0; i < ImplUsesCount; i++) {
for (unsigned Idx = 0; Idx < ImplUsesCount; Idx++) {
// Get the reaching definition of the implicit use register.
if (ImplUses[i] == X86::EFLAGS) {
if (ImplUses[Idx] == X86::EFLAGS) {
for (auto FlgBit : EFlagBits) {
Value *Val = getRegOrArgValue(FlgBit, MI.getParent()->getNumber());
assert((Val != nullptr) &&
@ -2501,7 +2501,7 @@ bool X86MachineInstructionRaiser::recordMachineInstrInfo(
}
} else {
Value *Val =
getRegOrArgValue(ImplUses[i], MI.getParent()->getNumber());
getRegOrArgValue(ImplUses[Idx], MI.getParent()->getNumber());
assert((Val != nullptr) &&
"Unexpected null value of implicit defined registers");
CurCTInfo->RegValues.push_back(Val);

4
X86/X86RaisedValueTracker.cpp
Просмотреть файл

@ -72,8 +72,8 @@ X86RaisedValueTracker::X86RaisedValueTracker(
// Look at all defs - explicit and implicit.
unsigned NumDefs = MI.getNumDefs();
for (unsigned i = 0, E = MI.getNumOperands(); NumDefs && i != E; ++i) {
MachineOperand &MO = MI.getOperand(i);
for (unsigned Idx = 0, E = MI.getNumOperands(); NumDefs && Idx != E; ++Idx) {
MachineOperand &MO = MI.getOperand(Idx);
if (!MO.isReg() || !MO.isDef())
continue;

54
llvm-mctoll.cpp
Просмотреть файл

@ -65,9 +65,9 @@
#include "llvm/Support/Errc.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/InitLLVM.h"
#include "llvm/Support/GraphWriter.h"
#include "llvm/Support/Host.h"
#include "llvm/Support/InitLLVM.h"
#include "llvm/Support/ManagedStatic.h"
#include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/Signals.h"
@ -95,9 +95,7 @@ namespace {
using namespace llvm::opt; // for HelpHidden in Opts.inc
// custom Flag for opt::DriverFlag defined in the llvm/Option/Option.h
enum MyFlag {
HelpSkipped = (1 << 4)
};
enum MyFlag { HelpSkipped = (1 << 4) };
enum ID {
OPT_INVALID = 0, // This is not an option ID.
@ -180,7 +178,8 @@ namespace {
static ManagedStatic<std::vector<std::string>> RunPassNames;
struct RunPassOption {
void operator=(const std::string &Val) const {
// NOLINTNEXTLINE(misc-unconventional-assign-operator)
auto operator=(const std::string &Val) const {
if (Val.empty())
return;
SmallVector<StringRef, 8> PassNames;
@ -692,7 +691,8 @@ static bool isAFunctionSymbol(const ObjectFile *Obj, SymbolInfoTy &Symbol) {
return false;
}
#define MODULE_RAISER(TargetName) extern "C" void register##TargetName##ModuleRaiser();
#define MODULE_RAISER(TargetName) \
extern "C" void register##TargetName##ModuleRaiser();
#include "Raisers.def"
static void initializeAllModuleRaisers() {
@ -709,8 +709,8 @@ static void disassembleObject(const ObjectFile *Obj, bool InlineRelocs) {
// Package up features to be passed to target/subtarget
SubtargetFeatures Features = Obj->getFeatures();
if (MAttrs.size()) {
for (unsigned i = 0; i != MAttrs.size(); ++i)
Features.AddFeature(MAttrs[i]);
for (unsigned Idx = 0; Idx != MAttrs.size(); ++Idx)
Features.AddFeature(MAttrs[Idx]);
}
std::unique_ptr<const MCRegisterInfo> MRI(
@ -778,9 +778,8 @@ static void disassembleObject(const ObjectFile *Obj, bool InlineRelocs) {
ModuleRaiser *MR = mctoll::getModuleRaiser(Target.get());
assert((MR != nullptr) && "Failed to build module raiser");
// Set data of module raiser
MR->setModuleRaiserInfo(&M, Target.get(),
&MachineModuleInfo->getMMI(), MIA.get(),
MII.get(), Obj, DisAsm.get());
MR->setModuleRaiserInfo(&M, Target.get(), &MachineModuleInfo->getMMI(),
MIA.get(), MII.get(), Obj, DisAsm.get());
// Collect dynamic relocations.
MR->collectDynamicRelocations();
@ -1085,8 +1084,7 @@ static void disassembleObject(const ObjectFile *Obj, bool InlineRelocs) {
BranchTargetSet.clear();
// Create a new MachineFunction raiser
CurMFRaiser =
MR->CreateAndAddMachineFunctionRaiser(
Func, MR, Start, End);
MR->CreateAndAddMachineFunctionRaiser(Func, MR, Start, End);
LLVM_DEBUG(dbgs() << "\nFunction " << Symbols[SI].Name << ":\n");
} else {
// Continue using to the most recent MachineFunctionRaiser
@ -1149,8 +1147,9 @@ static void disassembleObject(const ObjectFile *Obj, bool InlineRelocs) {
Bytes.data() + Index);
Data = *Word;
} else {
const auto *const Word = reinterpret_cast<const support::ubig32_t *>(
Bytes.data() + Index);
const auto *const Word =
reinterpret_cast<const support::ubig32_t *>(Bytes.data() +
Index);
Data = *Word;
}
InstRaiser->addMCInstOrData(Index, Data);
@ -1504,7 +1503,8 @@ commaSeparatedValues(const llvm::opt::InputArgList &InputArgs, int ID) {
static void parseOptions(const llvm::opt::InputArgList &InputArgs) {
llvm::DebugFlag = InputArgs.hasArg(OPT_debug);
Disassemble = InputArgs.hasArg(OPT_raise);
FilterConfigFileName = InputArgs.getLastArgValue(OPT_filter_functions_file_EQ).str();
FilterConfigFileName =
InputArgs.getLastArgValue(OPT_filter_functions_file_EQ).str();
MCPU = InputArgs.getLastArgValue(OPT_mcpu_EQ).str();
MAttrs = commaSeparatedValues(InputArgs, OPT_mattr_EQ);
FilterSections = InputArgs.getAllArgValues(OPT_section_EQ);
@ -1521,7 +1521,8 @@ static void parseOptions(const llvm::opt::InputArgList &InputArgs) {
reportCmdLineError("no input file");
IncludeFileNames = InputArgs.getAllArgValues(OPT_include_file_EQ);
std::string IncludeFileNames2 = InputArgs.getLastArgValue(OPT_include_files_EQ).str();
std::string IncludeFileNames2 =
InputArgs.getLastArgValue(OPT_include_files_EQ).str();
if (!IncludeFileNames2.empty()) {
SmallVector<StringRef, 8> FNames;
StringRef(IncludeFileNames2).split(FNames, ',', -1, false);
@ -1531,10 +1532,10 @@ static void parseOptions(const llvm::opt::InputArgList &InputArgs) {
if (const opt::Arg *A = InputArgs.getLastArg(OPT_output_format_EQ)) {
OutputFormat = StringSwitch<OutputFormatTy>(A->getValue())
.Case("ll", OF_LL)
.Case("BC", OF_BC)
.Case("Null", OF_Null)
.Default(OF_Unknown);
.Case("ll", OF_LL)
.Case("BC", OF_BC)
.Case("Null", OF_Null)
.Default(OF_Unknown);
if (OutputFormat == OF_Unknown)
invalidArgValue(A);
}
@ -1546,12 +1547,10 @@ int main(int argc, char **argv) {
// parse command line
BumpPtrAllocator A;
StringSaver Saver(A);
MctollOptTable Tbl(" [options] <input object files>",
"MC to LLVM IR raiser");
MctollOptTable Tbl(" [options] <input object files>", "MC to LLVM IR raiser");
ToolName = argv[0];
opt::InputArgList Args =
Tbl.parseArgs(argc, argv, OPT_UNKNOWN, Saver,
[&](StringRef Msg) {
Tbl.parseArgs(argc, argv, OPT_UNKNOWN, Saver, [&](StringRef Msg) {
error(Msg);
exit(1);
});
@ -1577,7 +1576,7 @@ int main(int argc, char **argv) {
return 0;
}
parseOptions(Args);
parseOptions(Args);
// Set appropriate bug report message
llvm::setBugReportMsg(
@ -1608,8 +1607,7 @@ int main(int argc, char **argv) {
if (!IncludeFNames.empty()) {
if (!IncludedFileInfo::getExternalFunctionPrototype(IncludeFNames,
TargetName,
SysRoot)) {
TargetName, SysRoot)) {
dbgs() << "Unable to read external function prototype. Ignoring\n";
}
}