QemuQ35Pkg/PlatformPei: Drop S3 and Lock Box support
Removes platform initialization logic for S3 and the lock box. Notably, the number of MMRAM regions is reduced from two to one since the first MMRAM range was previously a 4KB page used to hold S3 resume structures. The amount of ACPI NVS reservation is reduced substantially since areas like the following do not need to be preserved for S3 resume: - CPU AP stack buffers - Temp RAM stack and heap - GUIDed section extraction handlers - Reset vector initial page tables The lock box storage buffer is also not allocated at all. Previously, it was allocated as boot services data (not ACPI NVS) since S3 was never enabled. In any case, that space is no longer allocated. Asserts are added in places through key control flow to alert a developer if S3 is detected as enabled when it should not be. Signed-off-by: Michael Kubacki <Michael.kubacki@microsoft.com>
This commit is contained in:
Michael Kubacki
Родитель
4044593f31
Коммит
d21b07fa30
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@ -25,19 +25,15 @@ PeiFvInitialization (
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VOID
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)
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{
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BOOLEAN SecureS3Needed;
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DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
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//
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// Create a memory allocation HOB for the PEI FV.
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//
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// Allocate as ACPI NVS is S3 is supported
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//
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BuildMemoryAllocationHob (
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PcdGet32 (PcdOvmfPeiMemFvBase),
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PcdGet32 (PcdOvmfPeiMemFvSize),
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mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
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EfiBootServicesData
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);
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//
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@ -45,38 +41,15 @@ PeiFvInitialization (
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//
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BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSize));
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SecureS3Needed = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire);
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//
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// Create a memory allocation HOB for the DXE FV.
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//
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// If "secure" S3 is needed, then SEC will decompress both PEI and DXE
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// firmware volumes at S3 resume too, hence we need to keep away the OS from
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// DXEFV as well. Otherwise we only need to keep away DXE itself from the
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// DXEFV area.
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//
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BuildMemoryAllocationHob (
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PcdGet32 (PcdOvmfDxeMemFvBase),
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PcdGet32 (PcdOvmfDxeMemFvSize),
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SecureS3Needed ? EfiACPIMemoryNVS : EfiBootServicesData
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EfiBootServicesData
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);
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//
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// Additionally, said decompression will use temporary memory above the end
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// of DXEFV, so let's keep away the OS from there too.
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//
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if (SecureS3Needed) {
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UINT32 DxeMemFvEnd;
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DxeMemFvEnd = PcdGet32 (PcdOvmfDxeMemFvBase) +
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PcdGet32 (PcdOvmfDxeMemFvSize);
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BuildMemoryAllocationHob (
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DxeMemFvEnd,
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PcdGet32 (PcdOvmfDecompressionScratchEnd) - DxeMemFvEnd,
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EfiACPIMemoryNVS
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);
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}
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//
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// Let PEI know about the DXE FV so it can find the DXE Core
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//
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@ -2,12 +2,10 @@
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Memory Detection for Virtual Machines.
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Copyright (c) 2006 - 2024, Intel Corporation. All rights reserved.<BR>
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Copyright (c) Microsoft Corporation
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Module Name:
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MemDetect.c
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**/
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//
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@ -43,9 +41,6 @@ Module Name:
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UINT8 mPhysMemAddressWidth;
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STATIC UINT32 mS3AcpiReservedMemoryBase;
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STATIC UINT32 mS3AcpiReservedMemorySize;
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STATIC UINT16 mQ35TsegMbytes;
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BOOLEAN mQ35SmramAtDefaultSmbase;
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@ -70,7 +65,7 @@ Q35TsegMbytesInitialization (
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//
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// On a QEMU machine type that does not offer an extended TSEG, the initial
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// write overwrites whatever value a malicious guest OS may have placed in
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// the (unimplemented) register, before entering S3 or rebooting.
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// the (unimplemented) register before rebooting.
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// Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.
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//
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// On a QEMU machine type that offers an extended TSEG, the initial write
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@ -673,28 +668,14 @@ PublishPeiMemory (
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LowerMemorySize -= mQ35TsegMbytes * SIZE_1MB;
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}
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//
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// If S3 is supported, then the S3 permanent PEI memory is placed next,
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// downwards. Its size is primarily dictated by CpuMpPei. The formula below
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// is an approximation.
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//
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if (mS3Supported) {
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mS3AcpiReservedMemorySize = SIZE_512KB +
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mMaxCpuCount *
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PcdGet32 (PcdCpuApStackSize);
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mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;
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LowerMemorySize = mS3AcpiReservedMemoryBase;
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}
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// S3 is not supported
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ASSERT (mBootMode != BOOT_ON_S3_RESUME);
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if (mBootMode == BOOT_ON_S3_RESUME) {
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MemoryBase = mS3AcpiReservedMemoryBase;
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MemorySize = mS3AcpiReservedMemorySize;
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} else {
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PeiMemoryCap = GetPeiMemoryCap ();
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DEBUG ((
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DEBUG_INFO,
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"%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
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__FUNCTION__,
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__func__,
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mPhysMemAddressWidth,
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PeiMemoryCap >> 10
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));
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@ -702,27 +683,16 @@ PublishPeiMemory (
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//
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// Determine the range of memory to use during PEI
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//
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// Technically we could lay the permanent PEI RAM over SEC's temporary
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// decompression and scratch buffer even if "secure S3" is needed, since
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// their lifetimes don't overlap. However, PeiFvInitialization() will cover
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// RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory
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// allocation HOB, and other allocations served from the permanent PEI RAM
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// shouldn't overlap with that HOB.
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//
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MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?
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PcdGet32 (PcdOvmfDecompressionScratchEnd) :
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PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
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MemoryBase = PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
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MemorySize = LowerMemorySize - MemoryBase;
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if (MemorySize > PeiMemoryCap) {
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MemoryBase = LowerMemorySize - PeiMemoryCap;
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MemorySize = PeiMemoryCap;
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}
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}
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//
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// MEMFD_BASE_ADDRESS separates the SMRAM at the default SMBASE from the
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// normal boot permanent PEI RAM. Regarding the S3 boot path, the S3
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// permanent PEI RAM is located even higher.
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// normal boot permanent PEI RAM.
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//
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if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {
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ASSERT (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE <= MemoryBase);
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@ -758,7 +728,7 @@ CreateSmmSmramMemoryHob (
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EFI_PEI_HOB_POINTERS Hob;
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EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
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SmramRanges = 2;
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SmramRanges = 1;
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BufferSize = sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK) + (SmramRanges - 1) * sizeof (EFI_SMRAM_DESCRIPTOR);
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Hob.Raw = BuildGuidHob (
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@ -771,21 +741,12 @@ CreateSmmSmramMemoryHob (
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SmramHobDescriptorBlock->NumberOfSmmReservedRegions = SmramRanges;
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//
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// 1. Create first SMRAM descriptor, which contains data structures used in S3 resume.
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// One page is enough for the data structure
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// Create SMRAM descriptor, which is free and will be used by the SMM foundation.
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//
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SmramHobDescriptorBlock->Descriptor[0].PhysicalStart = StartAddress;
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SmramHobDescriptorBlock->Descriptor[0].CpuStart = StartAddress;
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SmramHobDescriptorBlock->Descriptor[0].PhysicalSize = EFI_PAGE_SIZE;
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SmramHobDescriptorBlock->Descriptor[0].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE | EFI_ALLOCATED;
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//
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// 2. Create second SMRAM descriptor, which is free and will be used by SMM foundation.
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//
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SmramHobDescriptorBlock->Descriptor[1].PhysicalStart = SmramHobDescriptorBlock->Descriptor[0].PhysicalStart + EFI_PAGE_SIZE;
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SmramHobDescriptorBlock->Descriptor[1].CpuStart = SmramHobDescriptorBlock->Descriptor[0].CpuStart + EFI_PAGE_SIZE;
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SmramHobDescriptorBlock->Descriptor[1].PhysicalSize = Size - EFI_PAGE_SIZE;
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SmramHobDescriptorBlock->Descriptor[1].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE;
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SmramHobDescriptorBlock->Descriptor[0].PhysicalSize = Size;
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SmramHobDescriptorBlock->Descriptor[0].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE;
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}
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STATIC
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@ -824,8 +785,10 @@ QemuInitializeRam (
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VOID
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)
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{
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UINT32 TsegSize;
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UINT64 LowerMemorySize;
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UINT64 UpperMemorySize;
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EFI_PHYSICAL_ADDRESS TsegBase;
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MTRR_SETTINGS MtrrSettings;
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EFI_STATUS Status;
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@ -836,38 +799,12 @@ QemuInitializeRam (
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//
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LowerMemorySize = GetSystemMemorySizeBelow4gb ();
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if (mBootMode == BOOT_ON_S3_RESUME) {
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//
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// Create the following memory HOB as an exception on the S3 boot path.
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//
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// Normally we'd create memory HOBs only on the normal boot path. However,
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// CpuMpPei specifically needs such a low-memory HOB on the S3 path as
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// well, for "borrowing" a subset of it temporarily, for the AP startup
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// vector.
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//
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// CpuMpPei saves the original contents of the borrowed area in permanent
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// PEI RAM, in a backup buffer allocated with the normal PEI services.
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// CpuMpPei restores the original contents ("returns" the borrowed area) at
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// End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before
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// transferring control to the OS's wakeup vector in the FACS.
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//
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// We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to
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// restore the original contents. Furthermore, we expect all such PEIMs
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// (CpuMpPei included) to claim the borrowed areas by producing memory
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// allocation HOBs, and to honor preexistent memory allocation HOBs when
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// looking for an area to borrow.
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//
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QemuInitializeRamBelow1gb ();
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} else {
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//
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// Create memory HOBs
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//
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QemuInitializeRamBelow1gb ();
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if (FeaturePcdGet (PcdSmmSmramRequire)) {
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UINT32 TsegSize;
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EFI_PHYSICAL_ADDRESS TsegBase;
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TsegSize = mQ35TsegMbytes * SIZE_1MB;
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TsegBase = LowerMemorySize - TsegSize;
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AddMemoryRangeHob (BASE_1MB, TsegBase);
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@ -896,7 +833,6 @@ QemuInitializeRam (
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AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);
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}
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}
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}
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//
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// We'd like to keep the following ranges uncached:
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@ -959,109 +895,15 @@ InitializeRamRegions (
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VOID
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)
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{
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QemuInitializeRam ();
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SevInitializeRam ();
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if (mS3Supported && (mBootMode != BOOT_ON_S3_RESUME)) {
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//
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// This is the memory range that will be used for PEI on S3 resume
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//
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BuildMemoryAllocationHob (
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mS3AcpiReservedMemoryBase,
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mS3AcpiReservedMemorySize,
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EfiACPIMemoryNVS
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);
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//
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// Cover the initial RAM area used as stack and temporary PEI heap.
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//
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// This is reserved as ACPI NVS so it can be used on S3 resume.
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//
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BuildMemoryAllocationHob (
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PcdGet32 (PcdSecPeiTemporaryRamBase),
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PcdGet32 (PcdSecPeiTemporaryRamSize),
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EfiACPIMemoryNVS
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);
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//
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// SEC stores its table of GUIDed section handlers here.
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//
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BuildMemoryAllocationHob (
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PcdGet64 (PcdGuidedExtractHandlerTableAddress),
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PcdGet32 (PcdGuidedExtractHandlerTableSize),
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EfiACPIMemoryNVS
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);
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#ifdef MDE_CPU_X64
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//
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// Reserve the initial page tables built by the reset vector code.
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//
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// Since this memory range will be used by the Reset Vector on S3
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// resume, it must be reserved as ACPI NVS.
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//
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BuildMemoryAllocationHob (
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(EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecPageTablesBase),
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(UINT64)(UINTN)PcdGet32 (PcdOvmfSecPageTablesSize),
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EfiACPIMemoryNVS
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);
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if (MemEncryptSevEsIsEnabled ()) {
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//
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// If SEV-ES is enabled, reserve the GHCB-related memory area. This
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// includes the extra page table used to break down the 2MB page
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// mapping into 4KB page entries where the GHCB resides and the
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// GHCB area itself.
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//
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// Since this memory range will be used by the Reset Vector on S3
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// resume, it must be reserved as ACPI NVS.
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//
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BuildMemoryAllocationHob (
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(EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableBase),
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(UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableSize),
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EfiACPIMemoryNVS
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);
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BuildMemoryAllocationHob (
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(EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBase),
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(UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbSize),
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EfiACPIMemoryNVS
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);
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BuildMemoryAllocationHob (
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(EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupBase),
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(UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupSize),
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EfiACPIMemoryNVS
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);
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}
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#endif
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}
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if (mBootMode != BOOT_ON_S3_RESUME) {
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if (!FeaturePcdGet (PcdSmmSmramRequire)) {
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//
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// Reserve the lock box storage area
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//
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// Since this memory range will be used on S3 resume, it must be
|
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// reserved as ACPI NVS.
|
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//
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// If S3 is unsupported, then various drivers might still write to the
|
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// LockBox area. We ought to prevent DXE from serving allocation requests
|
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// such that they would overlap the LockBox storage.
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//
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ZeroMem (
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(VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),
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(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize)
|
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);
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BuildMemoryAllocationHob (
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(EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),
|
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(UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize),
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mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
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);
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}
|
||||
|
||||
if (FeaturePcdGet (PcdSmmSmramRequire)) {
|
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UINT32 TsegSize;
|
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|
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QemuInitializeRam ();
|
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SevInitializeRam ();
|
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|
||||
// S3 is not supported.
|
||||
ASSERT (mBootMode != BOOT_ON_S3_RESUME);
|
||||
|
||||
if (FeaturePcdGet (PcdSmmSmramRequire)) {
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//
|
||||
// Make sure the TSEG area that we reported as a reserved memory resource
|
||||
// cannot be used for reserved memory allocations.
|
||||
|
|
@ -1090,20 +932,20 @@ InitializeRamRegions (
|
|||
//
|
||||
// Reserve the work area.
|
||||
//
|
||||
// Since this memory range will be used by the Reset Vector on S3
|
||||
// resume, it must be reserved as ACPI NVS.
|
||||
// This range was originally used by the Reset Vector on S3
|
||||
// resume and in that case, it would be allocated as ACPI NVS.
|
||||
//
|
||||
// If S3 is unsupported, then various drivers might still write to the
|
||||
// S3 is no longer supported. However, drivers might still write to the
|
||||
// work area. We ought to prevent DXE from serving allocation requests
|
||||
// such that they would overlap the work area.
|
||||
// such that they would overlap the work area. The area is also allocated
|
||||
// as boot services data to prevent impact on OS mapped memory.
|
||||
//
|
||||
BuildMemoryAllocationHob (
|
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(EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase),
|
||||
(UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize),
|
||||
mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
|
||||
EfiBootServicesData
|
||||
);
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
|
||||
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
|
||||
Copyright (c) Microsoft Corporation
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
|
|
@ -27,7 +28,6 @@
|
|||
#include <Library/PeimEntryPoint.h>
|
||||
#include <Library/PeiServicesLib.h>
|
||||
#include <Library/QemuFwCfgLib.h>
|
||||
#include <Library/QemuFwCfgS3Lib.h>
|
||||
#include <Library/QemuFwCfgSimpleParserLib.h>
|
||||
#include <Library/ResourcePublicationLib.h>
|
||||
#include <Ppi/MasterBootMode.h>
|
||||
|
|
@ -55,8 +55,6 @@ UINT16 mHostBridgeDevId;
|
|||
|
||||
EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
|
||||
|
||||
BOOLEAN mS3Supported = FALSE;
|
||||
|
||||
UINT32 mMaxCpuCount;
|
||||
|
||||
VOID
|
||||
|
|
@ -416,8 +414,7 @@ MiscInitialization (
|
|||
|
||||
//
|
||||
// Build the CPU HOB with guest RAM size dependent address width and 16-bits
|
||||
// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
|
||||
// S3 resume as well, so we build it unconditionally.)
|
||||
// of IO space.
|
||||
//
|
||||
BuildCpuHob (mPhysMemAddressWidth, 16);
|
||||
|
||||
|
|
@ -516,7 +513,9 @@ BootModeInitialization (
|
|||
EFI_STATUS Status;
|
||||
|
||||
if (CmosRead8 (0xF) == 0xFE) {
|
||||
mBootMode = BOOT_ON_S3_RESUME;
|
||||
// S3 is not supported. Do not modify the boot mode.
|
||||
DEBUG ((DEBUG_ERROR, "[%a] S3 is enabled in CMOS, but not supported!\n", __func__));
|
||||
ASSERT (FALSE);
|
||||
}
|
||||
|
||||
CmosWrite8 (0xF, 0x00);
|
||||
|
|
@ -578,35 +577,6 @@ DebugDumpCmos (
|
|||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
S3Verification (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
#if defined (MDE_CPU_X64)
|
||||
if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
|
||||
DEBUG ((
|
||||
DEBUG_ERROR,
|
||||
"%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",
|
||||
__FUNCTION__
|
||||
));
|
||||
DEBUG ((
|
||||
DEBUG_ERROR,
|
||||
"%a: Please disable S3 on the QEMU command line (see the README),\n",
|
||||
__FUNCTION__
|
||||
));
|
||||
DEBUG ((
|
||||
DEBUG_ERROR,
|
||||
"%a: or build OVMF with \"QemuQ35PkgIa32X64.dsc\".\n",
|
||||
__FUNCTION__
|
||||
));
|
||||
ASSERT (FALSE);
|
||||
CpuDeadLoop ();
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
Q35BoardVerification (
|
||||
VOID
|
||||
|
|
@ -818,7 +788,6 @@ InitializePlatform (
|
|||
IN CONST EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
// MU_CHANGE START
|
||||
DXE_MEMORY_PROTECTION_SETTINGS DxeSettings;
|
||||
MM_MEMORY_PROTECTION_SETTINGS MmSettings;
|
||||
|
|
@ -852,14 +821,6 @@ InitializePlatform (
|
|||
|
||||
DebugDumpCmos ();
|
||||
|
||||
if (QemuFwCfgS3Enabled ()) {
|
||||
DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));
|
||||
mS3Supported = TRUE;
|
||||
Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
}
|
||||
|
||||
S3Verification ();
|
||||
BootModeInitialization ();
|
||||
AddressWidthInitialization ();
|
||||
|
||||
|
|
@ -882,7 +843,6 @@ InitializePlatform (
|
|||
|
||||
InitializeRamRegions ();
|
||||
|
||||
if (mBootMode != BOOT_ON_S3_RESUME) {
|
||||
if (!FeaturePcdGet (PcdSmmSmramRequire)) {
|
||||
ReserveEmuVariableNvStore ();
|
||||
}
|
||||
|
|
@ -891,7 +851,6 @@ InitializePlatform (
|
|||
MemTypeInfoInitialization ();
|
||||
MemMapInitialization ();
|
||||
NoexecDxeInitialization ();
|
||||
}
|
||||
|
||||
InstallClearCacheCallback ();
|
||||
AmdSevInitialize ();
|
||||
|
|
|
|||
|
|
@ -114,8 +114,6 @@ SevInitializeRam (
|
|||
VOID
|
||||
);
|
||||
|
||||
extern BOOLEAN mS3Supported;
|
||||
|
||||
extern UINT8 mPhysMemAddressWidth;
|
||||
|
||||
extern UINT32 mMaxCpuCount;
|
||||
|
|
|
|||
|
|
@ -63,7 +63,6 @@
|
|||
PeiServicesTablePointerLib
|
||||
PeimEntryPoint
|
||||
QemuFwCfgLib
|
||||
QemuFwCfgS3Lib
|
||||
QemuFwCfgSimpleParserLib
|
||||
MtrrLib
|
||||
MemEncryptSevLib
|
||||
|
|
@ -83,8 +82,6 @@
|
|||
gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize
|
||||
gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSecGhcbBase
|
||||
gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSecGhcbSize
|
||||
gQemuPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase
|
||||
gQemuPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize
|
||||
gUefiQemuQ35PkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize
|
||||
gQemuPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
|
||||
gUefiQemuQ35PkgTokenSpaceGuid.PcdPciIoBase
|
||||
|
|
@ -104,7 +101,6 @@
|
|||
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable
|
||||
# gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack MU_CHANGE
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize
|
||||
|
|
|
|||
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