onnxruntime-tvm/verilog/verilog.mk

VPI_CFLAGS=`iverilog-vpi --cflags`
VPI_LDFLAGS=`iverilog-vpi --ldflags`

VER_SRCS = $(wildcard verilog/*.v)

VER_LIBS=lib/tvm_vpi.vpi

lib/tvm_vpi.vpi: verilog/tvm_vpi.cc verilog/tvm_vpi.h
	@mkdir -p $(@D)
	$(CXX) $(VPI_CFLAGS) $(CFLAGS) -o $@ $(filter %.cc, $^) $(LDFLAGS) $(VPI_LDFLAGS)
[VERILOG] Basic Verilog Testflow (#70) * [VERILOG] Basic Verilog Testflow * fix build * fix the comment * fix lint in verilog 2017-03-14 07:28:03 +03:00			VPI_CFLAGS=`iverilog-vpi --cflags`
[CODEGEN] Refactor common codegen, Verilog Codegen (#74) * [CODEGEN] Refactor common codegen, Verilog Codegen * fix make * fix mk * update enable signal * change function name to at neg edge * Move test to correct place 2017-03-26 04:26:28 +03:00			VPI_LDFLAGS=`iverilog-vpi --ldflags`
[VERILOG] Basic Verilog Testflow (#70) * [VERILOG] Basic Verilog Testflow * fix build * fix the comment * fix lint in verilog 2017-03-14 07:28:03 +03:00
			`VER_SRCS = $(wildcard verilog/*.v)`

			`VER_LIBS=lib/tvm_vpi.vpi`

			`lib/tvm_vpi.vpi: verilog/tvm_vpi.cc verilog/tvm_vpi.h`
			`@mkdir -p $(@D)`
[CODEGEN] Refactor common codegen, Verilog Codegen (#74) * [CODEGEN] Refactor common codegen, Verilog Codegen * fix make * fix mk * update enable signal * change function name to at neg edge * Move test to correct place 2017-03-26 04:26:28 +03:00			`$(CXX) $(VPI_CFLAGS) $(CFLAGS) -o $@ $(filter %.cc, $^) $(LDFLAGS) $(VPI_LDFLAGS)`