Граф коммитов

9 Коммитов

Автор SHA1 Сообщение Дата
Tianqi Chen 581509ab4b [PASS] copy intrin (#536)
* [PASS] copy intrin

* update comment thanks to derisavi
2017-10-11 10:07:22 -07:00
Tianqi Chen 65038950b4 [ARITH] Improve detect linear equation (#529)
* [ARITH] Improve detect linear equation

* fix doc
2017-10-10 09:48:36 -07:00
Tianqi Chen eefcfe1985 [PASS] Refactor thread storage sync to a common visitor (#296)
* [PASS] Refactor thread storage sync to a common visitor

* Fix the sync scope check behavior
2017-08-03 13:21:49 -07:00
Tianqi Chen 6bc0ae12ca [ARITH] Refactor intset eval with functor (#295) 2017-08-02 23:28:28 -07:00
Jian Weng 01cbc61a89 [API] Prefetch schedule supported (#258)
* prefetch interface added

* prefetch python comments modified. prefetch info data structure maintained.

* start injecting prefetches. first step (domain touch) implemented.

* domain touch tested.

* Prefetch ir_mutator and ir_visitor dispatch registered.

* modify domain touched from passing a func_ref to passing a tensor

* modify domain touched from passing a func_ref to passing a tensor

* modify Tensor copy to Tensor ref

* temp commit for rebase

* debug info removed, typo fixed, ready to rebase

* prefetch flatten test add!

* roll back builtin functions to side effect functions

* lint error fixed!

* add cache line size to storage flatten argument

* forgot modifications add

* change code style to dmlc-like; get rid of can_prove, use manually compute instead

* python lint error fixed

* modify instrinsic name to pass tests

* [TEST] get rid of str(), replace them by accessing attributes

* change map to list comprehension

* redundant numpy import removed
2017-07-18 09:40:54 -07:00
Tianqi Chen 825566ccff [SCHEDULE] tensorize (#223) 2017-07-06 13:56:39 -07:00
Tianqi Chen 00506a62e7 [IR] Add body to AssertStmt (#220)
* [IR] Add body to AssertStmt

* fix lint
2017-07-05 17:55:34 -07:00
Tianqi Chen df6fcc509c [CODEGEN] Refactor common codegen, Verilog Codegen (#74)
* [CODEGEN] Refactor common codegen, Verilog Codegen

* fix make

* fix mk

* update enable signal

* change function name to at neg edge

* Move test to correct place
2017-03-25 18:26:28 -07:00
Tianqi Chen 3fb8579695 [REFACTOR] Add Types to IterVar, Isolate Operator (#62)
* [IterVar/REFACTOR] Add types to IterVar

* [ARITH/REFACTOR] Move IntSet to include

* [REFACTOR/OP] Move Op detail to seperate folder.

* fix test
2017-03-05 12:45:02 -08:00