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* [VTA][Chisel] add scalafmt and format existing scala codebase * change column width to 100 * add scalafmt conf file as a valid file type * add asf header to scalafmt conf file and rerun formatter |
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| README.md | ||
README.md
VTA TSIM Installation
TSIM is a cycle-accurate hardware simulation environment that can be invoked and managed directly from TVM. It aims to enable cycle accurate simulation of deep learning accelerators including VTA. This simulation environment can be used in both OSX and Linux. There are two dependencies required to make TSIM works: Verilator and sbt for accelerators designed in Chisel3.
OSX Dependencies
Install sbt and verilator using Homebrew.
brew install verilator sbt
Linux Dependencies
Add sbt to package manager (Ubuntu).
echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list
sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823
sudo apt-get update
Install sbt and verilator.
sudo apt install verilator sbt
Verilator version check
verilator --version
the supported version of Verilator should be at least 4.012, if homebrew (OSX) or package-manager (Linux) does not support that version, please install Verilator 4.012 or later from binary or source base on following instruction of Verilator wiki.
https://www.veripool.org/projects/verilator/wiki/Installing
Setup in TVM
- Install
verilatorandsbtas described above - Get tvm
git clone https://github.com/dmlc/tvm.git - Build tvm
How to run VTA TSIM examples
There are two sample VTA accelerators, add-a-constant, designed in Chisel3 and Verilog to show how TSIM works. The default target language for these two implementations is Verilog. The following instructions show how to run both of them:
-
Test Verilog backend
- Go to
<tvm-root>/vta/apps/tsim_example - Run
make
- Go to
-
Test Chisel3 backend
- Go to
<tvm-root>/vta/apps/tsim_example - Run
make run_chisel
- Go to
-
Some pointers
- Verilog and Chisel3 tests in
<tvm-root>/vta/apps/tsim_example/tests/python - Verilog accelerator backend
<tvm-root>/vta/apps/tsim_example/hardware/verilog - Chisel3 accelerator backend
<tvm-root>/vta/apps/tsim_example/hardware/chisel - Software C++ driver (backend) that handles the accelerator
<tvm-root>/vta/apps/tsim_example/src/driver.cc - Software Python driver (frontend) that handles the accelerator
<tvm-root>/vta/apps/tsim_example/python/accel
- Verilog and Chisel3 tests in