microsoft
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onnxruntime-tvm
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onnxruntime-tvm/verilog
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Tianqi Chen f364d563c2 [CONTRIB/BLAS] Add CBLAS Example to contrib (#120) 
* [CONTRIB/BLAS] Add CBLAS Example to contrib

* Update makefile
 		2017-05-05 10:55:34 -07:00
..
README.md [CONTRIB/BLAS] Add CBLAS Example to contrib (#120) 2017-05-05 10:55:34 -07:00
example_counter.v [VERILOG] Basic Verilog Testflow (#70) 2017-03-13 21:28:03 -07:00
tvm_buffer.v [VERILOG] Generalize Buffer and Tests (#76) 2017-03-26 18:50:36 -07:00
tvm_marcos.v [CODEGEN] Refactor common codegen, Verilog Codegen (#74) 2017-03-25 18:26:28 -07:00
tvm_vpi.cc [CODEGEN] Refactor common codegen, Verilog Codegen (#74) 2017-03-25 18:26:28 -07:00
tvm_vpi.h [VERILOG] VPI Mem Interface/ VPI MMap (#73) 2017-03-17 13:04:17 -07:00
tvm_vpi_mem_interface.v [VERILOG] VPI Mem Interface/ VPI MMap (#73) 2017-03-17 13:04:17 -07:00
tvm_vpi_mmap.v [VERILOG] VPI Mem Interface/ VPI MMap (#73) 2017-03-17 13:04:17 -07:00
verilog.mk [CODEGEN] Refactor common codegen, Verilog Codegen (#74) 2017-03-25 18:26:28 -07:00

README.md

Verilog Code Guidline

The verilog backend is still at early alpha and not yet ready to use.

  • Use my_port_name for variable naming.
  • Always use suffix to indicate certain usage.

Common Suffix

  • clk: clock
  • rst: reset
  • in: input port
  • out: output port
  • en: enable signal
  • addr: address port
  • valid: valid signal in FIFO handshake.
  • ready: ready signal in FIFO handshake.