df6fcc509c
* [CODEGEN] Refactor common codegen, Verilog Codegen * fix make * fix mk * update enable signal * change function name to at neg edge * Move test to correct place |
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HalideIR@ce80d58741 | ||
cmake | ||
dlpack@9f433c5ecf | ||
dmlc-core@2b75a0ce6f | ||
docs | ||
include/tvm | ||
make | ||
python/tvm | ||
src | ||
tests | ||
verilog | ||
.gitignore | ||
.gitmodules | ||
.travis.yml | ||
CMakeLists.txt | ||
LICENSE | ||
Makefile | ||
README.md |
README.md
TVM
hack for fun
Run the tests, set the bashrc
export PYTHONPATH=${PYTHONPATH}:/path/to/tvm/python
Write and run tests via
nosetests tests/python