18 строки
343 B
Verilog
18 строки
343 B
Verilog
// a counter that counts up
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// Use as example of testcaase
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module counter(clk, rst, out);
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input clk;
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input rst;
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output [3:0] out;
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reg [3:0] counter;
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assign out = counter;
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always @(posedge clk) begin
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if (rst) begin
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counter <= 0;
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end else begin
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counter <= counter +1;
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end
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end
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endmodule
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