44 строки
1.7 KiB
Verilog
44 строки
1.7 KiB
Verilog
// Memory controller to access TVM VPI simulated RAM.
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//
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// You only see the wires and registers but no logics here.
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// The real computation is implemented via TVM VPI
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//
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// Usage: create and pass instance to additional arguments of $tvm_session.
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// Then it will be automatically hook up the RAM logic.
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//
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module tvm_vpi_mem_interface
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#(
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parameter READ_WIDTH = 8,
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parameter WRITE_WIDTH = 8,
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parameter ADDR_WIDTH = 32,
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parameter SIZE_WIDTH = 32
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)
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(
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input clk,
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input rst,
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// Read Ports
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input read_en, // Read buffer enable
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output [READ_WIDTH-1:0] read_data_out, // The data port for read
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output read_data_valid, // Read is valid.
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// Write ports
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input write_en, // Write buffer enable
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input [WRITE_WIDTH-1:0] write_data_in, // Input data to write.
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output write_data_ready, // There are still pending write
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// Status port
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// Control signal ports to issue tasks
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input host_read_req, // Read request
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input [ADDR_WIDTH-1:0] host_read_addr, // The address to issue a read task
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input [SIZE_WIDTH-1:0] host_read_size, // The size of a read
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input host_write_req, // Write request.
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input [ADDR_WIDTH-1:0] host_write_addr, // The write address
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input [SIZE_WIDTH-1:0] host_write_size // The write size
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);
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reg [READ_WIDTH-1:0] reg_read_data;
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reg reg_read_valid;
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reg reg_write_ready;
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// The wires up.
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assign read_data_out = reg_read_data;
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assign read_data_valid = reg_read_valid;
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assign write_data_ready = reg_write_ready;
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endmodule
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