44 строки
1.4 KiB
Verilog
44 строки
1.4 KiB
Verilog
// TVM mmap maps virtual DRAM into interface of SRAM.
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// This allows create testcases that directly access DRAM.
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// Read only memory map, one cycle read.
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// Usage: create and pass instance to additional arguments of $tvm_session.
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module tvm_vpi_read_mmap
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#(
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parameter DATA_WIDTH = 8,
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parameter ADDR_WIDTH = 8,
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parameter BASE_ADDR_WIDTH = 32
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)
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(
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input clk,
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input rst,
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// Read Ports
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input [ADDR_WIDTH-1:0] addr, // Local offset in terms of number of units
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output [DATA_WIDTH-1:0] data_out, // The data port for read
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// Configure port
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input [BASE_ADDR_WIDTH-1:0] mmap_addr // The base address of memory map.
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);
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reg [DATA_WIDTH-1:0] reg_data;
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assign data_out = reg_data;
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endmodule
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// Write only memory map, one cycle write.
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// Usage: create and pass instance to additional arguments of $tvm_session.
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module tvm_vpi_write_mmap
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#(
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parameter DATA_WIDTH = 8,
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parameter ADDR_WIDTH = 8,
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parameter BASE_ADDR_WIDTH = 32
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)
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(
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input clk,
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input rst,
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// Write Ports
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input [ADDR_WIDTH-1:0] addr, // Local offset in terms of number of units
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input [DATA_WIDTH-1:0] data_in, // The data port for write
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input en, // The enable port for write
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// Configure port
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input [BASE_ADDR_WIDTH-1:0] mmap_addr // The base address of memap
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);
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endmodule
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