421 строка
13 KiB
TypeScript
421 строка
13 KiB
TypeScript
declare namespace DapJS {
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export interface IHID {
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write(data: ArrayBuffer): Promise<void>;
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read(): Promise<Uint8Array>;
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close(): Promise<void>;
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// sends each of commands and expects one packet in response
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// this makes for better performance when HID access is proxied
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sendMany?(commands: Uint8Array[]): Promise<Uint8Array[]>;
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}
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export class DAP {
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constructor(device: IHID);
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reconnect(): Promise<void>;
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init(): Promise<void>;
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close(): Promise<void>;
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}
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/**
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* # Memory Interface
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*
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* Controls access to the target's memory.
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*
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* ## Usage
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*
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* Using an instance of `CortexM`, as described before, we can simply read and
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* write numbers to memory as follows:
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*
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* ```typescript
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* const mem = core.memory;
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*
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* // NOTE: the address parameter must be word (4-byte) aligned.
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* await mem.write32(0x200000, 12345);
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* const val = await mem.read32(0x200000);
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*
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* // val === 12345
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*
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* // NOTE: the address parameter must be half-word (2-byte) aligned
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* await mem.write16(0x2000002, 65534);
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* const val16 = await mem.read16(0x2000002);
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*
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* // val16 === 65534
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* ```
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*
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* To write a larger block of memory, we can use `readBlock` and `writeBlock`. Again,
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* these blocks must be written to word-aligned addresses in memory.
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*
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* ```typescript
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* const data = new Uint32Array([0x1234, 0x5678, 0x9ABC, 0xDEF0]);
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* await mem.writeBlock(0x200000, data);
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*
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* const readData = await mem.readBlock(0x200000, data.length, 0x100);
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* ```
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*
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* ## See also
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*
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* `PreparedMemoryCommand` provides an equivalent API with better performance (in some
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* cases) by enabling batched memory operations.
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*/
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export class Memory {
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private dev;
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constructor(dev: DAP);
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/**
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* Write a 32-bit word to the specified (word-aligned) memory address.
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*
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* @param addr Memory address to write to
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* @param data Data to write (values above 2**32 will be truncated)
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*/
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write32(addr: number, data: number): Promise<void>;
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/**
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* Write a 16-bit word to the specified (half word-aligned) memory address.
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*
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* @param addr Memory address to write to
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* @param data Data to write (values above 2**16 will be truncated)
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*/
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write16(addr: number, data: number): Promise<void>;
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/**
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* Read a 32-bit word from the specified (word-aligned) memory address.
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*
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* @param addr Memory address to read from.
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*/
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read32(addr: number): Promise<number>;
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/**
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* Read a 16-bit word from the specified (half word-aligned) memory address.
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*
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* @param addr Memory address to read from.
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*/
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read16(addr: number): Promise<number>;
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/**
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* Reads a block of memory from the specified memory address.
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*
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* @param addr Address to read from
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* @param words Number of words to read
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* @param pageSize Memory page size
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*/
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readBlock(addr: number, words: number, pageSize: number): Promise<Uint8Array>;
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/**
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* Write a block of memory to the specified memory address.
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*
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* @param addr Memory address to write to.
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* @param words Array of 32-bit words to write to memory.
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*/
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writeBlock(addr: number, words: Uint32Array): Promise<void>;
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private readBlockCore(addr, words);
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private writeBlockCore(addr, words);
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}
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/**
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* # Cortex M
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*
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* Manages access to a CPU core, and its associated memory and debug functionality.
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*
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* > **NOTE:** all of the methods that involve interaction with the CPU core
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* > are asynchronous, so must be `await`ed, or explicitly handled as a Promise.
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*
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* ## Usage
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*
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* First, let's create an instance of `CortexM`, using an associated _Debug Access
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* Port_ (DAP) instance that we created earlier.
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*
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* ```typescript
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* const core = new CortexM(dap);
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* ```
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*
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* Now, we can halt and resume the core just like this:
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*
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* > **NOTE:** If you're not using ES2017, you can replace the use of `async` and
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* > `await` with direct use of Promises. These examples also need to be run within
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* > an `async` function for `async` to be used.
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*
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* ```typescript
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* await core.halt();
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* await core.resume();
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* ```
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*
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* Resetting the core is just as easy:
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*
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* ```typescript
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* await core.reset();
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* ```
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*
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* You can even halt immediately after reset:
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*
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* ```typescript
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* await core.reset(true);
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* ```
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*
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* We can also read and write 32-bit values to/from core registers:
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*
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* ```typescript
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* const sp = await core.readCoreRegister(CortexReg.SP);
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*
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* await core.writeCoreRegister(CortexReg.R0, 0x1000);
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* await core.writeCoreRegister(CortexReg.PC, 0x1234);
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* ```
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*
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* ### See also
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*
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* For details on debugging and memory features, see the documentation for
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* `Debug` and `Memory`.
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*/
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export class CortexM {
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/**
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* Read and write to on-chip memory associated with this CPU core.
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*/
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memory: Memory;
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/**
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* Control the CPU's debugging features.
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*/
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debug: Debug;
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/**
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* Underlying Debug Access Port (DAP).
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*/
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private dev;
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constructor(device: DAP);
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/**
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* Initialise the debug access port on the device, and read the device type.
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*/
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init(): Promise<void>;
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/**
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* Read the current state of the CPU.
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*
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* @returns A member of the `CoreState` enum corresponding to the current status of the CPU.
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*/
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getState(): Promise<CoreState>;
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/**
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* Read a core register from the CPU (e.g. r0...r15, pc, sp, lr, s0...)
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*
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* @param no Member of the `CortexReg` enum - an ARM Cortex CPU general-purpose register.
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*/
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readCoreRegister(no: CortexReg): Promise<number>;
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/**
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* Write a 32-bit word to the specified CPU general-purpose register.
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*
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* @param no Member of the `CortexReg` enum - an ARM Cortex CPU general-purpose register.
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* @param val Value to be written.
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*/
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writeCoreRegister(no: CortexReg, val: number): Promise<void>;
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/**
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* Halt the CPU core.
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*/
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halt(): Promise<void>;
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/**
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* Resume the CPU core.
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*/
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resume(): Promise<void>;
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/**
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* Find out whether the CPU is halted.
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*/
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isHalted(): Promise<boolean>;
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/**
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* Read the current status of the CPU.
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*
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* @returns Object containing the contents of the `DHCSR` register, the `DFSR` register, and a boolean value
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* stating the current halted state of the CPU.
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*/
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status(): Promise<{
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dfsr: number;
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dhscr: number;
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isHalted: boolean;
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}>;
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/**
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* Reset the CPU core. This currently does a software reset - it is also technically possible to perform a 'hard'
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* reset using the reset pin from the debugger.
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*/
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reset(halt?: boolean): Promise<void>;
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/**
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* Run specified machine code natively on the device. Assumes usual C calling conventions
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* - returns the value of r0 once the program has terminated. The program _must_ terminate
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* in order for this function to return. This can be achieved by placing a `bkpt`
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* instruction at the end of the function.
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*
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* @param code array containing the machine code (32-bit words).
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* @param address memory address at which to place the code.
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* @param pc initial value of the program counter.
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* @param lr initial value of the link register.
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* @param sp initial value of the stack pointer.
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* @param upload should we upload the code before running it.
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* @param args set registers r0...rn before running code
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*
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* @returns A promise for the value of r0 on completion of the function call.
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*/
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runCode(code: Uint32Array, address: number, pc: number, lr: number, sp: number, upload: boolean, ...args: number[]): Promise<number>;
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/**
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* Spin until the chip has halted.
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*/
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waitForHalt(timeout?: number): Promise<void>;
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prepareCommand(): PreparedCortexMCommand;
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private softwareReset();
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}
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/**
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* # Cortex M: Prepared Command
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*
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* Allows batching of Cortex M-related commands, such as writing to a register,
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* halting and resuming the core.
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*
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* ## Example
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*
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* When preparing the sequence of commands, we can use the same API to prepare
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* a command as we would to execute them immediately.
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*
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* ```typescript
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* // Note that only the .go method is asynchronous.
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*
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* const prep = core.prepareCommand();
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* prep.writeCoreRegister(CortexReg.R0, 0x1000);
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* prep.writeCoreRegister(CortexReg.R1, 0x0);
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* prep.writeCoreRegister(CortexReg.PC, 0x2000000);
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* prep.resume();
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* ```
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*
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* We can then execute them as efficiently as possible by combining them together
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* and executing them like so.
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*
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* ```typescript
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* await prep.go();
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* ```
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*
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* The code above is equivalent to the following _non-prepared_ command:
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*
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* ```typescript
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* await core.writeCoreRegister(CortexReg.R0, 0x1000);
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* await core.writeCoreRegister(CortexReg.R1, 0x0);
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* await core.writeCoreRegister(CortexReg.PC, 0x2000000);
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* await core.resume();
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* ```
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*
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* Since the batched version of this code avoids making three round-trips to the
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* target, we are able to significantly improve performance. This is especially
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* noticable when uploading a binary to flash memory, where are large number of
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* repetetive commands are being used.
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*
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* ## Explanation
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*
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* For a detailed explanation of why prepared commands are used in DAP.js, see the
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* documentation for `PreparedDapCommand`.
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*/
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export class PreparedCortexMCommand {
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private cmd;
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constructor(dap: DAP);
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/**
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* Schedule a 32-bit integer to be written to a core register.
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*
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* @param no Core register to be written.
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* @param val Value to write.
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*/
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writeCoreRegister(no: CortexReg, val: number): void;
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/**
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* Schedule a halt command to be written to the CPU.
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*/
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halt(): void;
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/**
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* Schedule a resume command to be written to the CPU.
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*/
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resume(): void;
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/**
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* Execute all scheduled commands.
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*/
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go(): Promise<void>;
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}
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export const enum CortexReg {
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R0 = 0,
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R1 = 1,
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R2 = 2,
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R3 = 3,
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R4 = 4,
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R5 = 5,
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R6 = 6,
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R7 = 7,
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R8 = 8,
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R9 = 9,
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R10 = 10,
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R11 = 11,
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R12 = 12,
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SP = 13,
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LR = 14,
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PC = 15,
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XPSR = 16,
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MSP = 17,
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PSP = 18,
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PRIMASK = 20,
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CONTROL = 20,
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}
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export const enum CoreState {
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TARGET_RESET = 0,
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TARGET_LOCKUP = 1,
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TARGET_SLEEPING = 2,
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TARGET_HALTED = 3,
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TARGET_RUNNING = 4,
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}
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/**
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* # Debug Interface
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*
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* Keeps track of breakpoints set on the target, as well as deciding whether to
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* use a hardware breakpoint or a software breakpoint.
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*
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* ## Usage
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*
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* ```typescript
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* const dbg = core.debug;
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*
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* await dbg.setBreakpoint(0x123456);
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*
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* // resume the core and wait for the breakpoint
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* await core.resume();
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* await core.waitForHalt();
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*
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* // step forward one instruction
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* await dbg.step();
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*
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* // remove the breakpoint
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* await dbg.deleteBreakpoint(0x123456);
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* ```
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*/
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export class Debug {
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private core;
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private breakpoints;
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private availableHWBreakpoints;
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private totalHWBreakpoints;
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private enabled;
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constructor(core: CortexM);
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init(): Promise<void>;
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/**
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* Enable debugging on the target CPU
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*/
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enable(): Promise<void>;
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/**
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* Set breakpoints at specified memory addresses.
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*
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* @param addrs An array of memory addresses at which to set breakpoints.
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*/
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setBreakpoint(addr: number): Promise<void>;
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deleteBreakpoint(addr: number): Promise<void>;
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/**
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* Step the processor forward by one instruction.
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*/
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step(): Promise<void>;
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/**
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* Set up (and disable) the Flash Patch & Breakpoint unit. It will be enabled when
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* the first breakpoint is set.
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*
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* Also reads the number of available hardware breakpoints.
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*/
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private setupFpb();
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/**
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* Enable or disable the Flash Patch and Breakpoint unit (FPB).
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*
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* @param enabled
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*/
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private setFpbEnabled(enabled?);
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}
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} |