src/executor,model: use more registers

src/config.py

@@ -52,10 +52,11 @@ class ConfCls:
     # segment registers are also excluded as we don't support their handling so far
     # same for CR* and DR*
     gpr_blocklist = [
-        'R8', 'R9', 'R10', 'R11', 'R12', 'R13', 'R14', 'R15', 'RSP', 'RBP', 'RDI', 'RSI',
-        'R8D', 'R9D', 'R10D', 'R11D', 'R12D', 'R13D', 'R14D', 'R15D', 'ESP', 'EBP', 'EDI', 'ESI',
-        'R8W', 'R9W', 'R10W', 'R11W', 'R12W', 'R13W', 'R14W', 'R15W', 'SP', 'BP', 'DI', 'SI',
-        'R8B', 'R9B', 'R10B', 'R11B', 'R12B', 'R13B', 'R14B', 'R15B', 'SPL', 'BPL', 'DL', 'SL',
+        # free - rax, rbx, rcx, rdx, r8, r9, r10
+        'R10', 'R11', 'R12', 'R13', 'R14', 'R15', 'RSP', 'RBP', 'RDI', 'RSI',
+        'R10D', 'R11D', 'R12D', 'R13D', 'R14D', 'R15D', 'ESP', 'EBP', 'EDI', 'ESI',
+        'R10W', 'R11W', 'R12W', 'R13W', 'R14W', 'R15W', 'SP', 'BP', 'DI', 'SI',
+        'R10B', 'R11B', 'R12B', 'R13B', 'R14B', 'R15B', 'SPL', 'BPL', 'DL', 'SL',
         'ES', 'CS', 'SS', 'DS', 'FS', 'GS',
         'CR0', 'CR2', 'CR3', 'CR4', 'CR8',
         'DR0', 'DR1', 'DR2', 'DR3', 'DR4', 'DR5', 'DR6', 'DR7'

src/executor/x86

@@ -1 +1 @@
-Subproject commit cb277fbbfc3f51a0b7c13172e47692420f6cbff7
+Subproject commit dbbbbd714feb3f24ff5413f683fcea2d2351516b

src/model.py

@@ -296,7 +296,8 @@ class X86UnicornModel(Model):
                                     masked_rvalue.to_bytes(8, byteorder='little'))
 
         # Values in registers
-        for reg in [UC_X86_REG_RAX, UC_X86_REG_RBX, UC_X86_REG_RCX, UC_X86_REG_RDX]:
+        for reg in [UC_X86_REG_RAX, UC_X86_REG_RBX, UC_X86_REG_RCX, UC_X86_REG_RDX, UC_X86_REG_R8,
+                    UC_X86_REG_R9, UC_X86_REG_R10]:
             random_value = ((random_value * 2891336453) % POW32 + 12345) % POW32
             masked_rvalue = (random_value ^ (random_value >> 16)) & input_mask
             self.emulator.reg_write(reg, masked_rvalue)