src: controllable entropy of inputs
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4fff6fcf1a
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8f856bb02a
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@ -60,6 +60,7 @@ class ConfCls:
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# Input Generator
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prng_seed: int = 10 # zero is a reserved value, do not use it
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avoid_data_dependencies: bool = True
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input_mask: int = 0xffffffff
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# ==============================================================================================
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# Model
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model: str = 'x86-unicorn' # options: 'x86-serializing', 'x86-unicorn'
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@ -11,8 +11,14 @@ supported_categories:
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- LOGICAL
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- POP
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- PUSH
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attacker_capability: l1d # ct, l1d
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attacker_capability: l1d
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contracts:
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- seq
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# - seq
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# - cond
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# - bpas
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- bpas
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# max_nesting: 2
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# attack_variant: P+P
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enable_ssbp_patch: false
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enable_mds: false
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input_mask: 255
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#verbose: 999
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@ -41,6 +41,7 @@ class X86Intel(Executor):
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write_to_pseudo_file("F", "/sys/x86-executor/measurement_mode")
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elif CONF.attack_variant == 'P+P':
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write_to_pseudo_file("P", "/sys/x86-executor/measurement_mode")
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write_to_pseudo_file(CONF.input_mask, '/sys/x86-executor/input_mask')
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def load_test_case(self, test_case_asm: str):
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assemble(test_case_asm, 'generated.o')
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@ -215,12 +215,14 @@ class X86UnicornModel(Model):
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random_value = seed
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random_value = ((random_value * 2891336453) % POW32 + 12345) % POW32
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for i in range(0, 4096, 64):
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self.emulator.mem_write(self.r14_init + i, random_value.to_bytes(8, byteorder='little'))
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masked_rvalue = random_value & CONF.input_mask
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self.emulator.mem_write(self.r14_init + i, masked_rvalue.to_bytes(8, byteorder='little'))
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# Values in registers
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for reg in [UC_X86_REG_RAX, UC_X86_REG_RBX, UC_X86_REG_RCX, UC_X86_REG_RDX]:
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random_value = ((random_value * 2891336453) % POW32 + 12345) % POW32
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self.emulator.reg_write(reg, random_value)
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masked_rvalue = random_value & CONF.input_mask
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self.emulator.reg_write(reg, masked_rvalue)
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# FLAGS
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random_value = ((random_value * 2891336453) % POW32 + 12345) % POW32
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@ -1,10 +1,9 @@
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.intel_syntax noprefix
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MFENCE
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MOV rbx, r14
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MOV rax, [rbx + 128]
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MOV rax, [rbx + 128]
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MOV rax, [rbx + 128]
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MOV rax, [rbx + 128]
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MOV rax, [rbx + 128]
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MOV rax, [rbx + 128]
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MOV rax, [r14 + 128]
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MOV rax, [r14 + 128]
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MOV rax, [r14 + 128]
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MOV rax, [r14 + 128]
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MOV rax, [r14 + 128]
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MOV rax, [r14 + 128]
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MFENCE
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