exec/x86/vmx: [refact] rename DEFAULT_*_CTRL to MUST_SET_*_CTRL
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@ -48,30 +48,29 @@
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// Table 25-5. Definitions of Pin-Based VM-Execution Controls
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// IMPORTANT: never combine setting of PIN_BASED_EXT_INTR_MASK and VM_EXIT_ACK_INTR_ON_EXIT
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// (i.e., at least one must be disabled); otherwise, interrupts lead to system crash
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#define DEFAULT_PIN_BASED_VM_EXEC_CONTROL \
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#define MUST_SET_PIN_BASED_VM_EXEC_CONTROL \
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(PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS | PIN_BASED_VMX_PREEMPTION_TIMER)
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#define NOT_SUPPORTED_PIN_BASED_VM_EXEC_CONTROL (PIN_BASED_EXT_INTR_MASK | PIN_BASED_POSTED_INTR)
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#define MUST_CLEAR_PIN_BASED_VM_EXEC_CONTROL (PIN_BASED_EXT_INTR_MASK | PIN_BASED_POSTED_INTR)
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// Table 25-6. Definitions of Primary Processor-Based VM-Execution Controls
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// DO NOT add CPU_BASED_RDPMC_EXITING because we may need it if guest primes or probes
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#define DEFAULT_PRIMARY_VM_EXEC_CONTROL \
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#define MUST_SET_PRIMARY_VM_EXEC_CONTROL \
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(CPU_BASED_INTR_WINDOW_EXITING | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | \
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CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING | \
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CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | CPU_BASED_MOV_DR_EXITING | \
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CPU_BASED_UNCOND_IO_EXITING | CPU_BASED_MONITOR_EXITING | CPU_BASED_PAUSE_EXITING | \
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CPU_BASED_ACTIVATE_SECONDARY_CONTROLS | CPU_BASED_NMI_WINDOW_EXITING)
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#define NOT_SUPPORTED_PRIMARY_VM_EXEC_CONTROL \
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#define MUST_CLEAR_PRIMARY_VM_EXEC_CONTROL \
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(CPU_BASED_USE_TSC_OFFSETTING | CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING | \
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CPU_BASED_ACTIVATE_TERTIARY_CONTROLS | CPU_BASED_TPR_SHADOW | CPU_BASED_USE_IO_BITMAPS | \
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CPU_BASED_MONITOR_TRAP_FLAG | CPU_BASED_USE_MSR_BITMAPS)
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// Table 25-7. Definitions of Secondary Processor-Based VM-Execution Controls
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#define DEFAULT_SECONDARY_VM_EXEC_CONTROL \
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#define MUST_SET_SECONDARY_VM_EXEC_CONTROL \
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(SECONDARY_EXEC_ENABLE_EPT | SECONDARY_EXEC_DESC | SECONDARY_EXEC_WBINVD_EXITING | \
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SECONDARY_EXEC_ENCLS_EXITING | SECONDARY_EXEC_ENABLE_INVPCID | \
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SECONDARY_EXEC_RDRAND_EXITING | SECONDARY_EXEC_RDSEED_EXITING)
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#define OPTIONAL_SECONDARY_VM_EXEC_CONTROL (SECONDARY_EXEC_PAUSE_LOOP_EXITING)
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#define NOT_SUPPORTED_SECONDARY_VM_EXEC_CONTROL \
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#define MUST_CLEAR_SECONDARY_VM_EXEC_CONTROL \
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(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | SECONDARY_EXEC_RDTSCP | \
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SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | SECONDARY_EXEC_ENABLE_VPID | \
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SECONDARY_EXEC_UNRESTRICTED_GUEST | SECONDARY_EXEC_APIC_REGISTER_VIRT | \
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@ -87,15 +86,15 @@
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#define DEFAULT_EXCEPTION_BITMAP 0xFFFFFFFF // all exceptions are redirected to host
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// Exit/entry controls
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#define DEFAULT_EXIT_CTRL (VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_HOST_ADDR_SPACE_SIZE)
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#define NOT_SUPPORTED_EXIT_CTRL \
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#define MUST_SET_EXIT_CTRL (VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_HOST_ADDR_SPACE_SIZE)
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#define MUST_CLEAR_EXIT_CTRL \
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(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT | \
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VM_EXIT_SAVE_IA32_EFER | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | \
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VM_EXIT_CLEAR_BNDCFGS | VM_EXIT_PT_CONCEAL_PIP | VM_EXIT_CLEAR_IA32_RTIT_CTL | \
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VM_EXIT_ACK_INTR_ON_EXIT)
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#define DEFAULT_ENTRY_CTRL (VM_ENTRY_LOAD_DEBUG_CONTROLS | VM_ENTRY_IA32E_MODE)
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#define NOT_SUPPORTED_ENTRY_CTRL \
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#define MUST_SET_ENTRY_CTRL (VM_ENTRY_LOAD_DEBUG_CONTROLS | VM_ENTRY_IA32E_MODE)
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#define MUST_CLEAR_ENTRY_CTRL \
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(VM_ENTRY_SMM | VM_ENTRY_DEACT_DUAL_MONITOR | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \
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VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER | VM_ENTRY_LOAD_BNDCFGS | \
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VM_ENTRY_PT_CONCEAL_PIP | VM_ENTRY_LOAD_IA32_RTIT_CTL | VM_EXIT_UINV | VM_ENTRY_CET | \
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@ -5,12 +5,12 @@
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#include "macro_loader.h"
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#include "asm_snippets.h"
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#include "memory_guest.h"
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#include "vmx.h"
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#include "main.h"
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#include "memory_guest.h"
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#include "sandbox_manager.h"
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#include "shortcuts.h"
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#include "test_case_parser.h"
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#include "vmx.h"
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// Max sizes for sanity checks
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#define MAX_MACRO_START_OFFSET 0x100
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@ -225,23 +225,21 @@ int vmx_check_cpu_compatibility(void)
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// Pin-based controls
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msr_value = rdmsr64(MSR_IA32_VMX_TRUE_PINBASED_CTLS);
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ASSERT((msr_value & NOT_SUPPORTED_PIN_BASED_VM_EXEC_CONTROL) == 0,
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"vmx_check_cpu_compatibility");
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ASSERT((msr_value & MUST_CLEAR_PIN_BASED_VM_EXEC_CONTROL) == 0, "vmx_check_cpu_compatibility");
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// Primary processor-based controls
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msr_value = rdmsr64(MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
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ASSERT((msr_value & NOT_SUPPORTED_PRIMARY_VM_EXEC_CONTROL) == 0, "vmx_check_cpu_compatibility");
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ASSERT((msr_value & MUST_CLEAR_PRIMARY_VM_EXEC_CONTROL) == 0, "vmx_check_cpu_compatibility");
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// Secondary
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msr_value = rdmsr64(MSR_IA32_VMX_PROCBASED_CTLS2);
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ASSERT((msr_value & NOT_SUPPORTED_SECONDARY_VM_EXEC_CONTROL) == 0,
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"vmx_check_cpu_compatibility");
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ASSERT((msr_value & MUST_CLEAR_SECONDARY_VM_EXEC_CONTROL) == 0, "vmx_check_cpu_compatibility");
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// Exit/entry
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msr_value = rdmsr64(MSR_IA32_VMX_TRUE_EXIT_CTLS);
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ASSERT((msr_value & NOT_SUPPORTED_EXIT_CTRL) == 0, "vmx_check_cpu_compatibility");
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ASSERT((msr_value & MUST_CLEAR_EXIT_CTRL) == 0, "vmx_check_cpu_compatibility");
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msr_value = rdmsr64(MSR_IA32_VMX_TRUE_ENTRY_CTLS);
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ASSERT((msr_value & NOT_SUPPORTED_ENTRY_CTRL) == 0, "vmx_check_cpu_compatibility");
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ASSERT((msr_value & MUST_CLEAR_ENTRY_CTRL) == 0, "vmx_check_cpu_compatibility");
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return 0;
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}
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@ -459,10 +457,10 @@ static int set_vmcs_guest_state(void)
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(uint64_t)&guest_v_memory->data.main_area[LOCAL_RSP_OFFSET]);
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CHECKED_VMWRITE(GUEST_SYSENTER_EIP, (uint64_t)&guest_v_memory->code.section[0]);
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ASSERT((VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL & NOT_SUPPORTED_ENTRY_CTRL) != 0,
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ASSERT((VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL & MUST_CLEAR_ENTRY_CTRL) != 0,
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"set_vmcs_guest_state");
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ASSERT((VM_ENTRY_LOAD_IA32_PAT & NOT_SUPPORTED_ENTRY_CTRL) != 0, "set_vmcs_guest_state");
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ASSERT((VM_ENTRY_LOAD_IA32_EFER & NOT_SUPPORTED_ENTRY_CTRL) != 0, "set_vmcs_guest_state");
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ASSERT((VM_ENTRY_LOAD_IA32_PAT & MUST_CLEAR_ENTRY_CTRL) != 0, "set_vmcs_guest_state");
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ASSERT((VM_ENTRY_LOAD_IA32_EFER & MUST_CLEAR_ENTRY_CTRL) != 0, "set_vmcs_guest_state");
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// SDM 25.4.2 Guest Non-Register State
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CHECKED_VMWRITE(GUEST_ACTIVITY_STATE, 0);
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@ -523,9 +521,8 @@ static int set_vmcs_host_state(void)
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CHECKED_VMWRITE(HOST_IA32_SYSENTER_EIP, rdmsr64(MSR_IA32_SYSENTER_EIP));
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CHECKED_VMWRITE(HOST_IA32_EFER, rdmsr64(MSR_EFER));
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ASSERT((VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL & NOT_SUPPORTED_EXIT_CTRL) != 0,
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"set_vmcs_host_state");
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ASSERT((VM_EXIT_LOAD_IA32_PAT & NOT_SUPPORTED_EXIT_CTRL) != 0, "set_vmcs_host_state");
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ASSERT((VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL & MUST_CLEAR_EXIT_CTRL) != 0, "set_vmcs_host_state");
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ASSERT((VM_EXIT_LOAD_IA32_PAT & MUST_CLEAR_EXIT_CTRL) != 0, "set_vmcs_host_state");
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return 0;
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}
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@ -535,7 +532,7 @@ static int set_vmcs_exec_control(int actor_id)
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uint8_t err_inv, err_val = 0;
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// SDM 25.6.1 Pin-Based VM-Execution Controls
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uint32_t pin_based_vm_exec_control = DEFAULT_PIN_BASED_VM_EXEC_CONTROL |
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uint32_t pin_based_vm_exec_control = MUST_SET_PIN_BASED_VM_EXEC_CONTROL |
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(rdmsr64(MSR_IA32_VMX_TRUE_PINBASED_CTLS) & 0xFFFFFFFFULL);
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if (check_vmx_controls(pin_based_vm_exec_control, MSR_IA32_VMX_TRUE_PINBASED_CTLS))
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return -1;
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@ -543,15 +540,15 @@ static int set_vmcs_exec_control(int actor_id)
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// SDM 25.6.2 Processor-Based VM-Execution Controls
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// - primary
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uint32_t primary_vm_exec_control = DEFAULT_PRIMARY_VM_EXEC_CONTROL |
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uint32_t primary_vm_exec_control = MUST_SET_PRIMARY_VM_EXEC_CONTROL |
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(rdmsr64(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) & 0xFFFFFFFFULL);
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if (check_vmx_controls(primary_vm_exec_control, MSR_IA32_VMX_TRUE_PROCBASED_CTLS))
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return -1;
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CHECKED_VMWRITE(CPU_BASED_VM_EXEC_CONTROL, primary_vm_exec_control);
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// - secondary
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uint32_t secondary_vm_exec_control =
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DEFAULT_SECONDARY_VM_EXEC_CONTROL | (rdmsr64(MSR_IA32_VMX_PROCBASED_CTLS2) & 0xFFFFFFFFULL);
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uint32_t secondary_vm_exec_control = MUST_SET_SECONDARY_VM_EXEC_CONTROL |
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(rdmsr64(MSR_IA32_VMX_PROCBASED_CTLS2) & 0xFFFFFFFFULL);
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if (check_vmx_controls(secondary_vm_exec_control, MSR_IA32_VMX_PROCBASED_CTLS2))
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return -1;
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CHECKED_VMWRITE(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control);
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@ -615,7 +612,8 @@ static int set_vmcs_exit_control(void)
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{
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uint8_t err_inv, err_val = 0;
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uint64_t exit_ctls = DEFAULT_EXIT_CTRL | (rdmsr64(MSR_IA32_VMX_TRUE_EXIT_CTLS) & 0xFFFFFFFFULL);
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uint64_t exit_ctls =
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MUST_SET_EXIT_CTRL | (rdmsr64(MSR_IA32_VMX_TRUE_EXIT_CTLS) & 0xFFFFFFFFULL);
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if (check_vmx_controls(exit_ctls, MSR_IA32_VMX_TRUE_EXIT_CTLS))
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return -1;
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CHECKED_VMWRITE(VM_EXIT_CONTROLS, exit_ctls);
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@ -631,7 +629,7 @@ static int set_vmcs_entry_control(void)
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uint8_t err_inv, err_val = 0;
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uint64_t entry_ctls =
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DEFAULT_ENTRY_CTRL | (rdmsr64(MSR_IA32_VMX_TRUE_ENTRY_CTLS) & 0xFFFFFFFFULL);
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MUST_SET_ENTRY_CTRL | (rdmsr64(MSR_IA32_VMX_TRUE_ENTRY_CTLS) & 0xFFFFFFFFULL);
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if (check_vmx_controls(entry_ctls, MSR_IA32_VMX_TRUE_ENTRY_CTLS))
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return -1;
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CHECKED_VMWRITE(VM_ENTRY_CONTROLS, entry_ctls);
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@ -656,20 +654,20 @@ static int make_vmcs_launched(int actor_id)
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// launch VM
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asm volatile(""
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"lea (1f), %%rax\n"
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"mov $0x00006c16, %%rcx\n"
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"vmwrite %%rax, %%rcx\n"
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"mov %%rsp, %%rax\n"
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"mov $0x00006c14, %%rcx\n"
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"vmwrite %%rax, %%rcx\n"
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"vmlaunch; setc %[inval]; setz %[val]\n"
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"1:\n"
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: [val] "=rm"(err_val), [inval] "=rm"(err_inv)
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:
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: "cc", "memory", "rax", "rcx");
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"lea (1f), %%rax\n"
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"mov $0x00006c16, %%rcx\n"
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"vmwrite %%rax, %%rcx\n"
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"mov %%rsp, %%rax\n"
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"mov $0x00006c14, %%rcx\n"
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"vmwrite %%rax, %%rcx\n"
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"vmlaunch; setc %[inval]; setz %[val]\n"
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"1:\n"
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: [val] "=rm"(err_val), [inval] "=rm"(err_inv)
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:
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: "cc", "memory", "rax", "rcx");
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// PRINT_ERR("make_vmcs_launched: exited with VMfailInvalid=%d, VMfailValid=%d\n", err_inv,
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// err_val);
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// err_val);
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// print_vmx_exit_info();
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// finalize VMCS fields
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