msm: camera: cpas: Fix TCSR register programming
Program TCSR_CAMERA_HF_SF_ARES_GLITCH_MASK to ignore erroneous signals. CRs-Fixed: 2545751 Change-Id: Ie638136d364372b7a8309af1d9656a8c8b7772fc Signed-off-by: Trishansh Bhardwaj <tbhardwa@codeaurora.org>
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a62a432522
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@ -44,7 +44,7 @@ int cam_cpas_util_reg_update(struct cam_hw_info *cpas_hw,
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value = reg_info->value;
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}
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CAM_DBG(CAM_CPAS, "Base[%d] Offset[0x%8x] Value[0x%8x]",
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CAM_DBG(CAM_CPAS, "Base[%d] Offset[0x%08x] Value[0x%08x]",
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reg_base, reg_info->offset, value);
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cam_io_w_mb(value, soc_info->reg_map[reg_base_index].mem_base +
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@ -7,6 +7,8 @@
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#include <linux/timer.h>
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#include <linux/slab.h>
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#include <soc/qcom/scm.h>
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#include "cam_cpas_hw_intf.h"
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#include "cam_cpas_hw.h"
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#include "cam_cpastop_hw.h"
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@ -513,6 +515,10 @@ done:
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static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw)
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{
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int i;
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struct cam_cpas_hw_errata_wa_list *errata_wa_list =
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camnoc_info->errata_wa_list;
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struct cam_cpas_hw_errata_wa *errata_wa =
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&errata_wa_list->tcsr_camera_hf_sf_ares_glitch;
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cam_cpastop_reset_irq(cpas_hw);
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for (i = 0; i < camnoc_info->specific_size; i++) {
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@ -534,6 +540,11 @@ static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw)
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}
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}
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if (errata_wa->enable) {
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scm_io_write(errata_wa->data.reg_info.offset,
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errata_wa->data.reg_info.value);
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}
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return 0;
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}
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@ -208,10 +208,12 @@ struct cam_cpas_hw_errata_wa {
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*
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* @camnoc_flush_slave_pending_trans: Errata workaround info for flushing
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* camnoc slave pending transactions before turning off CPAS_TOP gdsc
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*
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* @tcsr_camera_hf_sf_ares_glitch: Errata workaround info from ignoring
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* erroneous signals at camera start
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*/
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struct cam_cpas_hw_errata_wa_list {
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struct cam_cpas_hw_errata_wa camnoc_flush_slave_pending_trans;
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struct cam_cpas_hw_errata_wa tcsr_camera_hf_sf_ares_glitch;
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};
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/**
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@ -747,6 +747,17 @@ static struct cam_cpas_hw_errata_wa_list cam175_cpas130_errata_wa_list = {
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.value = 0, /* expected to be 0 */
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},
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},
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/* TZ owned register */
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.tcsr_camera_hf_sf_ares_glitch = {
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.enable = true,
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.data.reg_info = {
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.enable = true,
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.access_type = CAM_REG_TYPE_READ_WRITE,
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/* TCSR_CAMERA_HF_SF_ARES_GLITCH_MASK */
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.offset = 0x01FCA08C,
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.value = 0x4, /* set bit[2] to 1 */
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},
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},
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};
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static struct cam_camnoc_info cam175_cpas130_camnoc_info = {
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