mips msa vp9 fdct 4x4 optimization
average improvement ~2x-3x Change-Id: Idf8be780b8b4228fc91f110a94e4ee1fd9af0163
This commit is contained in:
Parag Salasakar
Родитель
1395b56a1d
Коммит
bc94999148
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@ -541,13 +541,13 @@ INSTANTIATE_TEST_CASE_P(
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INSTANTIATE_TEST_CASE_P(
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MSA, Trans4x4DCT,
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::testing::Values(
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make_tuple(&vp9_fdct4x4_c, &vp9_idct4x4_16_add_msa, 1, VPX_BITS_8)));
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make_tuple(&vp9_fdct4x4_msa, &vp9_idct4x4_16_add_msa, 0, VPX_BITS_8)));
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INSTANTIATE_TEST_CASE_P(
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MSA, Trans4x4HT,
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::testing::Values(
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make_tuple(&vp9_fht4x4_c, &vp9_iht4x4_16_add_msa, 0, VPX_BITS_8),
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make_tuple(&vp9_fht4x4_c, &vp9_iht4x4_16_add_msa, 1, VPX_BITS_8),
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make_tuple(&vp9_fht4x4_c, &vp9_iht4x4_16_add_msa, 2, VPX_BITS_8),
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make_tuple(&vp9_fht4x4_c, &vp9_iht4x4_16_add_msa, 3, VPX_BITS_8)));
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make_tuple(&vp9_fht4x4_msa, &vp9_iht4x4_16_add_msa, 0, VPX_BITS_8),
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make_tuple(&vp9_fht4x4_msa, &vp9_iht4x4_16_add_msa, 1, VPX_BITS_8),
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make_tuple(&vp9_fht4x4_msa, &vp9_iht4x4_16_add_msa, 2, VPX_BITS_8),
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make_tuple(&vp9_fht4x4_msa, &vp9_iht4x4_16_add_msa, 3, VPX_BITS_8)));
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#endif // HAVE_MSA && !CONFIG_VP9_HIGHBITDEPTH && !CONFIG_EMULATE_HARDWARE
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} // namespace
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@ -467,6 +467,24 @@
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SH(out3_m, pblk_2x4_m + 3 * stride); \
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}
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/* Description : Store 4x2 byte block to destination memory from input vector
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Arguments : Inputs - in, pdst, stride
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Details : Index 0 word element from 'in' vector is copied to a GP
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register and stored to (pdst)
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Index 1 word element from 'in' vector is copied to a GP
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register and stored to (pdst + stride)
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*/
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#define ST4x2_UB(in, pdst, stride) { \
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uint32_t out0_m, out1_m; \
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uint8_t *pblk_4x2_m = (uint8_t *)(pdst); \
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\
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out0_m = __msa_copy_u_w((v4i32)in, 0); \
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out1_m = __msa_copy_u_w((v4i32)in, 1); \
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\
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SW(out0_m, pblk_4x2_m); \
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SW(out1_m, pblk_4x2_m + stride); \
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}
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/* Description : Store as 4x4 byte block to destination memory from input vector
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Arguments : Inputs - in0, in1, pdst, stride
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Return Type - unsigned byte
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@ -1472,6 +1490,22 @@
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}
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#define SRLI_H4_SH(...) SRLI_H4(v8i16, __VA_ARGS__)
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/* Description : Multiplication of pairs of vectors
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Arguments : Inputs - in0, in1, in2, in3
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Outputs - out0, out1
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Details : Each element from 'in0' is multiplied with elements from 'in1'
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and the result is written to 'out0'
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*/
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#define MUL2(in0, in1, in2, in3, out0, out1) { \
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out0 = in0 * in1; \
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out1 = in2 * in3; \
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}
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#define MUL4(in0, in1, in2, in3, in4, in5, in6, in7, \
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out0, out1, out2, out3) { \
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MUL2(in0, in1, in2, in3, out0, out1); \
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MUL2(in4, in5, in6, in7, out2, out3); \
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}
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/* Description : Addition of 2 pairs of vectors
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Arguments : Inputs - in0, in1, in2, in3
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Outputs - out0, out1
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@ -1023,7 +1023,7 @@ if (vpx_config("CONFIG_VP9_HIGHBITDEPTH") eq "yes") {
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specialize qw/vp9_fdct32x32_rd sse2/;
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} else {
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add_proto qw/void vp9_fht4x4/, "const int16_t *input, tran_low_t *output, int stride, int tx_type";
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specialize qw/vp9_fht4x4 sse2/;
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specialize qw/vp9_fht4x4 sse2 msa/;
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add_proto qw/void vp9_fht8x8/, "const int16_t *input, tran_low_t *output, int stride, int tx_type";
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specialize qw/vp9_fht8x8 sse2 msa/;
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@ -1032,13 +1032,13 @@ if (vpx_config("CONFIG_VP9_HIGHBITDEPTH") eq "yes") {
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specialize qw/vp9_fht16x16 sse2 msa/;
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add_proto qw/void vp9_fwht4x4/, "const int16_t *input, tran_low_t *output, int stride";
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specialize qw/vp9_fwht4x4/, "$mmx_x86inc";
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specialize qw/vp9_fwht4x4 msa/, "$mmx_x86inc";
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add_proto qw/void vp9_fdct4x4_1/, "const int16_t *input, tran_low_t *output, int stride";
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specialize qw/vp9_fdct4x4_1 sse2/;
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add_proto qw/void vp9_fdct4x4/, "const int16_t *input, tran_low_t *output, int stride";
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specialize qw/vp9_fdct4x4 sse2/;
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specialize qw/vp9_fdct4x4 sse2 msa/;
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add_proto qw/void vp9_fdct8x8_1/, "const int16_t *input, tran_low_t *output, int stride";
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specialize qw/vp9_fdct8x8_1 sse2 neon msa/;
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@ -0,0 +1,129 @@
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/*
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* Copyright (c) 2015 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include <assert.h>
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#include "./vp9_rtcd.h"
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#include "vp9/encoder/mips/msa/vp9_fdct_msa.h"
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void vp9_fwht4x4_msa(const int16_t *input, int16_t *output,
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int32_t src_stride) {
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v8i16 in0, in1, in2, in3, in4;
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LD_SH4(input, src_stride, in0, in1, in2, in3);
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in0 += in1;
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in3 -= in2;
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in4 = (in0 - in3) >> 1;
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SUB2(in4, in1, in4, in2, in1, in2);
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in0 -= in2;
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in3 += in1;
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TRANSPOSE4x4_SH_SH(in0, in2, in3, in1, in0, in2, in3, in1);
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in0 += in2;
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in1 -= in3;
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in4 = (in0 - in1) >> 1;
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SUB2(in4, in2, in4, in3, in2, in3);
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in0 -= in3;
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in1 += in2;
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SLLI_4V(in0, in1, in2, in3, 2);
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TRANSPOSE4x4_SH_SH(in0, in3, in1, in2, in0, in3, in1, in2);
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ST4x2_UB(in0, output, 4);
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ST4x2_UB(in3, output + 4, 4);
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ST4x2_UB(in1, output + 8, 4);
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ST4x2_UB(in2, output + 12, 4);
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}
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void vp9_fdct4x4_msa(const int16_t *input, int16_t *output,
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int32_t src_stride) {
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v8i16 in0, in1, in2, in3;
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LD_SH4(input, src_stride, in0, in1, in2, in3);
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/* fdct4 pre-process */
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{
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v8i16 vec, mask;
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v16i8 zero = { 0 };
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v16i8 one = __msa_ldi_b(1);
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mask = (v8i16)__msa_sldi_b(zero, one, 15);
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SLLI_4V(in0, in1, in2, in3, 4);
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vec = __msa_ceqi_h(in0, 0);
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vec = vec ^ 255;
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vec = mask & vec;
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in0 += vec;
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}
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VP9_FDCT4(in0, in1, in2, in3, in0, in1, in2, in3);
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TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
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VP9_FDCT4(in0, in1, in2, in3, in0, in1, in2, in3);
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TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
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ADD4(in0, 1, in1, 1, in2, 1, in3, 1, in0, in1, in2, in3);
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SRA_4V(in0, in1, in2, in3, 2);
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PCKEV_D2_SH(in1, in0, in3, in2, in0, in2);
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ST_SH2(in0, in2, output, 8);
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}
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void vp9_fht4x4_msa(const int16_t *input, int16_t *output, int32_t stride,
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int32_t tx_type) {
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v8i16 in0, in1, in2, in3;
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LD_SH4(input, stride, in0, in1, in2, in3);
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/* fdct4 pre-process */
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{
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v8i16 temp, mask;
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v16i8 zero = { 0 };
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v16i8 one = __msa_ldi_b(1);
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mask = (v8i16)__msa_sldi_b(zero, one, 15);
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SLLI_4V(in0, in1, in2, in3, 4);
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temp = __msa_ceqi_h(in0, 0);
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temp = (v8i16)__msa_xori_b((v16u8)temp, 255);
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temp = mask & temp;
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in0 += temp;
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}
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switch (tx_type) {
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case DCT_DCT:
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VP9_FDCT4(in0, in1, in2, in3, in0, in1, in2, in3);
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TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
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VP9_FDCT4(in0, in1, in2, in3, in0, in1, in2, in3);
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break;
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case ADST_DCT:
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VP9_FADST4(in0, in1, in2, in3, in0, in1, in2, in3);
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TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
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VP9_FDCT4(in0, in1, in2, in3, in0, in1, in2, in3);
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break;
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case DCT_ADST:
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VP9_FDCT4(in0, in1, in2, in3, in0, in1, in2, in3);
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TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
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VP9_FADST4(in0, in1, in2, in3, in0, in1, in2, in3);
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break;
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case ADST_ADST:
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VP9_FADST4(in0, in1, in2, in3, in0, in1, in2, in3);
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TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
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VP9_FADST4(in0, in1, in2, in3, in0, in1, in2, in3);
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break;
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default:
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assert(0);
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break;
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}
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TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
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ADD4(in0, 1, in1, 1, in2, 1, in3, 1, in0, in1, in2, in3);
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SRA_4V(in0, in1, in2, in3, 2);
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PCKEV_D2_SH(in1, in0, in3, in2, in0, in2);
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ST_SH2(in0, in2, output, 8);
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}
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@ -190,6 +190,67 @@
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vec1 >>= 2; \
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}
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#define VP9_FDCT4(in0, in1, in2, in3, out0, out1, out2, out3) { \
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v8i16 cnst0_m, cnst1_m, cnst2_m, cnst3_m; \
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v8i16 vec0_m, vec1_m, vec2_m, vec3_m; \
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v4i32 vec4_m, vec5_m, vec6_m, vec7_m; \
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v8i16 coeff_m = { cospi_16_64, -cospi_16_64, cospi_8_64, \
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cospi_24_64, -cospi_8_64, 0, 0, 0 }; \
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\
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BUTTERFLY_4(in0, in1, in2, in3, vec0_m, vec1_m, vec2_m, vec3_m); \
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ILVR_H2_SH(vec1_m, vec0_m, vec3_m, vec2_m, vec0_m, vec2_m); \
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SPLATI_H2_SH(coeff_m, 0, 1, cnst0_m, cnst1_m); \
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cnst1_m = __msa_ilvev_h(cnst1_m, cnst0_m); \
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vec5_m = __msa_dotp_s_w(vec0_m, cnst1_m); \
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\
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SPLATI_H2_SH(coeff_m, 4, 3, cnst2_m, cnst3_m); \
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cnst2_m = __msa_ilvev_h(cnst3_m, cnst2_m); \
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vec7_m = __msa_dotp_s_w(vec2_m, cnst2_m); \
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\
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vec4_m = __msa_dotp_s_w(vec0_m, cnst0_m); \
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cnst2_m = __msa_splati_h(coeff_m, 2); \
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cnst2_m = __msa_ilvev_h(cnst2_m, cnst3_m); \
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vec6_m = __msa_dotp_s_w(vec2_m, cnst2_m); \
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\
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SRARI_W4_SW(vec4_m, vec5_m, vec6_m, vec7_m, DCT_CONST_BITS); \
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PCKEV_H4_SH(vec4_m, vec4_m, vec5_m, vec5_m, vec6_m, vec6_m, \
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vec7_m, vec7_m, out0, out2, out1, out3); \
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}
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#define VP9_FADST4(in0, in1, in2, in3, out0, out1, out2, out3) { \
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v4i32 s0_m, s1_m, s2_m, s3_m, constant_m; \
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v4i32 in0_r_m, in1_r_m, in2_r_m, in3_r_m; \
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\
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UNPCK_R_SH_SW(in0, in0_r_m); \
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UNPCK_R_SH_SW(in1, in1_r_m); \
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UNPCK_R_SH_SW(in2, in2_r_m); \
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UNPCK_R_SH_SW(in3, in3_r_m); \
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\
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constant_m = __msa_fill_w(sinpi_4_9); \
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MUL2(in0_r_m, constant_m, in3_r_m, constant_m, s1_m, s0_m); \
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\
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constant_m = __msa_fill_w(sinpi_1_9); \
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s0_m += in0_r_m * constant_m; \
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s1_m -= in1_r_m * constant_m; \
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\
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constant_m = __msa_fill_w(sinpi_2_9); \
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s0_m += in1_r_m * constant_m; \
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s1_m += in3_r_m * constant_m; \
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\
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s2_m = in0_r_m + in1_r_m - in3_r_m; \
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\
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constant_m = __msa_fill_w(sinpi_3_9); \
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MUL2(in2_r_m, constant_m, s2_m, constant_m, s3_m, in1_r_m); \
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\
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in0_r_m = s0_m + s3_m; \
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s2_m = s1_m - s3_m; \
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s3_m = s1_m - s0_m + s3_m; \
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\
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SRARI_W4_SW(in0_r_m, in1_r_m, s2_m, s3_m, DCT_CONST_BITS); \
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PCKEV_H4_SH(in0_r_m, in0_r_m, in1_r_m, in1_r_m, s2_m, s2_m, \
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s3_m, s3_m, out0, out1, out2, out3); \
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}
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#define VP9_FDCT8(in0, in1, in2, in3, in4, in5, in6, in7, \
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out0, out1, out2, out3, out4, out5, out6, out7) { \
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v8i16 s0_m, s1_m, s2_m, s3_m, s4_m, s5_m, s6_m; \
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@ -152,6 +152,7 @@ VP9_CX_SRCS-$(HAVE_NEON) += encoder/arm/neon/vp9_quantize_neon.c
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VP9_CX_SRCS-$(HAVE_NEON) += encoder/arm/neon/vp9_subtract_neon.c
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VP9_CX_SRCS-$(HAVE_NEON) += encoder/arm/neon/vp9_variance_neon.c
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VP9_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/vp9_fdct4x4_msa.c
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VP9_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/vp9_fdct8x8_msa.c
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VP9_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/vp9_fdct16x16_msa.c
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VP9_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/vp9_fdct32x32_msa.c
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