VP9 common for ARMv8 by using NEON intrinsics 13
Add vp9_idct8x8_add_neon.c - vp9_idct8x8_64_add_neon - vp9_idct8x8_10_add_neon Change-Id: I6ee7b4496765aa36ed52990f2ef73e9f24459610 Signed-off-by: James Yu <james.yu@linaro.org>
This commit is contained in:
James Yu
Johann
Родитель
8c25f4af6a
Коммит
ce76aeb00d
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/*
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* Copyright (c) 2014 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include <arm_neon.h>
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static int16_t cospi_4_64 = 16069;
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static int16_t cospi_8_64 = 15137;
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static int16_t cospi_12_64 = 13623;
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static int16_t cospi_16_64 = 11585;
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static int16_t cospi_20_64 = 9102;
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static int16_t cospi_24_64 = 6270;
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static int16_t cospi_28_64 = 3196;
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static inline void TRANSPOSE8X8(
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int16x8_t *q8s16,
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int16x8_t *q9s16,
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int16x8_t *q10s16,
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int16x8_t *q11s16,
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int16x8_t *q12s16,
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int16x8_t *q13s16,
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int16x8_t *q14s16,
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int16x8_t *q15s16) {
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int16x4_t d16s16, d17s16, d18s16, d19s16, d20s16, d21s16, d22s16, d23s16;
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int16x4_t d24s16, d25s16, d26s16, d27s16, d28s16, d29s16, d30s16, d31s16;
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int32x4x2_t q0x2s32, q1x2s32, q2x2s32, q3x2s32;
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int16x8x2_t q0x2s16, q1x2s16, q2x2s16, q3x2s16;
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d16s16 = vget_low_s16(*q8s16);
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d17s16 = vget_high_s16(*q8s16);
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d18s16 = vget_low_s16(*q9s16);
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d19s16 = vget_high_s16(*q9s16);
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d20s16 = vget_low_s16(*q10s16);
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d21s16 = vget_high_s16(*q10s16);
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d22s16 = vget_low_s16(*q11s16);
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d23s16 = vget_high_s16(*q11s16);
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d24s16 = vget_low_s16(*q12s16);
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d25s16 = vget_high_s16(*q12s16);
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d26s16 = vget_low_s16(*q13s16);
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d27s16 = vget_high_s16(*q13s16);
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d28s16 = vget_low_s16(*q14s16);
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d29s16 = vget_high_s16(*q14s16);
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d30s16 = vget_low_s16(*q15s16);
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d31s16 = vget_high_s16(*q15s16);
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*q8s16 = vcombine_s16(d16s16, d24s16); // vswp d17, d24
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*q9s16 = vcombine_s16(d18s16, d26s16); // vswp d19, d26
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*q10s16 = vcombine_s16(d20s16, d28s16); // vswp d21, d28
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*q11s16 = vcombine_s16(d22s16, d30s16); // vswp d23, d30
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*q12s16 = vcombine_s16(d17s16, d25s16);
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*q13s16 = vcombine_s16(d19s16, d27s16);
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*q14s16 = vcombine_s16(d21s16, d29s16);
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*q15s16 = vcombine_s16(d23s16, d31s16);
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q0x2s32 = vtrnq_s32(vreinterpretq_s32_s16(*q8s16),
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vreinterpretq_s32_s16(*q10s16));
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q1x2s32 = vtrnq_s32(vreinterpretq_s32_s16(*q9s16),
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vreinterpretq_s32_s16(*q11s16));
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q2x2s32 = vtrnq_s32(vreinterpretq_s32_s16(*q12s16),
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vreinterpretq_s32_s16(*q14s16));
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q3x2s32 = vtrnq_s32(vreinterpretq_s32_s16(*q13s16),
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vreinterpretq_s32_s16(*q15s16));
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q0x2s16 = vtrnq_s16(vreinterpretq_s16_s32(q0x2s32.val[0]), // q8
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vreinterpretq_s16_s32(q1x2s32.val[0])); // q9
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q1x2s16 = vtrnq_s16(vreinterpretq_s16_s32(q0x2s32.val[1]), // q10
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vreinterpretq_s16_s32(q1x2s32.val[1])); // q11
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q2x2s16 = vtrnq_s16(vreinterpretq_s16_s32(q2x2s32.val[0]), // q12
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vreinterpretq_s16_s32(q3x2s32.val[0])); // q13
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q3x2s16 = vtrnq_s16(vreinterpretq_s16_s32(q2x2s32.val[1]), // q14
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vreinterpretq_s16_s32(q3x2s32.val[1])); // q15
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*q8s16 = q0x2s16.val[0];
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*q9s16 = q0x2s16.val[1];
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*q10s16 = q1x2s16.val[0];
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*q11s16 = q1x2s16.val[1];
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*q12s16 = q2x2s16.val[0];
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*q13s16 = q2x2s16.val[1];
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*q14s16 = q3x2s16.val[0];
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*q15s16 = q3x2s16.val[1];
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return;
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}
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static inline void IDCT8x8_1D(
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int16x8_t *q8s16,
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int16x8_t *q9s16,
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int16x8_t *q10s16,
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int16x8_t *q11s16,
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int16x8_t *q12s16,
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int16x8_t *q13s16,
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int16x8_t *q14s16,
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int16x8_t *q15s16) {
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int16x4_t d0s16, d1s16, d2s16, d3s16;
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int16x4_t d8s16, d9s16, d10s16, d11s16, d12s16, d13s16, d14s16, d15s16;
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int16x4_t d16s16, d17s16, d18s16, d19s16, d20s16, d21s16, d22s16, d23s16;
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int16x4_t d24s16, d25s16, d26s16, d27s16, d28s16, d29s16, d30s16, d31s16;
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int16x8_t q0s16, q1s16, q2s16, q3s16, q4s16, q5s16, q6s16, q7s16;
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int32x4_t q2s32, q3s32, q5s32, q6s32, q8s32, q9s32;
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int32x4_t q10s32, q11s32, q12s32, q13s32, q15s32;
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d0s16 = vdup_n_s16(cospi_28_64);
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d1s16 = vdup_n_s16(cospi_4_64);
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d2s16 = vdup_n_s16(cospi_12_64);
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d3s16 = vdup_n_s16(cospi_20_64);
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d16s16 = vget_low_s16(*q8s16);
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d17s16 = vget_high_s16(*q8s16);
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d18s16 = vget_low_s16(*q9s16);
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d19s16 = vget_high_s16(*q9s16);
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d20s16 = vget_low_s16(*q10s16);
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d21s16 = vget_high_s16(*q10s16);
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d22s16 = vget_low_s16(*q11s16);
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d23s16 = vget_high_s16(*q11s16);
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d24s16 = vget_low_s16(*q12s16);
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d25s16 = vget_high_s16(*q12s16);
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d26s16 = vget_low_s16(*q13s16);
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d27s16 = vget_high_s16(*q13s16);
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d28s16 = vget_low_s16(*q14s16);
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d29s16 = vget_high_s16(*q14s16);
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d30s16 = vget_low_s16(*q15s16);
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d31s16 = vget_high_s16(*q15s16);
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q2s32 = vmull_s16(d18s16, d0s16);
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q3s32 = vmull_s16(d19s16, d0s16);
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q5s32 = vmull_s16(d26s16, d2s16);
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q6s32 = vmull_s16(d27s16, d2s16);
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q2s32 = vmlsl_s16(q2s32, d30s16, d1s16);
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q3s32 = vmlsl_s16(q3s32, d31s16, d1s16);
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q5s32 = vmlsl_s16(q5s32, d22s16, d3s16);
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q6s32 = vmlsl_s16(q6s32, d23s16, d3s16);
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d8s16 = vqrshrn_n_s32(q2s32, 14);
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d9s16 = vqrshrn_n_s32(q3s32, 14);
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d10s16 = vqrshrn_n_s32(q5s32, 14);
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d11s16 = vqrshrn_n_s32(q6s32, 14);
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q4s16 = vcombine_s16(d8s16, d9s16);
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q5s16 = vcombine_s16(d10s16, d11s16);
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q2s32 = vmull_s16(d18s16, d1s16);
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q3s32 = vmull_s16(d19s16, d1s16);
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q9s32 = vmull_s16(d26s16, d3s16);
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q13s32 = vmull_s16(d27s16, d3s16);
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q2s32 = vmlal_s16(q2s32, d30s16, d0s16);
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q3s32 = vmlal_s16(q3s32, d31s16, d0s16);
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q9s32 = vmlal_s16(q9s32, d22s16, d2s16);
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q13s32 = vmlal_s16(q13s32, d23s16, d2s16);
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d14s16 = vqrshrn_n_s32(q2s32, 14);
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d15s16 = vqrshrn_n_s32(q3s32, 14);
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d12s16 = vqrshrn_n_s32(q9s32, 14);
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d13s16 = vqrshrn_n_s32(q13s32, 14);
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q6s16 = vcombine_s16(d12s16, d13s16);
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q7s16 = vcombine_s16(d14s16, d15s16);
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d0s16 = vdup_n_s16(cospi_16_64);
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q2s32 = vmull_s16(d16s16, d0s16);
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q3s32 = vmull_s16(d17s16, d0s16);
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q13s32 = vmull_s16(d16s16, d0s16);
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q15s32 = vmull_s16(d17s16, d0s16);
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q2s32 = vmlal_s16(q2s32, d24s16, d0s16);
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q3s32 = vmlal_s16(q3s32, d25s16, d0s16);
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q13s32 = vmlsl_s16(q13s32, d24s16, d0s16);
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q15s32 = vmlsl_s16(q15s32, d25s16, d0s16);
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d0s16 = vdup_n_s16(cospi_24_64);
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d1s16 = vdup_n_s16(cospi_8_64);
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d18s16 = vqrshrn_n_s32(q2s32, 14);
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d19s16 = vqrshrn_n_s32(q3s32, 14);
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d22s16 = vqrshrn_n_s32(q13s32, 14);
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d23s16 = vqrshrn_n_s32(q15s32, 14);
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*q9s16 = vcombine_s16(d18s16, d19s16);
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*q11s16 = vcombine_s16(d22s16, d23s16);
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q2s32 = vmull_s16(d20s16, d0s16);
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q3s32 = vmull_s16(d21s16, d0s16);
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q8s32 = vmull_s16(d20s16, d1s16);
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q12s32 = vmull_s16(d21s16, d1s16);
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q2s32 = vmlsl_s16(q2s32, d28s16, d1s16);
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q3s32 = vmlsl_s16(q3s32, d29s16, d1s16);
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q8s32 = vmlal_s16(q8s32, d28s16, d0s16);
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q12s32 = vmlal_s16(q12s32, d29s16, d0s16);
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d26s16 = vqrshrn_n_s32(q2s32, 14);
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d27s16 = vqrshrn_n_s32(q3s32, 14);
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d30s16 = vqrshrn_n_s32(q8s32, 14);
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d31s16 = vqrshrn_n_s32(q12s32, 14);
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*q13s16 = vcombine_s16(d26s16, d27s16);
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*q15s16 = vcombine_s16(d30s16, d31s16);
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q0s16 = vaddq_s16(*q9s16, *q15s16);
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q1s16 = vaddq_s16(*q11s16, *q13s16);
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q2s16 = vsubq_s16(*q11s16, *q13s16);
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q3s16 = vsubq_s16(*q9s16, *q15s16);
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*q13s16 = vsubq_s16(q4s16, q5s16);
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q4s16 = vaddq_s16(q4s16, q5s16);
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*q14s16 = vsubq_s16(q7s16, q6s16);
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q7s16 = vaddq_s16(q7s16, q6s16);
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d26s16 = vget_low_s16(*q13s16);
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d27s16 = vget_high_s16(*q13s16);
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d28s16 = vget_low_s16(*q14s16);
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d29s16 = vget_high_s16(*q14s16);
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d16s16 = vdup_n_s16(cospi_16_64);
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q9s32 = vmull_s16(d28s16, d16s16);
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q10s32 = vmull_s16(d29s16, d16s16);
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q11s32 = vmull_s16(d28s16, d16s16);
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q12s32 = vmull_s16(d29s16, d16s16);
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q9s32 = vmlsl_s16(q9s32, d26s16, d16s16);
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q10s32 = vmlsl_s16(q10s32, d27s16, d16s16);
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q11s32 = vmlal_s16(q11s32, d26s16, d16s16);
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q12s32 = vmlal_s16(q12s32, d27s16, d16s16);
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d10s16 = vqrshrn_n_s32(q9s32, 14);
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d11s16 = vqrshrn_n_s32(q10s32, 14);
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d12s16 = vqrshrn_n_s32(q11s32, 14);
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d13s16 = vqrshrn_n_s32(q12s32, 14);
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q5s16 = vcombine_s16(d10s16, d11s16);
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q6s16 = vcombine_s16(d12s16, d13s16);
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*q8s16 = vaddq_s16(q0s16, q7s16);
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*q9s16 = vaddq_s16(q1s16, q6s16);
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*q10s16 = vaddq_s16(q2s16, q5s16);
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*q11s16 = vaddq_s16(q3s16, q4s16);
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*q12s16 = vsubq_s16(q3s16, q4s16);
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*q13s16 = vsubq_s16(q2s16, q5s16);
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*q14s16 = vsubq_s16(q1s16, q6s16);
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*q15s16 = vsubq_s16(q0s16, q7s16);
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return;
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}
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void vp9_idct8x8_64_add_neon(
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int16_t *input,
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uint8_t *dest,
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int dest_stride) {
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uint8_t *d1, *d2;
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uint8x8_t d0u8, d1u8, d2u8, d3u8;
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uint64x1_t d0u64, d1u64, d2u64, d3u64;
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int16x8_t q8s16, q9s16, q10s16, q11s16, q12s16, q13s16, q14s16, q15s16;
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uint16x8_t q8u16, q9u16, q10u16, q11u16;
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q8s16 = vld1q_s16(input);
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q9s16 = vld1q_s16(input + 8);
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q10s16 = vld1q_s16(input + 16);
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q11s16 = vld1q_s16(input + 24);
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q12s16 = vld1q_s16(input + 32);
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q13s16 = vld1q_s16(input + 40);
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q14s16 = vld1q_s16(input + 48);
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q15s16 = vld1q_s16(input + 56);
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TRANSPOSE8X8(&q8s16, &q9s16, &q10s16, &q11s16,
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&q12s16, &q13s16, &q14s16, &q15s16);
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IDCT8x8_1D(&q8s16, &q9s16, &q10s16, &q11s16,
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&q12s16, &q13s16, &q14s16, &q15s16);
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TRANSPOSE8X8(&q8s16, &q9s16, &q10s16, &q11s16,
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&q12s16, &q13s16, &q14s16, &q15s16);
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IDCT8x8_1D(&q8s16, &q9s16, &q10s16, &q11s16,
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&q12s16, &q13s16, &q14s16, &q15s16);
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q8s16 = vrshrq_n_s16(q8s16, 5);
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q9s16 = vrshrq_n_s16(q9s16, 5);
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q10s16 = vrshrq_n_s16(q10s16, 5);
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q11s16 = vrshrq_n_s16(q11s16, 5);
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q12s16 = vrshrq_n_s16(q12s16, 5);
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q13s16 = vrshrq_n_s16(q13s16, 5);
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q14s16 = vrshrq_n_s16(q14s16, 5);
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q15s16 = vrshrq_n_s16(q15s16, 5);
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d1 = d2 = dest;
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d0u64 = vld1_u64((uint64_t *)d1);
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d1 += dest_stride;
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d1u64 = vld1_u64((uint64_t *)d1);
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d1 += dest_stride;
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d2u64 = vld1_u64((uint64_t *)d1);
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d1 += dest_stride;
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d3u64 = vld1_u64((uint64_t *)d1);
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d1 += dest_stride;
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q8u16 = vaddw_u8(vreinterpretq_u16_s16(q8s16),
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vreinterpret_u8_u64(d0u64));
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q9u16 = vaddw_u8(vreinterpretq_u16_s16(q9s16),
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vreinterpret_u8_u64(d1u64));
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q10u16 = vaddw_u8(vreinterpretq_u16_s16(q10s16),
|
||||
vreinterpret_u8_u64(d2u64));
|
||||
q11u16 = vaddw_u8(vreinterpretq_u16_s16(q11s16),
|
||||
vreinterpret_u8_u64(d3u64));
|
||||
|
||||
d0u8 = vqmovun_s16(vreinterpretq_s16_u16(q8u16));
|
||||
d1u8 = vqmovun_s16(vreinterpretq_s16_u16(q9u16));
|
||||
d2u8 = vqmovun_s16(vreinterpretq_s16_u16(q10u16));
|
||||
d3u8 = vqmovun_s16(vreinterpretq_s16_u16(q11u16));
|
||||
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d0u8));
|
||||
d2 += dest_stride;
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d1u8));
|
||||
d2 += dest_stride;
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d2u8));
|
||||
d2 += dest_stride;
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d3u8));
|
||||
d2 += dest_stride;
|
||||
|
||||
q8s16 = q12s16;
|
||||
q9s16 = q13s16;
|
||||
q10s16 = q14s16;
|
||||
q11s16 = q15s16;
|
||||
|
||||
d0u64 = vld1_u64((uint64_t *)d1);
|
||||
d1 += dest_stride;
|
||||
d1u64 = vld1_u64((uint64_t *)d1);
|
||||
d1 += dest_stride;
|
||||
d2u64 = vld1_u64((uint64_t *)d1);
|
||||
d1 += dest_stride;
|
||||
d3u64 = vld1_u64((uint64_t *)d1);
|
||||
d1 += dest_stride;
|
||||
|
||||
q8u16 = vaddw_u8(vreinterpretq_u16_s16(q8s16),
|
||||
vreinterpret_u8_u64(d0u64));
|
||||
q9u16 = vaddw_u8(vreinterpretq_u16_s16(q9s16),
|
||||
vreinterpret_u8_u64(d1u64));
|
||||
q10u16 = vaddw_u8(vreinterpretq_u16_s16(q10s16),
|
||||
vreinterpret_u8_u64(d2u64));
|
||||
q11u16 = vaddw_u8(vreinterpretq_u16_s16(q11s16),
|
||||
vreinterpret_u8_u64(d3u64));
|
||||
|
||||
d0u8 = vqmovun_s16(vreinterpretq_s16_u16(q8u16));
|
||||
d1u8 = vqmovun_s16(vreinterpretq_s16_u16(q9u16));
|
||||
d2u8 = vqmovun_s16(vreinterpretq_s16_u16(q10u16));
|
||||
d3u8 = vqmovun_s16(vreinterpretq_s16_u16(q11u16));
|
||||
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d0u8));
|
||||
d2 += dest_stride;
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d1u8));
|
||||
d2 += dest_stride;
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d2u8));
|
||||
d2 += dest_stride;
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d3u8));
|
||||
d2 += dest_stride;
|
||||
return;
|
||||
}
|
||||
|
||||
void vp9_idct8x8_12_add_neon(
|
||||
int16_t *input,
|
||||
uint8_t *dest,
|
||||
int dest_stride) {
|
||||
uint8_t *d1, *d2;
|
||||
uint8x8_t d0u8, d1u8, d2u8, d3u8;
|
||||
int16x4_t d10s16, d11s16, d12s16, d13s16, d16s16;
|
||||
int16x4_t d26s16, d27s16, d28s16, d29s16;
|
||||
uint64x1_t d0u64, d1u64, d2u64, d3u64;
|
||||
int16x8_t q0s16, q1s16, q2s16, q3s16, q4s16, q5s16, q6s16, q7s16;
|
||||
int16x8_t q8s16, q9s16, q10s16, q11s16, q12s16, q13s16, q14s16, q15s16;
|
||||
uint16x8_t q8u16, q9u16, q10u16, q11u16;
|
||||
int32x4_t q9s32, q10s32, q11s32, q12s32;
|
||||
|
||||
q8s16 = vld1q_s16(input);
|
||||
q9s16 = vld1q_s16(input + 8);
|
||||
q10s16 = vld1q_s16(input + 16);
|
||||
q11s16 = vld1q_s16(input + 24);
|
||||
q12s16 = vld1q_s16(input + 32);
|
||||
q13s16 = vld1q_s16(input + 40);
|
||||
q14s16 = vld1q_s16(input + 48);
|
||||
q15s16 = vld1q_s16(input + 56);
|
||||
|
||||
TRANSPOSE8X8(&q8s16, &q9s16, &q10s16, &q11s16,
|
||||
&q12s16, &q13s16, &q14s16, &q15s16);
|
||||
|
||||
// First transform rows
|
||||
// stage 1
|
||||
q0s16 = vdupq_n_s16(cospi_28_64 * 2);
|
||||
q1s16 = vdupq_n_s16(cospi_4_64 * 2);
|
||||
|
||||
q4s16 = vqrdmulhq_s16(q9s16, q0s16);
|
||||
|
||||
q0s16 = vdupq_n_s16(-cospi_20_64 * 2);
|
||||
|
||||
q7s16 = vqrdmulhq_s16(q9s16, q1s16);
|
||||
|
||||
q1s16 = vdupq_n_s16(cospi_12_64 * 2);
|
||||
|
||||
q5s16 = vqrdmulhq_s16(q11s16, q0s16);
|
||||
|
||||
q0s16 = vdupq_n_s16(cospi_16_64 * 2);
|
||||
|
||||
q6s16 = vqrdmulhq_s16(q11s16, q1s16);
|
||||
|
||||
// stage 2 & stage 3 - even half
|
||||
q1s16 = vdupq_n_s16(cospi_24_64 * 2);
|
||||
|
||||
q9s16 = vqrdmulhq_s16(q8s16, q0s16);
|
||||
|
||||
q0s16 = vdupq_n_s16(cospi_8_64 * 2);
|
||||
|
||||
q13s16 = vqrdmulhq_s16(q10s16, q1s16);
|
||||
|
||||
q15s16 = vqrdmulhq_s16(q10s16, q0s16);
|
||||
|
||||
// stage 3 -odd half
|
||||
q0s16 = vaddq_s16(q9s16, q15s16);
|
||||
q1s16 = vaddq_s16(q9s16, q13s16);
|
||||
q2s16 = vsubq_s16(q9s16, q13s16);
|
||||
q3s16 = vsubq_s16(q9s16, q15s16);
|
||||
|
||||
// stage 2 - odd half
|
||||
q13s16 = vsubq_s16(q4s16, q5s16);
|
||||
q4s16 = vaddq_s16(q4s16, q5s16);
|
||||
q14s16 = vsubq_s16(q7s16, q6s16);
|
||||
q7s16 = vaddq_s16(q7s16, q6s16);
|
||||
d26s16 = vget_low_s16(q13s16);
|
||||
d27s16 = vget_high_s16(q13s16);
|
||||
d28s16 = vget_low_s16(q14s16);
|
||||
d29s16 = vget_high_s16(q14s16);
|
||||
|
||||
d16s16 = vdup_n_s16(cospi_16_64);
|
||||
q9s32 = vmull_s16(d28s16, d16s16);
|
||||
q10s32 = vmull_s16(d29s16, d16s16);
|
||||
q11s32 = vmull_s16(d28s16, d16s16);
|
||||
q12s32 = vmull_s16(d29s16, d16s16);
|
||||
|
||||
q9s32 = vmlsl_s16(q9s32, d26s16, d16s16);
|
||||
q10s32 = vmlsl_s16(q10s32, d27s16, d16s16);
|
||||
q11s32 = vmlal_s16(q11s32, d26s16, d16s16);
|
||||
q12s32 = vmlal_s16(q12s32, d27s16, d16s16);
|
||||
|
||||
d10s16 = vqrshrn_n_s32(q9s32, 14);
|
||||
d11s16 = vqrshrn_n_s32(q10s32, 14);
|
||||
d12s16 = vqrshrn_n_s32(q11s32, 14);
|
||||
d13s16 = vqrshrn_n_s32(q12s32, 14);
|
||||
q5s16 = vcombine_s16(d10s16, d11s16);
|
||||
q6s16 = vcombine_s16(d12s16, d13s16);
|
||||
|
||||
// stage 4
|
||||
q8s16 = vaddq_s16(q0s16, q7s16);
|
||||
q9s16 = vaddq_s16(q1s16, q6s16);
|
||||
q10s16 = vaddq_s16(q2s16, q5s16);
|
||||
q11s16 = vaddq_s16(q3s16, q4s16);
|
||||
q12s16 = vsubq_s16(q3s16, q4s16);
|
||||
q13s16 = vsubq_s16(q2s16, q5s16);
|
||||
q14s16 = vsubq_s16(q1s16, q6s16);
|
||||
q15s16 = vsubq_s16(q0s16, q7s16);
|
||||
|
||||
TRANSPOSE8X8(&q8s16, &q9s16, &q10s16, &q11s16,
|
||||
&q12s16, &q13s16, &q14s16, &q15s16);
|
||||
|
||||
IDCT8x8_1D(&q8s16, &q9s16, &q10s16, &q11s16,
|
||||
&q12s16, &q13s16, &q14s16, &q15s16);
|
||||
|
||||
q8s16 = vrshrq_n_s16(q8s16, 5);
|
||||
q9s16 = vrshrq_n_s16(q9s16, 5);
|
||||
q10s16 = vrshrq_n_s16(q10s16, 5);
|
||||
q11s16 = vrshrq_n_s16(q11s16, 5);
|
||||
q12s16 = vrshrq_n_s16(q12s16, 5);
|
||||
q13s16 = vrshrq_n_s16(q13s16, 5);
|
||||
q14s16 = vrshrq_n_s16(q14s16, 5);
|
||||
q15s16 = vrshrq_n_s16(q15s16, 5);
|
||||
|
||||
d1 = d2 = dest;
|
||||
|
||||
d0u64 = vld1_u64((uint64_t *)d1);
|
||||
d1 += dest_stride;
|
||||
d1u64 = vld1_u64((uint64_t *)d1);
|
||||
d1 += dest_stride;
|
||||
d2u64 = vld1_u64((uint64_t *)d1);
|
||||
d1 += dest_stride;
|
||||
d3u64 = vld1_u64((uint64_t *)d1);
|
||||
d1 += dest_stride;
|
||||
|
||||
q8u16 = vaddw_u8(vreinterpretq_u16_s16(q8s16),
|
||||
vreinterpret_u8_u64(d0u64));
|
||||
q9u16 = vaddw_u8(vreinterpretq_u16_s16(q9s16),
|
||||
vreinterpret_u8_u64(d1u64));
|
||||
q10u16 = vaddw_u8(vreinterpretq_u16_s16(q10s16),
|
||||
vreinterpret_u8_u64(d2u64));
|
||||
q11u16 = vaddw_u8(vreinterpretq_u16_s16(q11s16),
|
||||
vreinterpret_u8_u64(d3u64));
|
||||
|
||||
d0u8 = vqmovun_s16(vreinterpretq_s16_u16(q8u16));
|
||||
d1u8 = vqmovun_s16(vreinterpretq_s16_u16(q9u16));
|
||||
d2u8 = vqmovun_s16(vreinterpretq_s16_u16(q10u16));
|
||||
d3u8 = vqmovun_s16(vreinterpretq_s16_u16(q11u16));
|
||||
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d0u8));
|
||||
d2 += dest_stride;
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d1u8));
|
||||
d2 += dest_stride;
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d2u8));
|
||||
d2 += dest_stride;
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d3u8));
|
||||
d2 += dest_stride;
|
||||
|
||||
q8s16 = q12s16;
|
||||
q9s16 = q13s16;
|
||||
q10s16 = q14s16;
|
||||
q11s16 = q15s16;
|
||||
|
||||
d0u64 = vld1_u64((uint64_t *)d1);
|
||||
d1 += dest_stride;
|
||||
d1u64 = vld1_u64((uint64_t *)d1);
|
||||
d1 += dest_stride;
|
||||
d2u64 = vld1_u64((uint64_t *)d1);
|
||||
d1 += dest_stride;
|
||||
d3u64 = vld1_u64((uint64_t *)d1);
|
||||
d1 += dest_stride;
|
||||
|
||||
q8u16 = vaddw_u8(vreinterpretq_u16_s16(q8s16),
|
||||
vreinterpret_u8_u64(d0u64));
|
||||
q9u16 = vaddw_u8(vreinterpretq_u16_s16(q9s16),
|
||||
vreinterpret_u8_u64(d1u64));
|
||||
q10u16 = vaddw_u8(vreinterpretq_u16_s16(q10s16),
|
||||
vreinterpret_u8_u64(d2u64));
|
||||
q11u16 = vaddw_u8(vreinterpretq_u16_s16(q11s16),
|
||||
vreinterpret_u8_u64(d3u64));
|
||||
|
||||
d0u8 = vqmovun_s16(vreinterpretq_s16_u16(q8u16));
|
||||
d1u8 = vqmovun_s16(vreinterpretq_s16_u16(q9u16));
|
||||
d2u8 = vqmovun_s16(vreinterpretq_s16_u16(q10u16));
|
||||
d3u8 = vqmovun_s16(vreinterpretq_s16_u16(q11u16));
|
||||
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d0u8));
|
||||
d2 += dest_stride;
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d1u8));
|
||||
d2 += dest_stride;
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d2u8));
|
||||
d2 += dest_stride;
|
||||
vst1_u64((uint64_t *)d2, vreinterpret_u64_u8(d3u8));
|
||||
d2 += dest_stride;
|
||||
return;
|
||||
}
|
||||
|
|
@ -431,12 +431,10 @@ if (vpx_config("CONFIG_VP9_HIGHBITDEPTH") eq "yes") {
|
|||
specialize qw/vp9_idct8x8_1_add sse2 neon dspr2/;
|
||||
|
||||
add_proto qw/void vp9_idct8x8_64_add/, "const tran_low_t *input, uint8_t *dest, int dest_stride";
|
||||
specialize qw/vp9_idct8x8_64_add sse2 neon_asm dspr2/, "$ssse3_x86_64";
|
||||
$vp9_idct8x8_64_add_neon_asm=vp9_idct8x8_64_add_neon;
|
||||
specialize qw/vp9_idct8x8_64_add sse2 neon dspr2/, "$ssse3_x86_64";
|
||||
|
||||
add_proto qw/void vp9_idct8x8_12_add/, "const tran_low_t *input, uint8_t *dest, int dest_stride";
|
||||
specialize qw/vp9_idct8x8_12_add sse2 neon_asm dspr2/, "$ssse3_x86_64";
|
||||
$vp9_idct8x8_12_add_neon_asm=vp9_idct8x8_12_add_neon;
|
||||
specialize qw/vp9_idct8x8_12_add sse2 neon dspr2/, "$ssse3_x86_64";
|
||||
|
||||
add_proto qw/void vp9_idct16x16_1_add/, "const tran_low_t *input, uint8_t *dest, int dest_stride";
|
||||
specialize qw/vp9_idct16x16_1_add sse2 neon dspr2/;
|
||||
|
|
|
|||
|
|
@ -134,7 +134,6 @@ endif
|
|||
VP9_COMMON_SRCS-$(HAVE_NEON_ASM) += common/arm/neon/vp9_idct16x16_neon.c
|
||||
VP9_COMMON_SRCS-$(HAVE_NEON_ASM) += common/arm/neon/vp9_loopfilter_16_neon_asm$(ASM)
|
||||
VP9_COMMON_SRCS-$(HAVE_NEON_ASM) += common/arm/neon/vp9_dc_only_idct_add_neon$(ASM)
|
||||
VP9_COMMON_SRCS-$(HAVE_NEON_ASM) += common/arm/neon/vp9_idct8x8_add_neon$(ASM)
|
||||
VP9_COMMON_SRCS-$(HAVE_NEON_ASM) += common/arm/neon/vp9_idct16x16_add_neon$(ASM)
|
||||
VP9_COMMON_SRCS-$(HAVE_NEON_ASM) += common/arm/neon/vp9_idct32x32_add_neon$(ASM)
|
||||
VP9_COMMON_SRCS-$(HAVE_NEON_ASM) += common/arm/neon/vp9_iht4x4_add_neon$(ASM)
|
||||
|
|
@ -156,6 +155,7 @@ VP9_COMMON_SRCS-yes += common/arm/neon/vp9_idct32x32_1_add_neon_asm$(ASM)
|
|||
VP9_COMMON_SRCS-yes += common/arm/neon/vp9_idct4x4_1_add_neon_asm$(ASM)
|
||||
VP9_COMMON_SRCS-yes += common/arm/neon/vp9_idct4x4_add_neon_asm$(ASM)
|
||||
VP9_COMMON_SRCS-yes += common/arm/neon/vp9_idct8x8_1_add_neon_asm$(ASM)
|
||||
VP9_COMMON_SRCS-yes += common/arm/neon/vp9_idct8x8_add_neon_asm$(ASM)
|
||||
VP9_COMMON_SRCS-yes += common/arm/neon/vp9_loopfilter_neon_asm$(ASM)
|
||||
VP9_COMMON_SRCS-yes += common/arm/neon/vp9_loopfilter_16_neon.c
|
||||
else
|
||||
|
|
@ -170,6 +170,7 @@ VP9_COMMON_SRCS-yes += common/arm/neon/vp9_idct32x32_1_add_neon.c
|
|||
VP9_COMMON_SRCS-yes += common/arm/neon/vp9_idct4x4_1_add_neon.c
|
||||
VP9_COMMON_SRCS-yes += common/arm/neon/vp9_idct4x4_add_neon.c
|
||||
VP9_COMMON_SRCS-yes += common/arm/neon/vp9_idct8x8_1_add_neon.c
|
||||
VP9_COMMON_SRCS-yes += common/arm/neon/vp9_idct8x8_add_neon.c
|
||||
VP9_COMMON_SRCS-yes += common/arm/neon/vp9_loopfilter_neon.c
|
||||
VP9_COMMON_SRCS-yes += common/arm/neon/vp9_loopfilter_16_neon.c
|
||||
endif # HAVE_NEON
|
||||
|
|
|
|||
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