Added vp9_fdct8x8_neon(), vp9_fdct8x8_1_neon()
On a Nexus 7, vpxenc (in realtime mode, speed -12) reported a performance improvement of ~3.7%. Change-Id: I428c72c40df82c6d537955e320a8debf99343004
This commit is contained in:
Scott LaVarnway
Родитель
4ba92dc5ab
Коммит
d19d222db6
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@ -337,7 +337,7 @@ INSTANTIATE_TEST_CASE_P(
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INSTANTIATE_TEST_CASE_P(
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NEON, FwdTrans8x8DCT,
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::testing::Values(
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make_tuple(&vp9_fdct8x8_c, &vp9_idct8x8_64_add_neon, 0)));
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make_tuple(&vp9_fdct8x8_neon, &vp9_idct8x8_64_add_neon, 0)));
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INSTANTIATE_TEST_CASE_P(
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DISABLED_NEON, FwdTrans8x8HT,
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::testing::Values(
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@ -757,10 +757,10 @@ add_proto qw/void vp9_fdct4x4/, "const int16_t *input, int16_t *output, int stri
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specialize qw/vp9_fdct4x4 sse2/;
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add_proto qw/void vp9_fdct8x8_1/, "const int16_t *input, int16_t *output, int stride";
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specialize qw/vp9_fdct8x8_1 sse2/;
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specialize qw/vp9_fdct8x8_1 sse2 neon/;
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add_proto qw/void vp9_fdct8x8/, "const int16_t *input, int16_t *output, int stride";
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specialize qw/vp9_fdct8x8 sse2/, "$ssse3_x86_64";
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specialize qw/vp9_fdct8x8 sse2 neon/, "$ssse3_x86_64";
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add_proto qw/void vp9_fdct16x16_1/, "const int16_t *input, int16_t *output, int stride";
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specialize qw/vp9_fdct16x16_1 sse2/;
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@ -0,0 +1,223 @@
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/*
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* Copyright (c) 2014 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include <arm_neon.h>
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#include "./vp9_rtcd.h"
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#include "./vpx_config.h"
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#include "vp9/common/vp9_blockd.h"
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#include "vp9/common/vp9_idct.h"
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void vp9_fdct8x8_1_neon(const int16_t *input, int16_t *output, int stride) {
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int r;
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int16x8_t sum = vld1q_s16(&input[0]);
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for (r = 1; r < 8; ++r) {
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const int16x8_t input_00 = vld1q_s16(&input[r * stride]);
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sum = vaddq_s16(sum, input_00);
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}
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{
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const int32x4_t a = vpaddlq_s16(sum);
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const int64x2_t b = vpaddlq_s32(a);
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const int32x2_t c = vadd_s32(vreinterpret_s32_s64(vget_low_s64(b)),
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vreinterpret_s32_s64(vget_high_s64(b)));
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output[0] = vget_lane_s16(vreinterpret_s16_s32(c), 0);
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output[1] = 0;
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}
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}
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void vp9_fdct8x8_neon(const int16_t *input, int16_t *final_output, int stride) {
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int i;
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// stage 1
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int16x8_t input_0 = vshlq_n_s16(vld1q_s16(&input[0 * stride]), 2);
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int16x8_t input_1 = vshlq_n_s16(vld1q_s16(&input[1 * stride]), 2);
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int16x8_t input_2 = vshlq_n_s16(vld1q_s16(&input[2 * stride]), 2);
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int16x8_t input_3 = vshlq_n_s16(vld1q_s16(&input[3 * stride]), 2);
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int16x8_t input_4 = vshlq_n_s16(vld1q_s16(&input[4 * stride]), 2);
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int16x8_t input_5 = vshlq_n_s16(vld1q_s16(&input[5 * stride]), 2);
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int16x8_t input_6 = vshlq_n_s16(vld1q_s16(&input[6 * stride]), 2);
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int16x8_t input_7 = vshlq_n_s16(vld1q_s16(&input[7 * stride]), 2);
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for (i = 0; i < 2; ++i) {
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int16x8_t out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7;
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const int16x8_t v_s0 = vaddq_s16(input_0, input_7);
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const int16x8_t v_s1 = vaddq_s16(input_1, input_6);
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const int16x8_t v_s2 = vaddq_s16(input_2, input_5);
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const int16x8_t v_s3 = vaddq_s16(input_3, input_4);
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const int16x8_t v_s4 = vsubq_s16(input_3, input_4);
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const int16x8_t v_s5 = vsubq_s16(input_2, input_5);
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const int16x8_t v_s6 = vsubq_s16(input_1, input_6);
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const int16x8_t v_s7 = vsubq_s16(input_0, input_7);
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// fdct4(step, step);
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int16x8_t v_x0 = vaddq_s16(v_s0, v_s3);
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int16x8_t v_x1 = vaddq_s16(v_s1, v_s2);
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int16x8_t v_x2 = vsubq_s16(v_s1, v_s2);
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int16x8_t v_x3 = vsubq_s16(v_s0, v_s3);
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// fdct4(step, step);
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int32x4_t v_t0_lo = vaddl_s16(vget_low_s16(v_x0), vget_low_s16(v_x1));
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int32x4_t v_t0_hi = vaddl_s16(vget_high_s16(v_x0), vget_high_s16(v_x1));
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int32x4_t v_t1_lo = vsubl_s16(vget_low_s16(v_x0), vget_low_s16(v_x1));
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int32x4_t v_t1_hi = vsubl_s16(vget_high_s16(v_x0), vget_high_s16(v_x1));
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int32x4_t v_t2_lo = vmull_n_s16(vget_low_s16(v_x2), (int16_t)cospi_24_64);
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int32x4_t v_t2_hi = vmull_n_s16(vget_high_s16(v_x2), (int16_t)cospi_24_64);
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int32x4_t v_t3_lo = vmull_n_s16(vget_low_s16(v_x3), (int16_t)cospi_24_64);
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int32x4_t v_t3_hi = vmull_n_s16(vget_high_s16(v_x3), (int16_t)cospi_24_64);
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v_t2_lo = vmlal_n_s16(v_t2_lo, vget_low_s16(v_x3), (int16_t)cospi_8_64);
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v_t2_hi = vmlal_n_s16(v_t2_hi, vget_high_s16(v_x3), (int16_t)cospi_8_64);
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v_t3_lo = vmlsl_n_s16(v_t3_lo, vget_low_s16(v_x2), (int16_t)cospi_8_64);
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v_t3_hi = vmlsl_n_s16(v_t3_hi, vget_high_s16(v_x2), (int16_t)cospi_8_64);
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v_t0_lo = vmulq_n_s32(v_t0_lo, cospi_16_64);
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v_t0_hi = vmulq_n_s32(v_t0_hi, cospi_16_64);
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v_t1_lo = vmulq_n_s32(v_t1_lo, cospi_16_64);
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v_t1_hi = vmulq_n_s32(v_t1_hi, cospi_16_64);
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{
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const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS);
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const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS);
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const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS);
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const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS);
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const int16x4_t e = vrshrn_n_s32(v_t2_lo, DCT_CONST_BITS);
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const int16x4_t f = vrshrn_n_s32(v_t2_hi, DCT_CONST_BITS);
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const int16x4_t g = vrshrn_n_s32(v_t3_lo, DCT_CONST_BITS);
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const int16x4_t h = vrshrn_n_s32(v_t3_hi, DCT_CONST_BITS);
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out_0 = vcombine_s16(a, c); // 00 01 02 03 40 41 42 43
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out_2 = vcombine_s16(e, g); // 20 21 22 23 60 61 62 63
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out_4 = vcombine_s16(b, d); // 04 05 06 07 44 45 46 47
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out_6 = vcombine_s16(f, h); // 24 25 26 27 64 65 66 67
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}
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// Stage 2
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v_x0 = vsubq_s16(v_s6, v_s5);
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v_x1 = vaddq_s16(v_s6, v_s5);
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v_t0_lo = vmull_n_s16(vget_low_s16(v_x0), (int16_t)cospi_16_64);
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v_t0_hi = vmull_n_s16(vget_high_s16(v_x0), (int16_t)cospi_16_64);
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v_t1_lo = vmull_n_s16(vget_low_s16(v_x1), (int16_t)cospi_16_64);
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v_t1_hi = vmull_n_s16(vget_high_s16(v_x1), (int16_t)cospi_16_64);
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{
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const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS);
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const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS);
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const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS);
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const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS);
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const int16x8_t ab = vcombine_s16(a, b);
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const int16x8_t cd = vcombine_s16(c, d);
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// Stage 3
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v_x0 = vaddq_s16(v_s4, ab);
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v_x1 = vsubq_s16(v_s4, ab);
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v_x2 = vsubq_s16(v_s7, cd);
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v_x3 = vaddq_s16(v_s7, cd);
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}
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// Stage 4
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v_t0_lo = vmull_n_s16(vget_low_s16(v_x3), (int16_t)cospi_4_64);
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v_t0_hi = vmull_n_s16(vget_high_s16(v_x3), (int16_t)cospi_4_64);
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v_t0_lo = vmlal_n_s16(v_t0_lo, vget_low_s16(v_x0), (int16_t)cospi_28_64);
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v_t0_hi = vmlal_n_s16(v_t0_hi, vget_high_s16(v_x0), (int16_t)cospi_28_64);
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v_t1_lo = vmull_n_s16(vget_low_s16(v_x1), (int16_t)cospi_12_64);
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v_t1_hi = vmull_n_s16(vget_high_s16(v_x1), (int16_t)cospi_12_64);
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v_t1_lo = vmlal_n_s16(v_t1_lo, vget_low_s16(v_x2), (int16_t)cospi_20_64);
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v_t1_hi = vmlal_n_s16(v_t1_hi, vget_high_s16(v_x2), (int16_t)cospi_20_64);
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v_t2_lo = vmull_n_s16(vget_low_s16(v_x2), (int16_t)cospi_12_64);
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v_t2_hi = vmull_n_s16(vget_high_s16(v_x2), (int16_t)cospi_12_64);
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v_t2_lo = vmlsl_n_s16(v_t2_lo, vget_low_s16(v_x1), (int16_t)cospi_20_64);
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v_t2_hi = vmlsl_n_s16(v_t2_hi, vget_high_s16(v_x1), (int16_t)cospi_20_64);
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v_t3_lo = vmull_n_s16(vget_low_s16(v_x3), (int16_t)cospi_28_64);
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v_t3_hi = vmull_n_s16(vget_high_s16(v_x3), (int16_t)cospi_28_64);
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v_t3_lo = vmlsl_n_s16(v_t3_lo, vget_low_s16(v_x0), (int16_t)cospi_4_64);
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v_t3_hi = vmlsl_n_s16(v_t3_hi, vget_high_s16(v_x0), (int16_t)cospi_4_64);
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{
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const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS);
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const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS);
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const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS);
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const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS);
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const int16x4_t e = vrshrn_n_s32(v_t2_lo, DCT_CONST_BITS);
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const int16x4_t f = vrshrn_n_s32(v_t2_hi, DCT_CONST_BITS);
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const int16x4_t g = vrshrn_n_s32(v_t3_lo, DCT_CONST_BITS);
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const int16x4_t h = vrshrn_n_s32(v_t3_hi, DCT_CONST_BITS);
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out_1 = vcombine_s16(a, c); // 10 11 12 13 50 51 52 53
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out_3 = vcombine_s16(e, g); // 30 31 32 33 70 71 72 73
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out_5 = vcombine_s16(b, d); // 14 15 16 17 54 55 56 57
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out_7 = vcombine_s16(f, h); // 34 35 36 37 74 75 76 77
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}
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// transpose 8x8
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{
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// 00 01 02 03 40 41 42 43
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// 10 11 12 13 50 51 52 53
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// 20 21 22 23 60 61 62 63
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// 30 31 32 33 70 71 72 73
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// 04 05 06 07 44 45 46 47
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// 14 15 16 17 54 55 56 57
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// 24 25 26 27 64 65 66 67
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// 34 35 36 37 74 75 76 77
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const int32x4x2_t r02_s32 = vtrnq_s32(vreinterpretq_s32_s16(out_0),
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vreinterpretq_s32_s16(out_2));
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const int32x4x2_t r13_s32 = vtrnq_s32(vreinterpretq_s32_s16(out_1),
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vreinterpretq_s32_s16(out_3));
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const int32x4x2_t r46_s32 = vtrnq_s32(vreinterpretq_s32_s16(out_4),
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vreinterpretq_s32_s16(out_6));
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const int32x4x2_t r57_s32 = vtrnq_s32(vreinterpretq_s32_s16(out_5),
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vreinterpretq_s32_s16(out_7));
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const int16x8x2_t r01_s16 =
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vtrnq_s16(vreinterpretq_s16_s32(r02_s32.val[0]),
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vreinterpretq_s16_s32(r13_s32.val[0]));
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const int16x8x2_t r23_s16 =
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vtrnq_s16(vreinterpretq_s16_s32(r02_s32.val[1]),
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vreinterpretq_s16_s32(r13_s32.val[1]));
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const int16x8x2_t r45_s16 =
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vtrnq_s16(vreinterpretq_s16_s32(r46_s32.val[0]),
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vreinterpretq_s16_s32(r57_s32.val[0]));
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const int16x8x2_t r67_s16 =
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vtrnq_s16(vreinterpretq_s16_s32(r46_s32.val[1]),
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vreinterpretq_s16_s32(r57_s32.val[1]));
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input_0 = r01_s16.val[0];
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input_1 = r01_s16.val[1];
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input_2 = r23_s16.val[0];
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input_3 = r23_s16.val[1];
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input_4 = r45_s16.val[0];
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input_5 = r45_s16.val[1];
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input_6 = r67_s16.val[0];
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input_7 = r67_s16.val[1];
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// 00 10 20 30 40 50 60 70
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// 01 11 21 31 41 51 61 71
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// 02 12 22 32 42 52 62 72
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// 03 13 23 33 43 53 63 73
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// 04 14 24 34 44 54 64 74
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// 05 15 25 35 45 55 65 75
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// 06 16 26 36 46 56 66 76
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// 07 17 27 37 47 57 67 77
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}
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} // for
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{
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// from vp9_dct_sse2.c
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// Post-condition (division by two)
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// division of two 16 bits signed numbers using shifts
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// n / 2 = (n - (n >> 15)) >> 1
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const int16x8_t sign_in0 = vshrq_n_s16(input_0, 15);
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const int16x8_t sign_in1 = vshrq_n_s16(input_1, 15);
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const int16x8_t sign_in2 = vshrq_n_s16(input_2, 15);
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const int16x8_t sign_in3 = vshrq_n_s16(input_3, 15);
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const int16x8_t sign_in4 = vshrq_n_s16(input_4, 15);
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const int16x8_t sign_in5 = vshrq_n_s16(input_5, 15);
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const int16x8_t sign_in6 = vshrq_n_s16(input_6, 15);
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const int16x8_t sign_in7 = vshrq_n_s16(input_7, 15);
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input_0 = vhsubq_s16(input_0, sign_in0);
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input_1 = vhsubq_s16(input_1, sign_in1);
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input_2 = vhsubq_s16(input_2, sign_in2);
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input_3 = vhsubq_s16(input_3, sign_in3);
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input_4 = vhsubq_s16(input_4, sign_in4);
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input_5 = vhsubq_s16(input_5, sign_in5);
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input_6 = vhsubq_s16(input_6, sign_in6);
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input_7 = vhsubq_s16(input_7, sign_in7);
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// store results
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vst1q_s16(&final_output[0 * 8], input_0);
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vst1q_s16(&final_output[1 * 8], input_1);
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vst1q_s16(&final_output[2 * 8], input_2);
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vst1q_s16(&final_output[3 * 8], input_3);
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vst1q_s16(&final_output[4 * 8], input_4);
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vst1q_s16(&final_output[5 * 8], input_5);
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vst1q_s16(&final_output[6 * 8], input_6);
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vst1q_s16(&final_output[7 * 8], input_7);
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}
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}
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@ -130,5 +130,6 @@ VP9_CX_SRCS-$(HAVE_AVX2) += encoder/x86/vp9_error_intrin_avx2.c
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VP9_CX_SRCS-$(HAVE_AVX2) += encoder/x86/vp9_variance_avx2.c
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VP9_CX_SRCS-$(HAVE_NEON) += encoder/arm/neon/vp9_sad_neon.c
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VP9_CX_SRCS-$(HAVE_NEON) += encoder/arm/neon/vp9_dct_neon.c
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VP9_CX_SRCS-yes := $(filter-out $(VP9_CX_SRCS_REMOVE-yes),$(VP9_CX_SRCS-yes))
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