Merge "Highbd fht4x4 SSE4.1 optimization for DCT_DCT mode - Setup function vp10_highbd_fht4x4_sse4_1 for highbd SSE4.1 intrinsics optimization. - Wrote SSE4.1 functions: load_buffer_4x4(), write_buffer_4x4(), and fdct4x4_sse4_1(). - Used logic right shift to avoid coeff memory write/read. - Turned on vp10_highbd_fht4x4_sse4_1 for DCT_DCT mode only. - Improved overall encoding performance >2.3% for 50 frames sequence, park_joy_1080p_12.y4m, in which, --input-bit-depth=12, --bit-depth=12, 50 frames. - Unit test passed." into nextgenv2
This commit is contained in:
Yi Luo
Gerrit Code Review
Коммит
deb33056d1
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@ -670,7 +670,7 @@ if (vpx_config("CONFIG_VP9_HIGHBITDEPTH") eq "yes") {
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# fdct functions
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add_proto qw/void vp10_highbd_fht4x4/, "const int16_t *input, tran_low_t *output, int stride, int tx_type";
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specialize qw/vp10_highbd_fht4x4/;
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specialize qw/vp10_highbd_fht4x4 sse4_1/;
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add_proto qw/void vp10_highbd_fht8x8/, "const int16_t *input, tran_low_t *output, int stride, int tx_type";
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specialize qw/vp10_highbd_fht8x8/;
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@ -202,10 +202,12 @@ void vp10_highbd_fwd_txfm_4x4(const int16_t *src_diff, tran_low_t *coeff,
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switch (tx_type) {
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case DCT_DCT:
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vp10_highbd_fht4x4(src_diff, coeff, diff_stride, tx_type);
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break;
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case ADST_DCT:
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case DCT_ADST:
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case ADST_ADST:
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vp10_highbd_fht4x4(src_diff, coeff, diff_stride, tx_type);
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vp10_highbd_fht4x4_c(src_diff, coeff, diff_stride, tx_type);
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break;
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#if CONFIG_EXT_TX
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case FLIPADST_DCT:
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@ -213,7 +215,7 @@ void vp10_highbd_fwd_txfm_4x4(const int16_t *src_diff, tran_low_t *coeff,
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case FLIPADST_FLIPADST:
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case ADST_FLIPADST:
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case FLIPADST_ADST:
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vp10_highbd_fht4x4(src_diff, coeff, diff_stride, tx_type);
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vp10_highbd_fht4x4_c(src_diff, coeff, diff_stride, tx_type);
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break;
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case V_DCT:
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case H_DCT:
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@ -0,0 +1,211 @@
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/*
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* Copyright (c) 2016 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include <assert.h>
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#include <smmintrin.h> /* SSE4.1 */
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#include "./vp10_rtcd.h"
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#include "./vpx_config.h"
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#include "vpx_dsp/txfm_common.h"
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#include "vpx_ports/mem.h"
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#if CONFIG_VP9_HIGHBITDEPTH
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static INLINE void load_buffer_4x4(const int16_t *input, __m128i *in,
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int stride, int flipud, int fliplr) {
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const __m128i k__nonzero_bias_a = _mm_setr_epi32(0, 1, 1, 1);
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const __m128i k__nonzero_bias_b = _mm_setr_epi32(1, 0, 0, 0);
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__m128i mask;
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if (!flipud) {
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in[0] = _mm_loadl_epi64((const __m128i *)(input + 0 * stride));
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in[1] = _mm_loadl_epi64((const __m128i *)(input + 1 * stride));
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in[2] = _mm_loadl_epi64((const __m128i *)(input + 2 * stride));
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in[3] = _mm_loadl_epi64((const __m128i *)(input + 3 * stride));
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} else {
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in[0] = _mm_loadl_epi64((const __m128i *)(input + 3 * stride));
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in[1] = _mm_loadl_epi64((const __m128i *)(input + 2 * stride));
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in[2] = _mm_loadl_epi64((const __m128i *)(input + 1 * stride));
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in[3] = _mm_loadl_epi64((const __m128i *)(input + 0 * stride));
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}
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if (fliplr) {
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in[0] = _mm_shufflelo_epi16(in[0], 0x1b);
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in[1] = _mm_shufflelo_epi16(in[1], 0x1b);
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in[2] = _mm_shufflelo_epi16(in[2], 0x1b);
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in[3] = _mm_shufflelo_epi16(in[3], 0x1b);
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}
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in[0] = _mm_cvtepi16_epi32(in[0]);
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in[1] = _mm_cvtepi16_epi32(in[1]);
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in[2] = _mm_cvtepi16_epi32(in[2]);
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in[3] = _mm_cvtepi16_epi32(in[3]);
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in[0] = _mm_slli_epi32(in[0], 4);
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in[1] = _mm_slli_epi32(in[1], 4);
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in[2] = _mm_slli_epi32(in[2], 4);
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in[3] = _mm_slli_epi32(in[3], 4);
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mask = _mm_cmpeq_epi32(in[0], k__nonzero_bias_a);
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in[0] = _mm_add_epi32(in[0], mask);
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in[0] = _mm_add_epi32(in[0], k__nonzero_bias_b);
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}
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static void fdct4x4_sse4_1(__m128i *in) {
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const __m128i k__cospi_p16_p16 = _mm_set1_epi64x(cospi_16_64);
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const __m128i k__cospi_m16_m16 = _mm_set1_epi64x(-cospi_16_64);
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const __m128i k__cospi_p08_p08 = _mm_set1_epi64x(cospi_8_64);
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const __m128i k__cospi_m08_m08 = _mm_set1_epi64x(-cospi_8_64);
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const __m128i k__cospi_p24_p24 = _mm_set1_epi64x(cospi_24_64);
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const __m128i k__DCT_CONST_ROUNDING = _mm_set1_epi64x(DCT_CONST_ROUNDING);
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__m128i s[8];
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__m128i u0, u1, u2, u3;
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__m128i v0, v1, v2, v3, v4, v5, v6, v7;
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s[0] = _mm_add_epi32(in[0], in[3]);
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s[1] = _mm_add_epi32(in[1], in[2]);
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s[2] = _mm_sub_epi32(in[1], in[2]);
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s[3] = _mm_sub_epi32(in[0], in[3]);
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v0 = _mm_cvtepi32_epi64(s[0]); // s01 s00
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v1 = _mm_cvtepi32_epi64(_mm_unpackhi_epi64(s[0], s[0])); // s03 s02
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v2 = _mm_cvtepi32_epi64(s[1]); // s11 s10
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v3 = _mm_cvtepi32_epi64(_mm_unpackhi_epi64(s[1], s[1])); // s13 s12
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v4 = _mm_cvtepi32_epi64(s[2]); // s21 s20
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v5 = _mm_cvtepi32_epi64(_mm_unpackhi_epi64(s[2], s[2])); // s23 s22
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v6 = _mm_cvtepi32_epi64(s[3]); // s31 s30
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v7 = _mm_cvtepi32_epi64(_mm_unpackhi_epi64(s[3], s[3])); // s33 s32
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u0 = _mm_mul_epi32(v0, k__cospi_p16_p16);
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u1 = _mm_mul_epi32(v1, k__cospi_p16_p16);
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u2 = _mm_mul_epi32(v2, k__cospi_p16_p16);
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u3 = _mm_mul_epi32(v3, k__cospi_p16_p16);
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s[0] = _mm_add_epi64(u0, u2); // y10 y00
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s[1] = _mm_add_epi64(u1, u3); // y30 y20
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u2 = _mm_mul_epi32(v2, k__cospi_m16_m16);
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u3 = _mm_mul_epi32(v3, k__cospi_m16_m16);
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s[2] = _mm_add_epi64(u0, u2); // y12 y02
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s[3] = _mm_add_epi64(u1, u3); // y32 y22
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u0 = _mm_mul_epi32(v6, k__cospi_p08_p08);
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u1 = _mm_mul_epi32(v5, k__cospi_p24_p24);
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u2 = _mm_mul_epi32(v4, k__cospi_p24_p24);
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u3 = _mm_mul_epi32(v7, k__cospi_p08_p08);
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s[4] = _mm_add_epi64(u0, u2); // y11 y01
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s[5] = _mm_add_epi64(u1, u3); // y31 y21
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u0 = _mm_mul_epi32(v4, k__cospi_m08_m08);
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u1 = _mm_mul_epi32(v5, k__cospi_m08_m08);
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u2 = _mm_mul_epi32(v6, k__cospi_p24_p24);
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u3 = _mm_mul_epi32(v7, k__cospi_p24_p24);
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s[6] = _mm_add_epi64(u0, u2); // y13 y03
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s[7] = _mm_add_epi64(u1, u3); // y33 y23
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s[0] = _mm_add_epi64(s[0], k__DCT_CONST_ROUNDING);
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s[1] = _mm_add_epi64(s[1], k__DCT_CONST_ROUNDING);
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s[2] = _mm_add_epi64(s[2], k__DCT_CONST_ROUNDING);
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s[3] = _mm_add_epi64(s[3], k__DCT_CONST_ROUNDING);
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s[4] = _mm_add_epi64(s[4], k__DCT_CONST_ROUNDING);
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s[5] = _mm_add_epi64(s[5], k__DCT_CONST_ROUNDING);
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s[6] = _mm_add_epi64(s[6], k__DCT_CONST_ROUNDING);
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s[7] = _mm_add_epi64(s[7], k__DCT_CONST_ROUNDING);
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s[0] = _mm_srli_epi64(s[0], DCT_CONST_BITS);
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s[1] = _mm_srli_epi64(s[1], DCT_CONST_BITS);
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s[2] = _mm_srli_epi64(s[2], DCT_CONST_BITS);
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s[3] = _mm_srli_epi64(s[3], DCT_CONST_BITS);
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s[4] = _mm_srli_epi64(s[4], DCT_CONST_BITS);
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s[5] = _mm_srli_epi64(s[5], DCT_CONST_BITS);
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s[6] = _mm_srli_epi64(s[6], DCT_CONST_BITS);
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s[7] = _mm_srli_epi64(s[7], DCT_CONST_BITS);
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s[0] = _mm_shuffle_epi32(s[0], 0x88);
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s[1] = _mm_shuffle_epi32(s[1], 0x88);
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s[2] = _mm_shuffle_epi32(s[2], 0x88);
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s[3] = _mm_shuffle_epi32(s[3], 0x88);
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s[4] = _mm_shuffle_epi32(s[4], 0x88);
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s[5] = _mm_shuffle_epi32(s[5], 0x88);
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s[6] = _mm_shuffle_epi32(s[6], 0x88);
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s[7] = _mm_shuffle_epi32(s[7], 0x88);
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v0 = _mm_unpacklo_epi32(s[0], s[4]);
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v1 = _mm_unpacklo_epi32(s[2], s[6]);
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v2 = _mm_unpacklo_epi32(s[1], s[5]);
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v3 = _mm_unpacklo_epi32(s[3], s[7]);
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in[0] = _mm_unpacklo_epi64(v0, v1);
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in[1] = _mm_unpackhi_epi64(v0, v1);
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in[2] = _mm_unpacklo_epi64(v2, v3);
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in[3] = _mm_unpackhi_epi64(v2, v3);
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}
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static INLINE void write_buffer_4x4(tran_low_t *output, __m128i *res) {
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const __m128i kOne = _mm_set1_epi32(1);
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res[0] = _mm_add_epi32(res[0], kOne);
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res[1] = _mm_add_epi32(res[1], kOne);
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res[2] = _mm_add_epi32(res[2], kOne);
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res[3] = _mm_add_epi32(res[3], kOne);
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res[0] = _mm_srai_epi32(res[0], 2);
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res[1] = _mm_srai_epi32(res[1], 2);
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res[2] = _mm_srai_epi32(res[2], 2);
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res[3] = _mm_srai_epi32(res[3], 2);
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_mm_store_si128((__m128i *)(output + 0 * 4), res[0]);
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_mm_store_si128((__m128i *)(output + 1 * 4), res[1]);
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_mm_store_si128((__m128i *)(output + 2 * 4), res[2]);
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_mm_store_si128((__m128i *)(output + 3 * 4), res[3]);
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}
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void vp10_highbd_fht4x4_sse4_1(const int16_t *input, tran_low_t *output,
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int stride, int tx_type) {
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__m128i in[4];
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switch (tx_type) {
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case DCT_DCT:
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load_buffer_4x4(input, in, stride, 0, 0);
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fdct4x4_sse4_1(in);
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fdct4x4_sse4_1(in);
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write_buffer_4x4(output, in);
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break;
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case ADST_DCT:
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case DCT_ADST:
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case ADST_ADST:
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vp10_highbd_fht4x4_c(input, output, stride, tx_type);
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break;
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#if CONFIG_EXT_TX
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case FLIPADST_DCT:
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case DCT_FLIPADST:
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case FLIPADST_FLIPADST:
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case ADST_FLIPADST:
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case FLIPADST_ADST:
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vp10_highbd_fht4x4_c(input, output, stride, tx_type);
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break;
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case DST_DST:
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case DCT_DST:
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case DST_DCT:
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case DST_ADST:
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case ADST_DST:
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case DST_FLIPADST:
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case FLIPADST_DST:
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vp10_highbd_fht4x4_c(input, output, stride, tx_type);
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break;
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#endif // CONFIG_EXT_TX
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default:
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assert(0);
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}
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}
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#endif // CONFIG_VP9_HIGHBITDEPTH
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@ -112,6 +112,7 @@ endif
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VP10_CX_SRCS-$(HAVE_SSE2) += encoder/x86/dct_sse2.c
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VP10_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/dct_ssse3.c
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VP10_CX_SRCS-$(HAVE_SSE4_1) += encoder/x86/highbd_fwd_txfm_sse4.c
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ifeq ($(CONFIG_VP9_TEMPORAL_DENOISING),yes)
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VP10_CX_SRCS-$(HAVE_SSE2) += encoder/x86/denoiser_sse2.c
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