- Interface function takes a local MxN function to call based on the
block size.
- Repetition call (w/o cache line miss) shows improvement:
~63% - ~340%.
- Overall encoder speed improvement: ~0.9%.
Change-Id: Ieff8f3d192415c61d6d58d8b99bb2a722004823f
The uncompressed frame header contains a bit to signal whether the
frame is encoded using 64x64 or 128x128 superblocks. This can vary
between any 2 frames.
vpxenc gained the --sb-size={64,128,dynamic} option, which allows the
configuration of the superblock size used (default is dynamic). 64/128
will force the encoder to always use the specified superblock size.
Dynamic would enable the encoder to choose the sb size for each
frame, but this is not implemented yet (dynamic does the same as 128
for now).
Constraints on tile sizes depend on the superblock size, the following
is a summary of the current bitstream syntax and semantics:
If both --enable-ext-tile is OFF and --enable-ext-partition is OFF:
The tile coding in this case is the same as VP9. In particular,
tiles have a minimum width of 256 pixels and a maximum width of
4096 pixels. The tile width must be multiples of 64 pixels
(except for the rightmost tile column). There can be a maximum
of 64 tile columns and 4 tile rows.
If --enable-ext-tile is OFF and --enable-ext-partition is ON:
Same constraints as above, except that tile width must be
multiples of 128 pixels (except for the rightmost tile column).
There is no change in the bitstream syntax used for coding the tile
configuration if --enable-ext-tile is OFF.
If --enable-ext-tile is ON and --enable-ext-partition is ON:
This is the new large scale tile coding configuration. The
minimum/maximum tile width and height are 64/4096 pixels. Tile
width and height must be multiples of 64 pixels. The uncompressed
header contains two 6 bit fields that hold the tile width/heigh
in units of 64 pixels. The maximum number of tile rows/columns
is only limited by the maximum frame size of 65536x65536 pixels
that can be coded in the bitstream. This yields a maximum of
1024x1024 tile rows and columns (of 64x64 tiles in a 65536x65536
frame).
If both --enable-ext-tile is ON and --enable-ext-partition is ON:
Same applies as above, except that in the bitstream the 2 fields
containing the tile width/height are in units of the superblock
size, and the superblock size itself is also coded in the bitstream.
If the uncompressed header signals the use of 64x64 superblocks,
then the tile width/height fields are 6 bits wide and are in units
of 64 pixels. If the uncompressed header signals the use of 128x128
superblocks, then the tile width/height fields are 5 bits wide and
are in units of 128 pixels.
The above is a summary of the bitstream. The user interface to vpxenc
(and the equivalent encoder API) behaves a follows:
If --enable-ext-tile is OFF:
No change in the user interface. --tile-columns and --tile-rows
specify the base 2 logarithm of the desired number of tile columns
and tile rows. The actual number of tile rows and tile columns,
and the particular tile width and tile height are computed by the
codec ensuring all of the above constraints are respected.
If --enable-ext-tile is ON, but --enable-ext-partition is OFF:
No change in the user interface. --tile-columns and --tile-rows
specify the WIDTH and HEIGHT of the tiles in unit of 64 pixels.
The valid values are in the range [1, 64] (which corresponds to
[64, 4096] pixels in increments of 64.
If both --enable-ext-tile is ON and --enable-ext-partition is ON:
If --sb-size=64 (default):
The user interface is the same as in the previous point.
--tile-columns and --tile-rows specify tile WIDTH and HEIGHT,
in units of 64 pixels, in the range [1, 64] (which corresponds
to [64, 4096] pixels in increments of 64).
If --sb-size=128 or --sb-size=dynamic:
--tile-columns and --tile-rows specify tile WIDTH and HEIGHT,
in units of 128 pixels in the range [1, 32] (which corresponds
to [128, 4096] pixels in increments of 128).
Change-Id: Idc9beee1ad12ff1634e83671985d14c680f9179a
only output[0] needs to be set, store_output is more involved than a
movdqa in the high bitdepth case
Change-Id: I2cbd85d7cf74688bdf47eb767934fe42e02bff67
If --enable-ext-partition is used at build time, the superblock size
(sometimes also referred to as coding unit (CU) size) is extended to
128x128 pixels.
Change-Id: Ie09cec6b7e8d765b7555ff5d80974aab60803f3a
Optimized 2 up-sampled reference prediction functions in high-bit
depth case. This reduced the HBD encoding time by 3%.
Change-Id: I8663ffb5234f5e70168c0fc9ca676309fe8e98f2
Using the up-sampled reference frames in sub-pixel motion search is
enabled as a speed feature for good-quality mode speed 0 and speed 1.
Change-Id: Ieb454bf8c646ddb99e87bd64c8e74dbd78d84a50
Up-sampled the reference frames to 8 times in each dimension using
the 8-tap interpolation filter. In sub-pixel motion search, use the
up-sampled reference frames to find the best matching blocks. This
largely improved the motion search precision, and thus, improved
the compression quality. There was no change in decoder side.
Borg test and speed test results:
1. On derflr set,
Overall PSNR gain: 1.306%, and SSIM gain: 1.512%.
Average speed loss on derf set was 6.0%.
2. On stdhd set,
Overall PSNR gain: 0.754%, and SSIM gain: 0.814%.
On hevchd set,
Overall PSNR gain: 0.465%, and SSIM gain: 0.527%.
Speed loss on HD clips was 3.5%.
Change-Id: I300ebaafff57e88914f3dedc8784cb21d316b04f
This commits adds a shift stage for FASTSSIM computaton when source
bit depth is different from working bit depth, to make sure metric
results are calculated in bit_depth consistent with source.
Change-Id: I997799634076ef7b00fd051710544681ed536185
This commit adds the ability to shift down the working buffer when
source bit_depth is different than working bit_depth. It does so
by shift down to be consistent with source bit_depth.
Change-Id: Idfdbfc614d73fe445d62e35e642cc7d75e9dc4ff
This makes all metric computation to locate at some place, also gets
rid of duplicate code between vp9 and vp10.
Change-Id: I24a2707d183a2419cd18a8343010adae185ffcd4
Adds new 32x32 masked 1-d transforms that combine 1-D length-16
DCT with length-16 identity transforms.
To be continued in subsequent patches.
Change-Id: I0b4f66492d44c079b3c3b531ba48a97201de1484
replace with vpx_highbd_lpf_horizontal_edge_16 and
vpx_highbd_lpf_horizontal_edge_8 to avoid passing a count parameter
Change-Id: I551f8cec0fce57032cb2652584bb802e2248644d
replace with vpx_lpf_horizontal_edge_16 and vpx_lpf_horizontal_edge_8 to
avoid passing a count parameter
Change-Id: I848c95c02a3c6ebaa6c2bdf0983dce05cd645271
Using this we can eliminate large numbers of calls to predict intra,
and is also faster than most of the variance functions it replaces.
This is an equivalence transform so coding performance is unaffected.
Encoder speedup is approx 7% when var_tx, super_tx and ext_tx are all
enabled.
Change-Id: I0d4c83afc4a97a1826f3abd864bd68e41bb504fb
This commit adds computation of PSNRHVS for highbitdepth build, it
also adds tests to make sure the calculation of psnrhvs metric for
10 and 12 bit correct.
Change-Id: Iac8a8073d2b3e3ba5d368829d770793212fa63b6
This commit adds the computation of fastSSIM for highbitdepth build,
it also modifies the hbdmetric test to be more generic and applicable
for fastSSIM.
The 255 used for calculating ssim constants c1 and c2 is not exactly
scaled by 4x and 16x to 1023 and 4095, therefore requries the metric
test to have a thresold more tolerant than 0, currently at 0.03dB.
Change-Id: I631829da7773de400e77fc36004156e5e126c7e0
There were a number of compiler warnings:
1. int16_t to uint8_t in recon_intra.c;
2. double to float conversions in psnrhvs.c
3. intptr_t to int in quantize.c
4. size_t to int32_t in decoder.c
Change-Id: Id95423b17779dcfa6cf39d9a90fe8cb8b910f5df
the results along the top and left border are then stored with a moving
window into the vector.
~40-67% faster on ARM, ~40-77+% on x86 depending on the block size.
Change-Id: Iab369aa2946a3ae4eb7290d512868fe5db92dbc8
Temporaly disable warning for unused function for vp10, needs clean
out the warnings before re-enable the flag for vp10.
Change-Id: I5636f8cd607423f6ea6963db9c2cbd688e30b495
This commit changes SSSE3 optimized idct8x8 functions to work with
highbitdepth build.
With this commit and the previous one that enabled SSSE3 idct32x32
functions, tests showed virtually no difference on decoding speed for
file fdJc1_IBKJA.248.webm for the build with -enable-vp9-highbitdpeth
option and the build without the option.
Change-Id: Ibe0634149ec70e8b921e6b30171664b8690a9c45
This commit changes the SSSE3 assembly functions for idct32x32 to
support highbitdepth build.
On test clip fdJc1_IBKJA.248.webm, this cuts the speed difference
between hbd and lbd build from between 3-4% to 1-2%.
Change-Id: Ic3390e0113bc1ca5bba8ec80d1795ad31b484fca
This reverts commit ea48370a50, reversing
changes made to 15939cb2d7.
The commit was insufficiently tested and causes failures.
Change-Id: I623d6fc2cd3ae6fd42d0abab1f8eada465ae57a7
reduce the register count by 1 to avoid xmm6 and unnecessarily
penalizing the other users of the base macro
Change-Id: I59605c9a41a31c1b74f67ec06a40d1a7f92c4699
In 32-bit build with --enable-shared, there is a lot of
register pressure and register src_strideq is reused.
The code needs to use the stack based version of src_stride,
but this doesn't compile when used in an lea instruction.
This patch also fixes a related segmentation fault caused by the
implementation using src_strideq even though it has been
reused.
This patch also fixes the HBD subpel variance tests that fail
when compiled without disable-optimizations.
These failures were caused by local variables in the assembler
routines colliding with the caller's stack frame.
Change-Id: Ice9d4dafdcbdc6038ad5ee7c1c09a8f06deca362
Reallocate the xmm register usage so that no ARCH_X86_64 required.
Reduce memory access to the left neighbor by half.
Speed up by single digit on big core machine.
Change-Id: I392515ed8e8aeb02e6a717b3966b1ba13f5be990
GET_GOT modifies the stack pointer so the offset for left's address will
be wrong if loaded afterword.
Change-Id: Iff9433aec45f5f6fe1a59ed8080c589bad429536
Relocate the function from SSSE3 to SSE2, Unroll loop from 16 to 8,
and reduce mem access to left.
Speed up by single digit in ./test_intra_pred_speed on big core
machines.
Change-Id: I2b7fc95ffc0c42145be2baca4dc77116dff1c960
4x4 Intra predictor implemented with MMX is replaced with SSE2.
Segfault in change 315561 when decoding vp8 is taken care of.
Change-Id: I083a7cb4eb8982954c20865160f91ebec777ec76
Relocate the function from SSSE3 to SSE2, Unroll loop from 8 to 4,
and reduce mem access to left.
Speed up by >20% in ./test_intra_pred_speed.
Change-Id: Ie48229c2e32404706b722442942c84983bda74cc
Relocate the function from SSSE3 to SSE2, Unroll loop from 4 to 2,
and reduce mem access to left.
Speed up by >20% in ./test_intra_pred_speed.
Change-Id: Ib9f1846819783b6e05e2a310c930eb844b2b4d2e
Reduce mem access to left. Speed up by 10% in ./test_intra_pred_speed
with the same instruction size.
Change-Id: Ia33689d62476972cc82ebb06b50415aeccc95d15
Relocate h_predictor_4x4 from SSSE3 to SSE2 with XMM registers.
Speed up by ~25% in ./test_intra_pred_speed.
Change-Id: I64e14c13b482a471449be3559bfb0da45cf88d9d
Always round sum error and sum square error toward zero in variance
calculations. This prevents variance from becoming negative.
Avoiding rounding variance at all might be better but would be far
more invasive.
Change-Id: Icf24e0e75ff94952fc026ba6a4d26adf8d373f1c
Johann
Yi Luo
Debargha Mukherjee
Geza Lore
James Zern
Yaowu Xu
Yunqing Wang
Scott LaVarnway
hui su
Alex Converse
Jian Zhou
Peter de Rivaz
Johann Koenig
Sergey Kolomenkin