Brennan Shacklett f975ac57b0 Temporary fix for 4X8 block intra prediction. ... Currently the RD loop traverses 4X8 blocks in inverted N order while the bitstream stores blocks smaller than 8x8 in Z order. This causes a discrepancy where the RD loop reads uninitialized data while performing intra prediction. As a temporary fix simply disable the use of the extended right edge for 4X8 blocks, until the bitstream can be changed to match the logical structure of the blocks. Change-Id: I44a9e4fc1a15cd551a7b38c3c1227bc5dac77e9a		2016-08-04 18:01:36 +00:00
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common	Temporary fix for 4X8 block intra prediction.	2016-08-04 18:01:36 +00:00
decoder	Update partition_cdf per frame.	2016-07-28 20:52:32 +00:00
encoder	Linearize extrabits writing.	2016-08-02 15:46:24 +00:00
av1_common.mk	Move simd optimization of 10/12 taps convolve function to AOM	2016-07-22 10:36:13 -07:00
av1_cx.mk	New CLPF: New kernel and RDO for strength and block size	2016-07-15 15:28:17 +00:00
av1_cx_iface.c	Add the use of new reference frames at encoder in EXT_REFS	2016-07-13 17:35:37 -07:00
av1_dx.mk	Add copyright notice to .mk files	2016-03-29 09:36:13 -07:00
av1_dx_iface.c	Fix warnings reported by -Wshadow: Part2: av1 directory	2016-07-25 14:24:51 -07:00
av1_iface_common.h	Rename AOM_ENC/DEC_BORDER_IN_PIXELS to AOM_BORDER_IN_PIXELS	2016-06-08 00:59:23 +00:00
exports_dec	Change "vp10" to "av1" in source code	2016-03-25 12:43:01 -07:00
exports_enc	Change "vp10" to "av1" in source code	2016-03-25 12:43:01 -07:00