153 строки
6.4 KiB
C
153 строки
6.4 KiB
C
/*
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* Copyright (c) 2016, Alliance for Open Media. All rights reserved
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*
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* This source code is subject to the terms of the BSD 2 Clause License and
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* the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
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* was not distributed with this source code in the LICENSE file, you can
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* obtain it at www.aomedia.org/license/software. If the Alliance for Open
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* Media Patent License 1.0 was not distributed with this source code in the
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* PATENTS file, you can obtain it at www.aomedia.org/license/patent.
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*/
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#include "aom_dsp/aom_dsp_common.h"
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void aom_idct16x16_256_add_neon_pass1(const int16_t *input, int16_t *output,
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int output_stride);
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void aom_idct16x16_256_add_neon_pass2(const int16_t *src, int16_t *output,
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int16_t *pass1Output, int16_t skip_adding,
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uint8_t *dest, int dest_stride);
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void aom_idct16x16_10_add_neon_pass1(const int16_t *input, int16_t *output,
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int output_stride);
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void aom_idct16x16_10_add_neon_pass2(const int16_t *src, int16_t *output,
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int16_t *pass1Output, int16_t skip_adding,
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uint8_t *dest, int dest_stride);
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#if HAVE_NEON_ASM
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/* For ARM NEON, d8-d15 are callee-saved registers, and need to be saved. */
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extern void aom_push_neon(int64_t *store);
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extern void aom_pop_neon(int64_t *store);
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#endif // HAVE_NEON_ASM
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void aom_idct16x16_256_add_neon(const int16_t *input, uint8_t *dest,
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int dest_stride) {
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#if HAVE_NEON_ASM
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int64_t store_reg[8];
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#endif
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int16_t pass1_output[16 * 16] = { 0 };
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int16_t row_idct_output[16 * 16] = { 0 };
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#if HAVE_NEON_ASM
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// save d8-d15 register values.
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aom_push_neon(store_reg);
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#endif
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/* Parallel idct on the upper 8 rows */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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aom_idct16x16_256_add_neon_pass1(input, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7
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// which will be saved into row_idct_output.
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aom_idct16x16_256_add_neon_pass2(input + 1, row_idct_output, pass1_output, 0,
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dest, dest_stride);
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/* Parallel idct on the lower 8 rows */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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aom_idct16x16_256_add_neon_pass1(input + 8 * 16, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7
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// which will be saved into row_idct_output.
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aom_idct16x16_256_add_neon_pass2(input + 8 * 16 + 1, row_idct_output + 8,
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pass1_output, 0, dest, dest_stride);
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/* Parallel idct on the left 8 columns */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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aom_idct16x16_256_add_neon_pass1(row_idct_output, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7.
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// Then add the result to the destination data.
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aom_idct16x16_256_add_neon_pass2(row_idct_output + 1, row_idct_output,
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pass1_output, 1, dest, dest_stride);
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/* Parallel idct on the right 8 columns */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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aom_idct16x16_256_add_neon_pass1(row_idct_output + 8 * 16, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7.
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// Then add the result to the destination data.
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aom_idct16x16_256_add_neon_pass2(row_idct_output + 8 * 16 + 1,
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row_idct_output + 8, pass1_output, 1,
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dest + 8, dest_stride);
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#if HAVE_NEON_ASM
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// restore d8-d15 register values.
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aom_pop_neon(store_reg);
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#endif
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return;
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}
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void aom_idct16x16_10_add_neon(const int16_t *input, uint8_t *dest,
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int dest_stride) {
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#if HAVE_NEON_ASM
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int64_t store_reg[8];
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#endif
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int16_t pass1_output[16 * 16] = { 0 };
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int16_t row_idct_output[16 * 16] = { 0 };
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#if HAVE_NEON_ASM
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// save d8-d15 register values.
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aom_push_neon(store_reg);
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#endif
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/* Parallel idct on the upper 8 rows */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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aom_idct16x16_10_add_neon_pass1(input, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7
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// which will be saved into row_idct_output.
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aom_idct16x16_10_add_neon_pass2(input + 1, row_idct_output, pass1_output, 0,
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dest, dest_stride);
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/* Skip Parallel idct on the lower 8 rows as they are all 0s */
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/* Parallel idct on the left 8 columns */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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aom_idct16x16_256_add_neon_pass1(row_idct_output, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7.
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// Then add the result to the destination data.
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aom_idct16x16_256_add_neon_pass2(row_idct_output + 1, row_idct_output,
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pass1_output, 1, dest, dest_stride);
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/* Parallel idct on the right 8 columns */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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aom_idct16x16_256_add_neon_pass1(row_idct_output + 8 * 16, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7.
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// Then add the result to the destination data.
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aom_idct16x16_256_add_neon_pass2(row_idct_output + 8 * 16 + 1,
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row_idct_output + 8, pass1_output, 1,
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dest + 8, dest_stride);
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#if HAVE_NEON_ASM
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// restore d8-d15 register values.
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aom_pop_neon(store_reg);
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#endif
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return;
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}
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